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GET /api/patches/1191874/?format=api
{ "id": 1191874, "url": "http://patchwork.ozlabs.org/api/patches/1191874/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20191108130123.6839-4-linux@rasmusvillemoes.dk/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20191108130123.6839-4-linux@rasmusvillemoes.dk>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20191108130123.6839-4-linux@rasmusvillemoes.dk/", "date": "2019-11-08T13:00:39", "name": "[v4,03/47] soc: fsl: qe: rename qe_(clr/set/clrset)bit* helpers", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "70e92b74bd3ac39c8e44e3f5897befef90d13c19", "submitter": { "id": 27394, "url": "http://patchwork.ozlabs.org/api/people/27394/?format=api", "name": "Rasmus Villemoes", "email": "linux@rasmusvillemoes.dk" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20191108130123.6839-4-linux@rasmusvillemoes.dk/mbox/", "series": [ { "id": 141654, "url": "http://patchwork.ozlabs.org/api/series/141654/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=141654", "date": "2019-11-08T13:00:38", "name": "QUICC Engine support on ARM and ARM64", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/141654/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1191874/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1191874/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\tkey-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 478gjg14BJz9s7T\n\tfor <patchwork-incoming@ozlabs.org>;\n\tSat, 9 Nov 2019 00:15:03 +1100 (AEDT)", "from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 478gjf0cT2zF6C2\n\tfor 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"X-Gm-Message-State": "APjAAAW784R3B+lRka2l20sDaJUAT6EEQl+4/bbJu0sDVPQhf2RYSspZ\n\tfNr4Q1or2TgcEngvI7ORLMVTYEFsGE1MWehA", "X-Google-Smtp-Source": "APXvYqwHe/94bHQUIiS2PHM5f7Vm4tOkuQQeHPPg8bsOABWlpDnKO27QowlfW02ScK7V7DeZLJYQpw==", "X-Received": "by 2002:a2e:3805:: with SMTP id f5mr6440382lja.220.1573218091677;\n\tFri, 08 Nov 2019 05:01:31 -0800 (PST)", "From": "Rasmus Villemoes <linux@rasmusvillemoes.dk>", "To": "Qiang Zhao <qiang.zhao@nxp.com>, Li Yang <leoyang.li@nxp.com>,\n\tChristophe Leroy <christophe.leroy@c-s.fr>", "Subject": "[PATCH v4 03/47] soc: fsl: qe: rename qe_(clr/set/clrset)bit*\n\thelpers", "Date": "Fri, 8 Nov 2019 14:00:39 +0100", "Message-Id": "<20191108130123.6839-4-linux@rasmusvillemoes.dk>", "X-Mailer": "git-send-email 2.23.0", "In-Reply-To": "<20191108130123.6839-1-linux@rasmusvillemoes.dk>", "References": "<20191108130123.6839-1-linux@rasmusvillemoes.dk>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Cc": "netdev@vger.kernel.org, Rasmus Villemoes <linux@rasmusvillemoes.dk>,\n\tlinux-kernel@vger.kernel.org, Scott Wood <oss@buserror.net>,\n\tlinuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "Make it clear that these operate on big-endian registers (i.e. use the\niowrite*be primitives) before we introduce more uses of them and allow\nthe QE drivers to be built for platforms other than ppc32.\n\nSigned-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>\n---\n drivers/net/wan/fsl_ucc_hdlc.c | 4 ++--\n drivers/soc/fsl/qe/ucc.c | 10 +++++-----\n include/soc/fsl/qe/qe.h | 18 +++++++++---------\n 3 files changed, 16 insertions(+), 16 deletions(-)", "diff": "diff --git a/drivers/net/wan/fsl_ucc_hdlc.c b/drivers/net/wan/fsl_ucc_hdlc.c\nindex ca0f3be2b6bf..ce6af7d5380f 100644\n--- a/drivers/net/wan/fsl_ucc_hdlc.c\n+++ b/drivers/net/wan/fsl_ucc_hdlc.c\n@@ -623,8 +623,8 @@ static int ucc_hdlc_poll(struct napi_struct *napi, int budget)\n \n \tif (howmany < budget) {\n \t\tnapi_complete_done(napi, howmany);\n-\t\tqe_setbits32(priv->uccf->p_uccm,\n-\t\t\t (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS) << 16);\n+\t\tqe_setbits_be32(priv->uccf->p_uccm,\n+\t\t\t\t(UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS) << 16);\n \t}\n \n \treturn howmany;\ndiff --git a/drivers/soc/fsl/qe/ucc.c b/drivers/soc/fsl/qe/ucc.c\nindex 024d239ac1e1..ae9f2cf560cb 100644\n--- a/drivers/soc/fsl/qe/ucc.c\n+++ b/drivers/soc/fsl/qe/ucc.c\n@@ -540,8 +540,8 @@ int ucc_set_tdm_rxtx_clk(u32 tdm_num, enum qe_clock clock,\n \tcmxs1cr = (tdm_num < 4) ? &qe_mux_reg->cmxsi1cr_l :\n \t\t\t\t &qe_mux_reg->cmxsi1cr_h;\n \n-\tqe_clrsetbits32(cmxs1cr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,\n-\t\t\tclock_bits << shift);\n+\tqe_clrsetbits_be32(cmxs1cr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,\n+\t\t\t clock_bits << shift);\n \n \treturn 0;\n }\n@@ -650,9 +650,9 @@ int ucc_set_tdm_rxtx_sync(u32 tdm_num, enum qe_clock clock,\n \n \tshift = ucc_get_tdm_sync_shift(mode, tdm_num);\n \n-\tqe_clrsetbits32(&qe_mux_reg->cmxsi1syr,\n-\t\t\tQE_CMXUCR_TX_CLK_SRC_MASK << shift,\n-\t\t\tsource << shift);\n+\tqe_clrsetbits_be32(&qe_mux_reg->cmxsi1syr,\n+\t\t\t QE_CMXUCR_TX_CLK_SRC_MASK << shift,\n+\t\t\t source << shift);\n \n \treturn 0;\n }\ndiff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h\nindex c1036d16ed03..a1aa4eb28f0c 100644\n--- a/include/soc/fsl/qe/qe.h\n+++ b/include/soc/fsl/qe/qe.h\n@@ -241,20 +241,20 @@ static inline int qe_alive_during_sleep(void)\n #define qe_muram_offset cpm_muram_offset\n #define qe_muram_dma cpm_muram_dma\n \n-#define qe_setbits32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr))\n-#define qe_clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))\n+#define qe_setbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr))\n+#define qe_clrbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))\n \n-#define qe_setbits16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr))\n-#define qe_clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))\n+#define qe_setbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr))\n+#define qe_clrbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))\n \n-#define qe_setbits8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr))\n-#define qe_clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))\n+#define qe_setbits_8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr))\n+#define qe_clrbits_8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))\n \n-#define qe_clrsetbits32(addr, clear, set) \\\n+#define qe_clrsetbits_be32(addr, clear, set) \\\n \tiowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))\n-#define qe_clrsetbits16(addr, clear, set) \\\n+#define qe_clrsetbits_be16(addr, clear, set) \\\n \tiowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))\n-#define qe_clrsetbits8(addr, clear, set) \\\n+#define qe_clrsetbits_8(addr, clear, set) \\\n \tiowrite8((ioread8(addr) & ~(clear)) | (set), (addr))\n \n /* Structure that defines QE firmware binary files.\n", "prefixes": [ "v4", "03/47" ] }