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{
    "id": 1182401,
    "url": "http://patchwork.ozlabs.org/api/patches/1182401/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20191023182253.1115-13-shiraz.saleem@intel.com/",
    "project": {
        "id": 46,
        "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api",
        "name": "Intel Wired Ethernet development",
        "link_name": "intel-wired-lan",
        "list_id": "intel-wired-lan.osuosl.org",
        "list_email": "intel-wired-lan@osuosl.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20191023182253.1115-13-shiraz.saleem@intel.com>",
    "list_archive_url": null,
    "date": "2019-10-23T18:22:48",
    "name": "[rdma-nxt,12/16] RDMA/irdma: Add miscellaneous utility definitions",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": false,
    "hash": "a5478dead3d5ac61f902b850e353eca1909fa1a7",
    "submitter": {
        "id": 69500,
        "url": "http://patchwork.ozlabs.org/api/people/69500/?format=api",
        "name": "Saleem, Shiraz",
        "email": "shiraz.saleem@intel.com"
    },
    "delegate": {
        "id": 68,
        "url": "http://patchwork.ozlabs.org/api/users/68/?format=api",
        "username": "jtkirshe",
        "first_name": "Jeff",
        "last_name": "Kirsher",
        "email": "jeffrey.t.kirsher@intel.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20191023182253.1115-13-shiraz.saleem@intel.com/mbox/",
    "series": [
        {
            "id": 138160,
            "url": "http://patchwork.ozlabs.org/api/series/138160/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=138160",
            "date": "2019-10-23T18:22:36",
            "name": "Add unified Intel Ethernet RDMA driver (irdma)",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/138160/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1182401/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1182401/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<intel-wired-lan-bounces@osuosl.org>",
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            "from ssaleem-mobl.amr.corp.intel.com ([10.122.128.45])\n\tby fmsmga002.fm.intel.com with ESMTP; 23 Oct 2019 11:37:57 -0700"
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        "X-IronPort-AV": "E=Sophos;i=\"5.68,221,1569308400\"; d=\"scan'208\";a=\"228225085\"",
        "From": "Shiraz Saleem <shiraz.saleem@intel.com>",
        "To": "intel-wired-lan@lists.osuosl.org",
        "Date": "Wed, 23 Oct 2019 13:22:48 -0500",
        "Message-Id": "<20191023182253.1115-13-shiraz.saleem@intel.com>",
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        "In-Reply-To": "<20191023182253.1115-1-shiraz.saleem@intel.com>",
        "References": "<20191023182253.1115-1-shiraz.saleem@intel.com>",
        "MIME-Version": "1.0",
        "Subject": "[Intel-wired-lan] [PATCH rdma-nxt 12/16] RDMA/irdma: Add\n\tmiscellaneous utility definitions",
        "X-BeenThere": "intel-wired-lan@osuosl.org",
        "X-Mailman-Version": "2.1.29",
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        "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>",
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        "Cc": "Mustafa Ismail <mustafa.ismail@intel.com>,\n\tShiraz Saleem <shiraz.saleem@intel.com>",
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    },
    "content": "From: Mustafa Ismail <mustafa.ismail@intel.com>\n\nAdd miscellaneous utility functions and headers.\n\nSigned-off-by: Mustafa Ismail <mustafa.ismail@intel.com>\nSigned-off-by: Shiraz Saleem <shiraz.saleem@intel.com>\n---\n drivers/infiniband/hw/irdma/osdep.h  |  107 ++\n drivers/infiniband/hw/irdma/protos.h |   96 ++\n drivers/infiniband/hw/irdma/status.h |   70 +\n drivers/infiniband/hw/irdma/utils.c  | 2335 ++++++++++++++++++++++++++++++++++\n 4 files changed, 2608 insertions(+)\n create mode 100644 drivers/infiniband/hw/irdma/osdep.h\n create mode 100644 drivers/infiniband/hw/irdma/protos.h\n create mode 100644 drivers/infiniband/hw/irdma/status.h\n create mode 100644 drivers/infiniband/hw/irdma/utils.c",
    "diff": "diff --git a/drivers/infiniband/hw/irdma/osdep.h b/drivers/infiniband/hw/irdma/osdep.h\nnew file mode 100644\nindex 0000000..00b0005\n--- /dev/null\n+++ b/drivers/infiniband/hw/irdma/osdep.h\n@@ -0,0 +1,107 @@\n+/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */\n+/* Copyright (c) 2019, Intel Corporation. */\n+\n+#ifndef IRDMA_OSDEP_H\n+#define IRDMA_OSDEP_H\n+\n+#include <linux/version.h>\n+#include <linux/kernel.h>\n+#include <linux/vmalloc.h>\n+#include <linux/string.h>\n+#include <linux/bitops.h>\n+#include <linux/pci.h>\n+#include <net/tcp.h>\n+#include <crypto/hash.h>\n+/* get readq/writeq support for 32 bit kernels, use the low-first version */\n+#include <linux/io-64-nonatomic-lo-hi.h>\n+\n+#define STATS_TIMER_DELAY\t60000\n+#define rfdev_to_dev(ptr)\t(&((ptr)->hw->pdev->dev))\n+#define to_ibdev(iwdev)\t\t(&((iwdev)->iwibdev->ibdev))\n+#define hw_to_dev(hw)\t\t(&(hw)->pdev->dev)\n+#define irdma_debug_buf(dev, prefix, desc, buf, size)\t\\\n+\tprint_hex_dump_debug(prefix \": \" desc \" \",\t\\\n+\t\t\t     DUMP_PREFIX_OFFSET,\t\\\n+\t\t\t     16, 8, buf, size, false)\n+\n+struct irdma_dma_info {\n+\tdma_addr_t *dmaaddrs;\n+};\n+\n+struct irdma_dma_mem {\n+\tvoid *va;\n+\tdma_addr_t pa;\n+\tu32 size;\n+} __packed;\n+\n+struct irdma_virt_mem {\n+\tvoid *va;\n+\tu32 size;\n+} __packed;\n+\n+struct irdma_sc_vsi;\n+struct irdma_sc_dev;\n+struct irdma_sc_qp;\n+struct irdma_puda_buf;\n+struct irdma_puda_cmpl_info;\n+struct irdma_update_sds_info;\n+struct irdma_hmc_fcn_info;\n+struct irdma_virtchnl_work_info;\n+struct irdma_manage_vf_pble_info;\n+struct irdma_hw;\n+struct irdma_pci_f;\n+\n+u8 __iomem *irdma_get_hw_addr(void *dev);\n+void irdma_ieq_mpa_crc_ae(struct irdma_sc_dev *dev, struct irdma_sc_qp *qp);\n+enum irdma_status_code irdma_vf_wait_vchnl_resp(struct irdma_sc_dev *dev);\n+bool irdma_vf_clear_to_send(struct irdma_sc_dev *dev);\n+void irdma_add_dev_ref(struct irdma_sc_dev *dev);\n+void irdma_put_dev_ref(struct irdma_sc_dev *dev);\n+enum irdma_status_code irdma_ieq_check_mpacrc(struct shash_desc *desc,\n+\t\t\t\t\t      void *addr, u32 len, u32 val);\n+struct irdma_sc_qp *irdma_ieq_get_qp(struct irdma_sc_dev *dev,\n+\t\t\t\t     struct irdma_puda_buf *buf);\n+void irdma_send_ieq_ack(struct irdma_sc_qp *qp);\n+void irdma_ieq_update_tcpip_info(struct irdma_puda_buf *buf, u16 len,\n+\t\t\t\t u32 seqnum);\n+void irdma_free_hash_desc(struct shash_desc *hash_desc);\n+enum irdma_status_code irdma_init_hash_desc(struct shash_desc **hash_desc);\n+enum irdma_status_code\n+irdma_puda_get_tcpip_info(struct irdma_puda_cmpl_info *info,\n+\t\t\t  struct irdma_puda_buf *buf);\n+enum irdma_status_code irdma_cqp_sds_cmd(struct irdma_sc_dev *dev,\n+\t\t\t\t\t struct irdma_update_sds_info *info);\n+enum irdma_status_code\n+irdma_cqp_manage_hmc_fcn_cmd(struct irdma_sc_dev *dev,\n+\t\t\t     struct irdma_hmc_fcn_info *hmcfcninfo);\n+enum irdma_status_code\n+irdma_cqp_query_fpm_val_cmd(struct irdma_sc_dev *dev,\n+\t\t\t    struct irdma_dma_mem *val_mem, u8 hmc_fn_id);\n+enum irdma_status_code\n+irdma_cqp_commit_fpm_val_cmd(struct irdma_sc_dev *dev,\n+\t\t\t     struct irdma_dma_mem *val_mem, u8 hmc_fn_id);\n+enum irdma_status_code irdma_alloc_query_fpm_buf(struct irdma_sc_dev *dev,\n+\t\t\t\t\t\t struct irdma_dma_mem *mem);\n+enum irdma_status_code\n+irdma_cqp_manage_vf_pble_bp(struct irdma_sc_dev *dev,\n+\t\t\t    struct irdma_manage_vf_pble_info *info);\n+void irdma_cqp_spawn_worker(struct irdma_sc_dev *dev,\n+\t\t\t    struct irdma_virtchnl_work_info *work_info,\n+\t\t\t    u32 iw_vf_idx);\n+void *irdma_remove_cqp_head(struct irdma_sc_dev *dev);\n+enum irdma_status_code irdma_qp_suspend_resume(struct irdma_sc_qp *qp,\n+\t\t\t\t\t       bool suspend);\n+void irdma_term_modify_qp(struct irdma_sc_qp *qp, u8 next_state, u8 term,\n+\t\t\t  u8 term_len);\n+void irdma_terminate_done(struct irdma_sc_qp *qp, int timeout_occurred);\n+void irdma_terminate_start_timer(struct irdma_sc_qp *qp);\n+void irdma_terminate_del_timer(struct irdma_sc_qp *qp);\n+enum irdma_status_code\n+irdma_hw_manage_vf_pble_bp(struct irdma_pci_f *rf,\n+\t\t\t   struct irdma_manage_vf_pble_info *info, bool wait);\n+void irdma_hw_stats_start_timer(struct irdma_sc_vsi *vsi);\n+void irdma_hw_stats_stop_timer(struct irdma_sc_vsi *vsi);\n+void wr32(struct irdma_hw *hw, u32 reg, u32 val);\n+u32 rd32(struct irdma_hw *hw, u32 reg);\n+u64 rd64(struct irdma_hw *hw, u32 reg);\n+#endif /* IRDMA_OSDEP_H */\ndiff --git a/drivers/infiniband/hw/irdma/protos.h b/drivers/infiniband/hw/irdma/protos.h\nnew file mode 100644\nindex 0000000..63d5b96\n--- /dev/null\n+++ b/drivers/infiniband/hw/irdma/protos.h\n@@ -0,0 +1,96 @@\n+/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */\n+/* Copyright (c) 2019, Intel Corporation. */\n+\n+#ifndef IRDMA_PROTOS_H\n+#define IRDMA_PROTOS_H\n+\n+#define PAUSE_TIMER_VAL\t\t0xffff\n+#define REFRESH_THRESHOLD\t0x7fff\n+#define HIGH_THRESHOLD\t\t0x800\n+#define LOW_THRESHOLD\t\t0x200\n+#define ALL_TC2PFC\t\t0xff\n+#define CQP_COMPL_WAIT_TIME_MS\t10\n+#define CQP_TIMEOUT_THRESHOLD\t500\n+\n+/* init operations */\n+enum irdma_status_code irdma_sc_ctrl_init(enum irdma_vers ver,\n+\t\t\t\t\t  struct irdma_sc_dev *dev,\n+\t\t\t\t\t  struct irdma_device_init_info *info);\n+void irdma_sc_rt_init(struct irdma_sc_dev *dev);\n+void irdma_sc_cqp_post_sq(struct irdma_sc_cqp *cqp);\n+__le64 *irdma_sc_cqp_get_next_send_wqe(struct irdma_sc_cqp *cqp, u64 scratch);\n+enum irdma_status_code\n+irdma_sc_mr_fast_register(struct irdma_sc_qp *qp,\n+\t\t\t  struct irdma_fast_reg_stag_info *info, bool post_sq);\n+/* HMC/FPM functions */\n+enum irdma_status_code irdma_sc_init_iw_hmc(struct irdma_sc_dev *dev,\n+\t\t\t\t\t    u8 hmc_fn_id);\n+/* stats misc */\n+enum irdma_status_code\n+irdma_cqp_gather_stats_cmd(struct irdma_sc_dev *dev,\n+\t\t\t   struct irdma_vsi_pestat *pestat, bool wait);\n+enum irdma_status_code\n+irdma_cqp_ws_node_cmd(struct irdma_sc_dev *dev, u8 cmd,\n+\t\t      struct irdma_ws_node_info *node_info);\n+enum irdma_status_code irdma_cqp_up_map_cmd(struct irdma_sc_dev *dev, u8 cmd,\n+\t\t\t\t\t    struct irdma_up_info *map_info);\n+enum irdma_status_code irdma_cqp_ceq_cmd(struct irdma_sc_dev *dev,\n+\t\t\t\t\t struct irdma_sc_ceq *sc_ceq, u8 op);\n+enum irdma_status_code\n+irdma_cqp_stats_inst_cmd(struct irdma_sc_vsi *vsi, u8 cmd,\n+\t\t\t struct irdma_stats_inst_info *stats_info);\n+u16 irdma_alloc_ws_node_id(struct irdma_sc_dev *dev);\n+void irdma_free_ws_node_id(struct irdma_sc_dev *dev, u16 node_id);\n+void irdma_update_stats(struct irdma_dev_hw_stats *hw_stats,\n+\t\t\tstruct irdma_gather_stats *gather_stats,\n+\t\t\tstruct irdma_gather_stats *last_gather_stats);\n+/* vsi functions */\n+enum irdma_status_code irdma_vsi_stats_init(struct irdma_sc_vsi *vsi,\n+\t\t\t\t\t    struct irdma_vsi_stats_info *info);\n+void irdma_vsi_stats_free(struct irdma_sc_vsi *vsi);\n+void irdma_sc_vsi_init(struct irdma_sc_vsi *vsi,\n+\t\t       struct irdma_vsi_init_info *info);\n+enum irdma_status_code irdma_sc_add_cq_ctx(struct irdma_sc_ceq *ceq,\n+\t\t\t\t\t   struct irdma_sc_cq *cq);\n+void irdma_sc_remove_cq_ctx(struct irdma_sc_ceq *ceq, struct irdma_sc_cq *cq);\n+/* misc L2 param change functions */\n+void irdma_change_l2params(struct irdma_sc_vsi *vsi,\n+\t\t\t   struct irdma_l2params *l2params);\n+void irdma_suspend_qps(struct irdma_sc_vsi *vsi);\n+void irdma_qp_add_qos(struct irdma_sc_qp *qp);\n+void irdma_qp_rem_qos(struct irdma_sc_qp *qp);\n+struct irdma_sc_qp *irdma_get_qp_from_list(struct list_head *head,\n+\t\t\t\t\t   struct irdma_sc_qp *qp);\n+void irdma_reinitialize_ieq(struct irdma_sc_vsi *vsi);\n+u16 irdma_alloc_ws_node_id(struct irdma_sc_dev *dev);\n+void irdma_free_ws_node_id(struct irdma_sc_dev *dev, u16 node_id);\n+enum irdma_status_code irdma_lan_register_qset(struct irdma_sc_vsi *vsi,\n+\t\t\t\t\t       struct irdma_ws_node *tc_node);\n+void irdma_lan_unregister_qset(struct irdma_sc_vsi *vsi,\n+\t\t\t       struct irdma_ws_node *tc_node);\n+/* terminate functions*/\n+void irdma_terminate_send_fin(struct irdma_sc_qp *qp);\n+\n+void irdma_terminate_connection(struct irdma_sc_qp *qp,\n+\t\t\t\tstruct irdma_aeqe_info *info);\n+\n+void irdma_terminate_received(struct irdma_sc_qp *qp,\n+\t\t\t      struct irdma_aeqe_info *info);\n+/* dynamic memory allocation */\n+/* misc */\n+u8 irdma_get_encoded_wqe_size(u32 wqsize, bool cqpsq);\n+void irdma_modify_qp_to_err(struct irdma_sc_qp *sc_qp);\n+enum irdma_status_code\n+irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp *cqp, u64 scratch,\n+\t\t\t\t    u8 hmc_fn_id, bool post_sq,\n+\t\t\t\t    bool poll_registers);\n+enum irdma_status_code irdma_cfg_fpm_val(struct irdma_sc_dev *dev,\n+\t\t\t\t\t u32 qp_count);\n+enum irdma_status_code irdma_get_rdma_features(struct irdma_sc_dev *dev);\n+void free_sd_mem(struct irdma_sc_dev *dev);\n+enum irdma_status_code irdma_process_cqp_cmd(struct irdma_sc_dev *dev,\n+\t\t\t\t\t     struct cqp_cmds_info *pcmdinfo);\n+enum irdma_status_code irdma_process_bh(struct irdma_sc_dev *dev);\n+enum irdma_status_code irdma_cqp_sds_cmd(struct irdma_sc_dev *dev,\n+\t\t\t\t\t struct irdma_update_sds_info *info);\n+#endif /* IRDMA_PROTOS_H */\ndiff --git a/drivers/infiniband/hw/irdma/status.h b/drivers/infiniband/hw/irdma/status.h\nnew file mode 100644\nindex 0000000..a23e42c\n--- /dev/null\n+++ b/drivers/infiniband/hw/irdma/status.h\n@@ -0,0 +1,70 @@\n+/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */\n+/* Copyright (c) 2019, Intel Corporation. */\n+\n+#ifndef IRDMA_STATUS_H\n+#define IRDMA_STATUS_H\n+\n+/* Error Codes */\n+enum irdma_status_code {\n+\tIRDMA_SUCCESS\t\t\t\t= 0,\n+\tIRDMA_ERR_NVM\t\t\t\t= -1,\n+\tIRDMA_ERR_NVM_CHECKSUM\t\t\t= -2,\n+\tIRDMA_ERR_CFG\t\t\t\t= -4,\n+\tIRDMA_ERR_PARAM\t\t\t\t= -5,\n+\tIRDMA_ERR_DEVICE_NOT_SUPPORTED\t\t= -6,\n+\tIRDMA_ERR_RESET_FAILED\t\t\t= -7,\n+\tIRDMA_ERR_SWFW_SYNC\t\t\t= -8,\n+\tIRDMA_ERR_NO_MEMORY\t\t\t= -9,\n+\tIRDMA_ERR_BAD_PTR\t\t\t= -10,\n+\tIRDMA_ERR_INVALID_PD_ID\t\t\t= -11,\n+\tIRDMA_ERR_INVALID_QP_ID\t\t\t= -12,\n+\tIRDMA_ERR_INVALID_CQ_ID\t\t\t= -13,\n+\tIRDMA_ERR_INVALID_CEQ_ID\t\t= -14,\n+\tIRDMA_ERR_INVALID_AEQ_ID\t\t= -15,\n+\tIRDMA_ERR_INVALID_SIZE\t\t\t= -16,\n+\tIRDMA_ERR_INVALID_ARP_INDEX\t\t= -17,\n+\tIRDMA_ERR_INVALID_FPM_FUNC_ID\t\t= -18,\n+\tIRDMA_ERR_QP_INVALID_MSG_SIZE\t\t= -19,\n+\tIRDMA_ERR_QP_TOOMANY_WRS_POSTED\t\t= -20,\n+\tIRDMA_ERR_INVALID_FRAG_COUNT\t\t= -21,\n+\tIRDMA_ERR_Q_EMPTY\t\t\t= -22,\n+\tIRDMA_ERR_INVALID_ALIGNMENT\t\t= -23,\n+\tIRDMA_ERR_FLUSHED_Q\t\t\t= -24,\n+\tIRDMA_ERR_INVALID_PUSH_PAGE_INDEX\t= -25,\n+\tIRDMA_ERR_INVALID_INLINE_DATA_SIZE\t= -26,\n+\tIRDMA_ERR_TIMEOUT\t\t\t= -27,\n+\tIRDMA_ERR_OPCODE_MISMATCH\t\t= -28,\n+\tIRDMA_ERR_CQP_COMPL_ERROR\t\t= -29,\n+\tIRDMA_ERR_INVALID_VF_ID\t\t\t= -30,\n+\tIRDMA_ERR_INVALID_HMCFN_ID\t\t= -31,\n+\tIRDMA_ERR_BACKING_PAGE_ERROR\t\t= -32,\n+\tIRDMA_ERR_NO_PBLCHUNKS_AVAILABLE\t= -33,\n+\tIRDMA_ERR_INVALID_PBLE_INDEX\t\t= -34,\n+\tIRDMA_ERR_INVALID_SD_INDEX\t\t= -35,\n+\tIRDMA_ERR_INVALID_PAGE_DESC_INDEX\t= -36,\n+\tIRDMA_ERR_INVALID_SD_TYPE\t\t= -37,\n+\tIRDMA_ERR_MEMCPY_FAILED\t\t\t= -38,\n+\tIRDMA_ERR_INVALID_HMC_OBJ_INDEX\t\t= -39,\n+\tIRDMA_ERR_INVALID_HMC_OBJ_COUNT\t\t= -40,\n+\tIRDMA_ERR_BUF_TOO_SHORT\t\t\t= -43,\n+\tIRDMA_ERR_BAD_IWARP_CQE\t\t\t= -44,\n+\tIRDMA_ERR_NVM_BLANK_MODE\t\t= -45,\n+\tIRDMA_ERR_NOT_IMPL\t\t\t= -46,\n+\tIRDMA_ERR_PE_DOORBELL_NOT_ENA\t\t= -47,\n+\tIRDMA_ERR_NOT_READY\t\t\t= -48,\n+\tIRDMA_NOT_SUPPORTED\t\t\t= -49,\n+\tIRDMA_ERR_FIRMWARE_API_VER\t\t= -50,\n+\tIRDMA_ERR_RING_FULL\t\t\t= -51,\n+\tIRDMA_ERR_MPA_CRC\t\t\t= -61,\n+\tIRDMA_ERR_NO_TXBUFS\t\t\t= -62,\n+\tIRDMA_ERR_SEQ_NUM\t\t\t= -63,\n+\tIRDMA_ERR_list_empty\t\t\t= -64,\n+\tIRDMA_ERR_INVALID_MAC_ADDR\t\t= -65,\n+\tIRDMA_ERR_BAD_STAG\t\t\t= -66,\n+\tIRDMA_ERR_CQ_COMPL_ERROR\t\t= -67,\n+\tIRDMA_ERR_Q_DESTROYED\t\t\t= -68,\n+\tIRDMA_ERR_INVALID_FEAT_CNT\t\t= -69,\n+\tIRDMA_ERR_REG_CQ_FULL\t\t\t= -70,\n+\tIRDMA_ERR_VF_MSG_ERROR\t\t\t= -71,\n+};\n+#endif /* IRDMA_STATUS_H */\ndiff --git a/drivers/infiniband/hw/irdma/utils.c b/drivers/infiniband/hw/irdma/utils.c\nnew file mode 100644\nindex 0000000..656fff6\n--- /dev/null\n+++ b/drivers/infiniband/hw/irdma/utils.c\n@@ -0,0 +1,2335 @@\n+// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB\n+/* Copyright (c) 2019, Intel Corporation. */\n+\n+#include <linux/mii.h>\n+#include <linux/in.h>\n+#include <linux/init.h>\n+#include <asm/irq.h>\n+#include <asm/byteorder.h>\n+#include <net/neighbour.h>\n+#include \"main.h\"\n+\n+/**\n+ * irdma_arp_table -manage arp table\n+ * @rf: RDMA PCI function\n+ * @ip_addr: ip address for device\n+ * @ipv4: IPv4 flag\n+ * @mac_addr: mac address ptr\n+ * @action: modify, delete or add\n+ */\n+int irdma_arp_table(struct irdma_pci_f *rf, u32 *ip_addr, bool ipv4,\n+\t\t    u8 *mac_addr, u32 action)\n+{\n+\tunsigned long flags;\n+\tint arp_index;\n+\tu32 ip[4] = {};\n+\n+\tif (ipv4)\n+\t\tip[0] = *ip_addr;\n+\telse\n+\t\tmemcpy(ip, ip_addr, sizeof(ip));\n+\n+\tspin_lock_irqsave(&rf->arp_lock, flags);\n+\tfor (arp_index = 0; (u32)arp_index < rf->arp_table_size; arp_index++) {\n+\t\tif (!memcmp(rf->arp_table[arp_index].ip_addr, ip, sizeof(ip)))\n+\t\t\tbreak;\n+\t}\n+\n+\tswitch (action) {\n+\tcase IRDMA_ARP_ADD:\n+\t\tif (arp_index != rf->arp_table_size) {\n+\t\t\tarp_index = -1;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tarp_index = 0;\n+\t\tif (irdma_alloc_rsrc(rf, rf->allocated_arps, rf->arp_table_size,\n+\t\t\t\t     (u32 *)&arp_index, &rf->next_arp_index)) {\n+\t\t\tarp_index = -1;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tmemcpy(rf->arp_table[arp_index].ip_addr, ip,\n+\t\t       sizeof(rf->arp_table[arp_index].ip_addr));\n+\t\tether_addr_copy(rf->arp_table[arp_index].mac_addr, mac_addr);\n+\t\tbreak;\n+\tcase IRDMA_ARP_RESOLVE:\n+\t\tif (arp_index == rf->arp_table_size)\n+\t\t\tarp_index = -1;\n+\t\tbreak;\n+\tcase IRDMA_ARP_DELETE:\n+\t\tif (arp_index == rf->arp_table_size) {\n+\t\t\tarp_index = -1;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tmemset(rf->arp_table[arp_index].ip_addr, 0,\n+\t\t       sizeof(rf->arp_table[arp_index].ip_addr));\n+\t\teth_zero_addr(rf->arp_table[arp_index].mac_addr);\n+\t\tirdma_free_rsrc(rf, rf->allocated_arps, arp_index);\n+\t\tbreak;\n+\tdefault:\n+\t\tarp_index = -1;\n+\t\tbreak;\n+\t}\n+\n+\tspin_unlock_irqrestore(&rf->arp_lock, flags);\n+\treturn arp_index;\n+}\n+\n+/**\n+ * irdma_add_arp - add a new arp entry if needed\n+ * @rf: RDMA function\n+ * @ip: IP address\n+ * @ipv4: IPv4 flag\n+ * @mac: MAC address\n+ */\n+int irdma_add_arp(struct irdma_pci_f *rf, u32 *ip, bool ipv4, u8 *mac)\n+{\n+\tint arpidx;\n+\n+\tarpidx = irdma_arp_table(rf, &ip[0], ipv4, NULL, IRDMA_ARP_RESOLVE);\n+\tif (arpidx >= 0) {\n+\t\tif (ether_addr_equal(rf->arp_table[arpidx].mac_addr, mac))\n+\t\t\treturn arpidx;\n+\n+\t\tirdma_manage_arp_cache(rf, rf->arp_table[arpidx].mac_addr, ip,\n+\t\t\t\t       ipv4, IRDMA_ARP_DELETE);\n+\t}\n+\n+\tirdma_manage_arp_cache(rf, mac, ip, ipv4, IRDMA_ARP_ADD);\n+\n+\treturn irdma_arp_table(rf, ip, ipv4, NULL, IRDMA_ARP_RESOLVE);\n+}\n+\n+/**\n+ * wr32 - write 32 bits to hw register\n+ * @hw: hardware information including registers\n+ * @reg: register offset\n+ * @val: value to write to register\n+ */\n+inline void wr32(struct irdma_hw *hw, u32 reg, u32 val)\n+{\n+\twritel(val, hw->hw_addr + reg);\n+}\n+\n+/**\n+ * rd32 - read a 32 bit hw register\n+ * @hw: hardware information including registers\n+ * @reg: register offset\n+ *\n+ * Return value of register content\n+ */\n+inline u32 rd32(struct irdma_hw *hw, u32 reg)\n+{\n+\treturn readl(hw->hw_addr + reg);\n+}\n+\n+/**\n+ * rd64 - read a 64 bit hw register\n+ * @hw: hardware information including registers\n+ * @reg: register offset\n+ *\n+ * Return value of register content\n+ */\n+inline u64 rd64(struct irdma_hw *hw, u32 reg)\n+{\n+\treturn readq(hw->hw_addr + reg);\n+}\n+\n+/**\n+ * irdma_inetaddr_event - system notifier for ipv4 addr events\n+ * @notifier: not used\n+ * @event: event for notifier\n+ * @ptr: if address\n+ */\n+int irdma_inetaddr_event(struct notifier_block *notifier, unsigned long event,\n+\t\t\t void *ptr)\n+{\n+\tstruct in_ifaddr *ifa = ptr;\n+\tstruct net_device *netdev = ifa->ifa_dev->dev;\n+\tstruct irdma_device *iwdev;\n+\tu32 local_ipaddr;\n+\n+\tiwdev = irdma_get_device(netdev);\n+\tif (!iwdev)\n+\t\treturn NOTIFY_DONE;\n+\n+\tlocal_ipaddr = ntohl(ifa->ifa_address);\n+\tswitch (event) {\n+\tcase NETDEV_DOWN:\n+\t\tirdma_manage_arp_cache(iwdev->rf, netdev->dev_addr,\n+\t\t\t\t       &local_ipaddr, true, IRDMA_ARP_DELETE);\n+\t\tirdma_if_notify(iwdev, netdev, &local_ipaddr, true, false);\n+\t\tbreak;\n+\tcase NETDEV_UP:\n+\t\t/* Fall through */\n+\tcase NETDEV_CHANGEADDR:\n+\t\tirdma_add_arp(iwdev->rf, &local_ipaddr, true, netdev->dev_addr);\n+\t\tirdma_if_notify(iwdev, netdev, &local_ipaddr, true, true);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tirdma_put_device(iwdev);\n+\n+\treturn NOTIFY_DONE;\n+}\n+\n+/**\n+ * irdma_inet6addr_event - system notifier for ipv6 addr events\n+ * @notifier: not used\n+ * @event: event for notifier\n+ * @ptr: if address\n+ */\n+int irdma_inet6addr_event(struct notifier_block *notifier, unsigned long event,\n+\t\t\t  void *ptr)\n+{\n+\tstruct inet6_ifaddr *ifa = ptr;\n+\tstruct net_device *netdev = ifa->idev->dev;\n+\tstruct irdma_device *iwdev;\n+\tu32 local_ipaddr6[4];\n+\n+\tiwdev = irdma_get_device(netdev);\n+\tif (!iwdev)\n+\t\treturn NOTIFY_DONE;\n+\n+\tirdma_copy_ip_ntohl(local_ipaddr6, ifa->addr.in6_u.u6_addr32);\n+\tswitch (event) {\n+\tcase NETDEV_DOWN:\n+\t\tirdma_manage_arp_cache(iwdev->rf, netdev->dev_addr,\n+\t\t\t\t       local_ipaddr6, false, IRDMA_ARP_DELETE);\n+\t\tirdma_if_notify(iwdev, netdev, local_ipaddr6, false, false);\n+\t\tbreak;\n+\tcase NETDEV_UP:\n+\t\t/* Fall through */\n+\tcase NETDEV_CHANGEADDR:\n+\t\tirdma_add_arp(iwdev->rf, local_ipaddr6, false,\n+\t\t\t      netdev->dev_addr);\n+\t\tirdma_if_notify(iwdev, netdev, local_ipaddr6, false, true);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tirdma_put_device(iwdev);\n+\n+\treturn NOTIFY_DONE;\n+}\n+\n+/**\n+ * irdma_net_event - system notifier for net events\n+ * @notifier: not used\n+ * @event: event for notifier\n+ * @ptr: neighbor\n+ */\n+int irdma_net_event(struct notifier_block *notifier, unsigned long event,\n+\t\t    void *ptr)\n+{\n+\tstruct neighbour *neigh = ptr;\n+\tstruct irdma_device *iwdev;\n+\t__be32 *p;\n+\tu32 local_ipaddr[4];\n+\n+\tiwdev = irdma_get_device((struct net_device *)neigh->dev);\n+\tif (!iwdev)\n+\t\treturn NOTIFY_DONE;\n+\n+\tswitch (event) {\n+\tcase NETEVENT_NEIGH_UPDATE:\n+\t\tp = (__be32 *)neigh->primary_key;\n+\t\tirdma_copy_ip_ntohl(local_ipaddr, p);\n+\t\tif (neigh->nud_state & NUD_VALID)\n+\t\t\tirdma_add_arp(iwdev->rf, local_ipaddr, false,\n+\t\t\t\t      neigh->ha);\n+\n+\t\telse\n+\t\t\tirdma_manage_arp_cache(iwdev->rf, neigh->ha,\n+\t\t\t\t\t       local_ipaddr, false,\n+\t\t\t\t\t       IRDMA_ARP_DELETE);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tirdma_put_device(iwdev);\n+\n+\treturn NOTIFY_DONE;\n+}\n+\n+/**\n+ * irdma_netdevice_event - system notifier for netdev events\n+ * @notifier: not used\n+ * @event: event for notifier\n+ * @ptr: netdev\n+ */\n+int irdma_netdevice_event(struct notifier_block *notifier, unsigned long event,\n+\t\t\t  void *ptr)\n+{\n+\tstruct irdma_device *iwdev;\n+\tstruct net_device *netdev = netdev_notifier_info_to_dev(ptr);\n+\n+\tiwdev = irdma_get_device(netdev);\n+\tif (!iwdev)\n+\t\treturn NOTIFY_DONE;\n+\n+\tiwdev->iw_status = 1;\n+\tswitch (event) {\n+\tcase NETDEV_DOWN:\n+\t\tiwdev->iw_status = 0;\n+\t\t/* Fall through */\n+\tcase NETDEV_UP:\n+\t\tirdma_port_ibevent(iwdev);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\tirdma_put_device(iwdev);\n+\n+\treturn NOTIFY_DONE;\n+}\n+\n+/**\n+ * irdma_get_cqp_request - get cqp struct\n+ * @cqp: device cqp ptr\n+ * @wait: cqp to be used in wait mode\n+ */\n+struct irdma_cqp_request *irdma_get_cqp_request(struct irdma_cqp *cqp,\n+\t\t\t\t\t\tbool wait)\n+{\n+\tstruct irdma_cqp_request *cqp_request = NULL;\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&cqp->req_lock, flags);\n+\tif (!list_empty(&cqp->cqp_avail_reqs)) {\n+\t\tcqp_request = list_entry(cqp->cqp_avail_reqs.next,\n+\t\t\t\t\t struct irdma_cqp_request, list);\n+\t\tlist_del_init(&cqp_request->list);\n+\t}\n+\tspin_unlock_irqrestore(&cqp->req_lock, flags);\n+\tif (!cqp_request) {\n+\t\tcqp_request = kzalloc(sizeof(*cqp_request), GFP_ATOMIC);\n+\t\tif (cqp_request) {\n+\t\t\tcqp_request->dynamic = true;\n+\t\t\tif (wait)\n+\t\t\t\tinit_waitqueue_head(&cqp_request->waitq);\n+\t\t}\n+\t}\n+\tif (!cqp_request) {\n+\t\tdev_dbg(rfdev_to_dev(cqp->sc_cqp.dev),\n+\t\t\t\"ERR: CQP Request Fail: No Memory\");\n+\t\treturn NULL;\n+\t}\n+\n+\tif (wait) {\n+\t\tatomic_set(&cqp_request->refcount, 2);\n+\t\tcqp_request->waiting = true;\n+\t} else {\n+\t\tatomic_set(&cqp_request->refcount, 1);\n+\t}\n+\tmemset(&cqp_request->compl_info, 0, sizeof(cqp_request->compl_info));\n+\n+\treturn cqp_request;\n+}\n+\n+/**\n+ * irdma_free_cqp_request - free cqp request\n+ * @cqp: cqp ptr\n+ * @cqp_request: to be put back in cqp list\n+ */\n+void irdma_free_cqp_request(struct irdma_cqp *cqp,\n+\t\t\t    struct irdma_cqp_request *cqp_request)\n+{\n+\tunsigned long flags;\n+\n+\tif (cqp_request->dynamic) {\n+\t\tkfree(cqp_request);\n+\t} else {\n+\t\tcqp_request->request_done = false;\n+\t\tcqp_request->callback_fcn = NULL;\n+\t\tcqp_request->waiting = false;\n+\n+\t\tspin_lock_irqsave(&cqp->req_lock, flags);\n+\t\tlist_add_tail(&cqp_request->list, &cqp->cqp_avail_reqs);\n+\t\tspin_unlock_irqrestore(&cqp->req_lock, flags);\n+\t}\n+\twake_up(&cqp->remove_wq);\n+}\n+\n+/**\n+ * irdma_put_cqp_request - dec ref count and free if 0\n+ * @cqp: cqp ptr\n+ * @cqp_request: to be put back in cqp list\n+ */\n+void irdma_put_cqp_request(struct irdma_cqp *cqp,\n+\t\t\t   struct irdma_cqp_request *cqp_request)\n+{\n+\tif (atomic_dec_and_test(&cqp_request->refcount))\n+\t\tirdma_free_cqp_request(cqp, cqp_request);\n+}\n+\n+/**\n+ * irdma_free_pending_cqp_request -free pending cqp request objs\n+ * @cqp: cqp ptr\n+ * @cqp_request: to be put back in cqp list\n+ */\n+static void\n+irdma_free_pending_cqp_request(struct irdma_cqp *cqp,\n+\t\t\t       struct irdma_cqp_request *cqp_request)\n+{\n+\tif (cqp_request->waiting) {\n+\t\tcqp_request->compl_info.error = true;\n+\t\tcqp_request->request_done = true;\n+\t\twake_up(&cqp_request->waitq);\n+\t}\n+\twait_event_timeout(cqp->remove_wq,\n+\t\t\t   atomic_read(&cqp_request->refcount) == 1, 1000);\n+\tirdma_put_cqp_request(cqp, cqp_request);\n+}\n+\n+/**\n+ * irdma_cleanup_pending_cqp_op - clean-up cqp with no\n+ * completions\n+ * @rf: RDMA PCI function\n+ */\n+void irdma_cleanup_pending_cqp_op(struct irdma_pci_f *rf)\n+{\n+\tstruct irdma_sc_dev *dev = &rf->sc_dev;\n+\tstruct irdma_cqp *cqp = &rf->cqp;\n+\tstruct irdma_cqp_request *cqp_request = NULL;\n+\tstruct cqp_cmds_info *pcmdinfo = NULL;\n+\tu32 i, pending_work, wqe_idx;\n+\n+\tpending_work = IRDMA_RING_USED_QUANTA(cqp->sc_cqp.sq_ring);\n+\twqe_idx = IRDMA_RING_CURRENT_TAIL(cqp->sc_cqp.sq_ring);\n+\tfor (i = 0; i < pending_work; i++) {\n+\t\tcqp_request = (struct irdma_cqp_request *)(unsigned long)\n+\t\t\t\t      cqp->scratch_array[wqe_idx];\n+\t\tif (cqp_request)\n+\t\t\tirdma_free_pending_cqp_request(cqp, cqp_request);\n+\t\twqe_idx = (wqe_idx + 1) % IRDMA_RING_SIZE(cqp->sc_cqp.sq_ring);\n+\t}\n+\n+\twhile (!list_empty(&dev->cqp_cmd_head)) {\n+\t\tpcmdinfo = (struct cqp_cmds_info *)\n+\t\t\t   irdma_remove_cqp_head(dev);\n+\t\tcqp_request =\n+\t\t\tcontainer_of(pcmdinfo, struct irdma_cqp_request, info);\n+\t\tif (cqp_request)\n+\t\t\tirdma_free_pending_cqp_request(cqp, cqp_request);\n+\t}\n+}\n+\n+/**\n+ * irdma_free_qp_worker - worker for freeing QP resources\n+ * @work: ptr to work struct\n+ */\n+static void irdma_free_qp_worker(struct work_struct *work)\n+{\n+\tstruct irdma_qp *iwqp = container_of(work, struct irdma_qp, work);\n+\n+\tirdma_free_qp_rsrc(iwqp->iwdev, iwqp, iwqp->ibqp.qp_num);\n+}\n+\n+/**\n+ * irdma_free_qp - callback after destroy cqp completes\n+ * @cqp_request: cqp request for destroy qp\n+ */\n+static void irdma_free_qp(struct irdma_cqp_request *cqp_request)\n+{\n+\tstruct irdma_sc_qp *qp = cqp_request->param;\n+\tstruct irdma_qp *iwqp = qp->qp_uk.back_qp;\n+\tstruct irdma_device *iwdev = iwqp->iwdev;\n+\n+\tINIT_WORK(&iwqp->work, irdma_free_qp_worker);\n+\tqueue_work(iwdev->rf->free_qp_wq, &iwqp->work);\n+}\n+\n+/**\n+ * irdma_wait_event - wait for completion\n+ * @rf: RDMA PCI function\n+ * @cqp_request: cqp request to wait\n+ */\n+static int irdma_wait_event(struct irdma_pci_f *rf,\n+\t\t\t    struct irdma_cqp_request *cqp_request)\n+{\n+\tstruct cqp_cmds_info *info = &cqp_request->info;\n+\tstruct irdma_cqp *iwcqp = &rf->cqp;\n+\tstruct irdma_cqp_timeout cqp_timeout = {};\n+\tbool cqp_error = false;\n+\tint err_code = 0;\n+\n+\tcqp_timeout.compl_cqp_cmds =\n+\t\trf->sc_dev.cqp_cmd_stats[IRDMA_OP_CMPL_CMDS];\n+\tdo {\n+\t\tup(&iwcqp->cqp_compl_sem);\n+\t\tif (wait_event_timeout(cqp_request->waitq,\n+\t\t\t\t       cqp_request->request_done,\n+\t\t\t\t       msecs_to_jiffies(CQP_COMPL_WAIT_TIME_MS)))\n+\t\t\tbreak;\n+\n+\t\trf->sc_dev.cqp_ops->check_cqp_progress(&cqp_timeout,\n+\t\t\t\t\t\t       &rf->sc_dev);\n+\n+\t\tif (cqp_timeout.count < CQP_TIMEOUT_THRESHOLD)\n+\t\t\tcontinue;\n+\n+\t\tdev_dbg(rfdev_to_dev(&rf->sc_dev),\n+\t\t\t\"ERR: error cqp command 0x%x timed out\",\n+\t\t\tinfo->cqp_cmd);\n+\t\terr_code = -ETIME;\n+\t\tif (!rf->reset) {\n+\t\t\trf->reset = true;\n+\t\t\tirdma_request_reset(rf);\n+\t\t}\n+\t\tgoto done;\n+\t} while (1);\n+\n+\tcqp_error = cqp_request->compl_info.error;\n+\tif (cqp_error) {\n+\t\tdev_dbg(rfdev_to_dev(&rf->sc_dev),\n+\t\t\t\"ERR: error cqp command 0x%x completion maj = 0x%x min=0x%x\\n\",\n+\t\t\tinfo->cqp_cmd, cqp_request->compl_info.maj_err_code,\n+\t\t\tcqp_request->compl_info.min_err_code);\n+\t\terr_code = -EPROTO;\n+\t\tgoto done;\n+\t}\n+\n+done:\n+\tirdma_put_cqp_request(iwcqp, cqp_request);\n+\n+\treturn err_code;\n+}\n+\n+/**\n+ * irdma_handle_cqp_op - process cqp command\n+ * @rf: RDMA PCI function\n+ * @cqp_request: cqp request to process\n+ */\n+enum irdma_status_code irdma_handle_cqp_op(struct irdma_pci_f *rf,\n+\t\t\t\t\t   struct irdma_cqp_request\n+\t\t\t\t\t   *cqp_request)\n+{\n+\tstruct irdma_sc_dev *dev = &rf->sc_dev;\n+\tenum irdma_status_code status;\n+\tstruct cqp_cmds_info *info = &cqp_request->info;\n+\tint err_code = 0;\n+\n+\tif (rf->reset) {\n+\t\tirdma_free_cqp_request(&rf->cqp, cqp_request);\n+\t\treturn IRDMA_ERR_CQP_COMPL_ERROR;\n+\t}\n+\n+\tstatus = irdma_process_cqp_cmd(dev, info);\n+\tif (status) {\n+\t\tdev_dbg(rfdev_to_dev(&rf->sc_dev),\n+\t\t\t\"ERR: error cqp command 0x%x failed\\n\", info->cqp_cmd);\n+\t\tirdma_free_cqp_request(&rf->cqp, cqp_request);\n+\t\treturn status;\n+\t}\n+\n+\tif (cqp_request->waiting)\n+\t\terr_code = irdma_wait_event(rf, cqp_request);\n+\tif (err_code)\n+\t\tstatus = IRDMA_ERR_CQP_COMPL_ERROR;\n+\n+\treturn status;\n+}\n+\n+/**\n+ * irdma_add_ref - add refcount for qp\n+ * @ibqp: iqarp qp\n+ */\n+void irdma_add_ref(struct ib_qp *ibqp)\n+{\n+\tstruct irdma_qp *iwqp = (struct irdma_qp *)ibqp;\n+\n+\tatomic_inc(&iwqp->refcount);\n+}\n+\n+/**\n+ * irdma_rem_ref - rem refcount for qp and free if 0\n+ * @ibqp: iqarp qp\n+ */\n+void irdma_rem_ref(struct ib_qp *ibqp)\n+{\n+\tstruct irdma_qp *iwqp;\n+\tenum irdma_status_code status;\n+\tstruct irdma_cqp_request *cqp_request;\n+\tstruct cqp_cmds_info *cqp_info;\n+\tstruct irdma_device *iwdev;\n+\tu32 qp_num;\n+\tunsigned long flags;\n+\n+\tiwqp = to_iwqp(ibqp);\n+\tiwdev = iwqp->iwdev;\n+\tspin_lock_irqsave(&iwdev->rf->qptable_lock, flags);\n+\tif (!atomic_dec_and_test(&iwqp->refcount)) {\n+\t\tspin_unlock_irqrestore(&iwdev->rf->qptable_lock, flags);\n+\t\treturn;\n+\t}\n+\n+\tqp_num = iwqp->ibqp.qp_num;\n+\tiwdev->rf->qp_table[qp_num] = NULL;\n+\tspin_unlock_irqrestore(&iwdev->rf->qptable_lock, flags);\n+\tcqp_request = irdma_get_cqp_request(&iwdev->rf->cqp, false);\n+\tif (!cqp_request)\n+\t\treturn;\n+\n+\tcqp_request->callback_fcn = irdma_free_qp;\n+\tcqp_request->param = (void *)&iwqp->sc_qp;\n+\tcqp_info = &cqp_request->info;\n+\tcqp_info->cqp_cmd = IRDMA_OP_QP_DESTROY;\n+\tcqp_info->post_sq = 1;\n+\tcqp_info->in.u.qp_destroy.qp = &iwqp->sc_qp;\n+\tcqp_info->in.u.qp_destroy.scratch = (uintptr_t)cqp_request;\n+\tcqp_info->in.u.qp_destroy.remove_hash_idx = true;\n+\tstatus = irdma_handle_cqp_op(iwdev->rf, cqp_request);\n+\tif (status) {\n+\t\tdev_dbg(rfdev_to_dev(&iwdev->rf->sc_dev),\n+\t\t\t\"ERR: CQP-OP Destroy QP fail\");\n+\t\tINIT_WORK(&iwqp->work, irdma_free_qp_worker);\n+\t\tqueue_work(iwdev->rf->free_qp_wq, &iwqp->work);\n+\t}\n+}\n+\n+/**\n+ * irdma_get_qp - get qp address\n+ * @device: iwarp device\n+ * @qpn: qp number\n+ */\n+struct ib_qp *irdma_get_qp(struct ib_device *device, int qpn)\n+{\n+\tstruct irdma_device *iwdev = to_iwdev(device);\n+\n+\tif (qpn < IW_FIRST_QPN || qpn >= iwdev->rf->max_qp)\n+\t\treturn NULL;\n+\n+\treturn &iwdev->rf->qp_table[qpn]->ibqp;\n+}\n+\n+/**\n+ * irdma_get_hw_addr - return hw addr\n+ * @par: points to shared dev\n+ */\n+u8 __iomem *irdma_get_hw_addr(void *par)\n+{\n+\tstruct irdma_sc_dev *dev = par;\n+\n+\treturn dev->hw->hw_addr;\n+}\n+\n+/**\n+ * irdma_remove_cqp_head - return head entry and remove\n+ * @dev: device\n+ */\n+void *irdma_remove_cqp_head(struct irdma_sc_dev *dev)\n+{\n+\tstruct list_head *entry;\n+\tstruct list_head *list = &dev->cqp_cmd_head;\n+\n+\tif (list_empty(list))\n+\t\treturn NULL;\n+\n+\tentry = (void *)list->next;\n+\tlist_del(entry);\n+\n+\treturn (void *)entry;\n+}\n+\n+/**\n+ * irdma_cqp_sds_cmd - create cqp command for sd\n+ * @dev: hardware control device structure\n+ * @sdinfo: information for sd cqp\n+ *\n+ */\n+enum irdma_status_code irdma_cqp_sds_cmd(struct irdma_sc_dev *dev,\n+\t\t\t\t\t struct irdma_update_sds_info *sdinfo)\n+{\n+\tenum irdma_status_code status;\n+\tstruct irdma_cqp_request *cqp_request;\n+\tstruct cqp_cmds_info *cqp_info;\n+\tstruct irdma_pci_f *rf = dev->back_dev;\n+\n+\tcqp_request = irdma_get_cqp_request(&rf->cqp, false);\n+\tif (!cqp_request)\n+\t\treturn IRDMA_ERR_NO_MEMORY;\n+\n+\tcqp_info = &cqp_request->info;\n+\tmemcpy(&cqp_info->in.u.update_pe_sds.info, sdinfo,\n+\t       sizeof(cqp_info->in.u.update_pe_sds.info));\n+\tcqp_info->cqp_cmd = IRDMA_OP_UPDATE_PE_SDS;\n+\tcqp_info->post_sq = 1;\n+\tcqp_info->in.u.update_pe_sds.dev = dev;\n+\tcqp_info->in.u.update_pe_sds.scratch = (uintptr_t)cqp_request;\n+\tstatus = irdma_handle_cqp_op(rf, cqp_request);\n+\tif (status)\n+\t\tdev_dbg(rfdev_to_dev(dev), \"ERR: CQP-OP Update SD's fail\");\n+\n+\treturn status;\n+}\n+\n+/**\n+ * irdma_qp_suspend_resume - cqp command for suspend/resume\n+ * @qp: hardware control qp\n+ * @suspend: flag if suspend or resume\n+ */\n+enum irdma_status_code irdma_qp_suspend_resume(struct irdma_sc_qp *qp,\n+\t\t\t\t\t       bool suspend)\n+{\n+\tstruct irdma_sc_dev *dev = qp->dev;\n+\tenum irdma_status_code status;\n+\tstruct irdma_cqp_request *cqp_request;\n+\tstruct irdma_sc_cqp *cqp = dev->cqp;\n+\tstruct cqp_cmds_info *cqp_info;\n+\tstruct irdma_pci_f *rf = dev->back_dev;\n+\n+\tcqp_request = irdma_get_cqp_request(&rf->cqp, false);\n+\tif (!cqp_request)\n+\t\treturn IRDMA_ERR_NO_MEMORY;\n+\n+\tcqp_info = &cqp_request->info;\n+\tcqp_info->cqp_cmd = (suspend) ? IRDMA_OP_SUSPEND : IRDMA_OP_RESUME;\n+\tcqp_info->in.u.suspend_resume.cqp = cqp;\n+\tcqp_info->in.u.suspend_resume.qp = qp;\n+\tcqp_info->in.u.suspend_resume.scratch = (uintptr_t)cqp_request;\n+\tstatus = irdma_handle_cqp_op(rf, cqp_request);\n+\tif (status)\n+\t\tdev_dbg(rfdev_to_dev(dev),\n+\t\t\t\"ERR: CQP-OP QP Suspend/Resume fail\");\n+\n+\treturn status;\n+}\n+\n+/**\n+ * irdma_term_modify_qp - modify qp for term message\n+ * @qp: hardware control qp\n+ * @next_state: qp's next state\n+ * @term: terminate code\n+ * @term_len: length\n+ */\n+void irdma_term_modify_qp(struct irdma_sc_qp *qp, u8 next_state, u8 term,\n+\t\t\t  u8 term_len)\n+{\n+\tstruct irdma_qp *iwqp;\n+\n+\tiwqp = qp->qp_uk.back_qp;\n+\tirdma_next_iw_state(iwqp, next_state, 0, term, term_len);\n+};\n+\n+/**\n+ * irdma_terminate_done - after terminate is completed\n+ * @qp: hardware control qp\n+ * @timeout_occurred: indicates if terminate timer expired\n+ */\n+void irdma_terminate_done(struct irdma_sc_qp *qp, int timeout_occurred)\n+{\n+\tstruct irdma_qp *iwqp;\n+\tu8 hte = 0;\n+\tbool first_time;\n+\tunsigned long flags;\n+\n+\tiwqp = qp->qp_uk.back_qp;\n+\tspin_lock_irqsave(&iwqp->lock, flags);\n+\tif (iwqp->hte_added) {\n+\t\tiwqp->hte_added = 0;\n+\t\thte = 1;\n+\t}\n+\tfirst_time = !(qp->term_flags & IRDMA_TERM_DONE);\n+\tqp->term_flags |= IRDMA_TERM_DONE;\n+\tspin_unlock_irqrestore(&iwqp->lock, flags);\n+\tif (first_time) {\n+\t\tif (!timeout_occurred)\n+\t\t\tirdma_terminate_del_timer(qp);\n+\n+\t\tirdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, hte, 0, 0);\n+\t\tirdma_cm_disconn(iwqp);\n+\t}\n+}\n+\n+static void irdma_terminate_timeout(struct timer_list *t)\n+{\n+\tstruct irdma_qp *iwqp = from_timer(iwqp, t, terminate_timer);\n+\tstruct irdma_sc_qp *qp = &iwqp->sc_qp;\n+\n+\tirdma_terminate_done(qp, 1);\n+\tirdma_rem_ref(&iwqp->ibqp);\n+}\n+\n+/**\n+ * irdma_terminate_start_timer - start terminate timeout\n+ * @qp: hardware control qp\n+ */\n+void irdma_terminate_start_timer(struct irdma_sc_qp *qp)\n+{\n+\tstruct irdma_qp *iwqp;\n+\n+\tiwqp = qp->qp_uk.back_qp;\n+\tirdma_add_ref(&iwqp->ibqp);\n+\ttimer_setup(&iwqp->terminate_timer, irdma_terminate_timeout, 0);\n+\tiwqp->terminate_timer.expires = jiffies + HZ;\n+\n+\tadd_timer(&iwqp->terminate_timer);\n+}\n+\n+/**\n+ * irdma_terminate_del_timer - delete terminate timeout\n+ * @qp: hardware control qp\n+ */\n+void irdma_terminate_del_timer(struct irdma_sc_qp *qp)\n+{\n+\tstruct irdma_qp *iwqp;\n+\tint ret;\n+\n+\tiwqp = qp->qp_uk.back_qp;\n+\tret = del_timer(&iwqp->terminate_timer);\n+\tif (ret)\n+\t\tirdma_rem_ref(&iwqp->ibqp);\n+}\n+\n+/**\n+ * irdma_cqp_query_fpm_values_cmd - send cqp command for fpm\n+ * @dev: function device struct\n+ * @val_mem: buffer for fpm\n+ * @hmc_fn_id: function id for fpm\n+ */\n+enum irdma_status_code\n+irdma_cqp_query_fpm_val_cmd(struct irdma_sc_dev *dev,\n+\t\t\t    struct irdma_dma_mem *val_mem, u8 hmc_fn_id)\n+{\n+\tenum irdma_status_code status;\n+\tstruct irdma_cqp_request *cqp_request;\n+\tstruct cqp_cmds_info *cqp_info;\n+\tstruct irdma_pci_f *rf = dev->back_dev;\n+\n+\tcqp_request = irdma_get_cqp_request(&rf->cqp, true);\n+\tif (!cqp_request)\n+\t\treturn IRDMA_ERR_NO_MEMORY;\n+\n+\tcqp_info = &cqp_request->info;\n+\tcqp_request->param = NULL;\n+\tcqp_info->in.u.query_fpm_val.cqp = dev->cqp;\n+\tcqp_info->in.u.query_fpm_val.fpm_val_pa = val_mem->pa;\n+\tcqp_info->in.u.query_fpm_val.fpm_val_va = val_mem->va;\n+\tcqp_info->in.u.query_fpm_val.hmc_fn_id = hmc_fn_id;\n+\tcqp_info->cqp_cmd = IRDMA_OP_QUERY_FPM_VAL;\n+\tcqp_info->post_sq = 1;\n+\tcqp_info->in.u.query_fpm_val.scratch = (uintptr_t)cqp_request;\n+\tstatus = irdma_handle_cqp_op(rf, cqp_request);\n+\tif (status)\n+\t\tdev_dbg(rfdev_to_dev(dev), \"ERR: CQP-OP Query FPM fail\");\n+\n+\treturn status;\n+}\n+\n+/**\n+ * irdma_cqp_commit_fpm_values_cmd - commit fpm values in hw\n+ * @dev: hardware control device structure\n+ * @val_mem: buffer with fpm values\n+ * @hmc_fn_id: function id for fpm\n+ */\n+enum irdma_status_code\n+irdma_cqp_commit_fpm_val_cmd(struct irdma_sc_dev *dev,\n+\t\t\t     struct irdma_dma_mem *val_mem, u8 hmc_fn_id)\n+{\n+\tenum irdma_status_code status;\n+\tstruct irdma_cqp_request *cqp_request;\n+\tstruct cqp_cmds_info *cqp_info;\n+\tstruct irdma_pci_f *rf = dev->back_dev;\n+\n+\tcqp_request = irdma_get_cqp_request(&rf->cqp, true);\n+\tif (!cqp_request)\n+\t\treturn IRDMA_ERR_NO_MEMORY;\n+\n+\tcqp_info = &cqp_request->info;\n+\tcqp_request->param = NULL;\n+\tcqp_info->in.u.commit_fpm_val.cqp = dev->cqp;\n+\tcqp_info->in.u.commit_fpm_val.fpm_val_pa = val_mem->pa;\n+\tcqp_info->in.u.commit_fpm_val.fpm_val_va = val_mem->va;\n+\tcqp_info->in.u.commit_fpm_val.hmc_fn_id = hmc_fn_id;\n+\tcqp_info->cqp_cmd = IRDMA_OP_COMMIT_FPM_VAL;\n+\tcqp_info->post_sq = 1;\n+\tcqp_info->in.u.commit_fpm_val.scratch = (uintptr_t)cqp_request;\n+\tstatus = irdma_handle_cqp_op(rf, cqp_request);\n+\tif (status)\n+\t\tdev_dbg(rfdev_to_dev(dev), \"ERR: CQP-OP Commit FPM fail\");\n+\n+\treturn status;\n+}\n+\n+/**\n+ * irdma_cqp_cq_create_cmd - create a cq for the cqp\n+ * @dev: device pointer\n+ * @cq: pointer to created cq\n+ */\n+enum irdma_status_code irdma_cqp_cq_create_cmd(struct irdma_sc_dev *dev,\n+\t\t\t\t\t       struct irdma_sc_cq *cq)\n+{\n+\tstruct irdma_pci_f *rf = dev->back_dev;\n+\tstruct irdma_cqp *iwcqp = &rf->cqp;\n+\tstruct irdma_cqp_request *cqp_request;\n+\tstruct cqp_cmds_info *cqp_info;\n+\tenum irdma_status_code status;\n+\n+\tcqp_request = irdma_get_cqp_request(iwcqp, true);\n+\tif (!cqp_request)\n+\t\treturn IRDMA_ERR_NO_MEMORY;\n+\n+\tcqp_info = &cqp_request->info;\n+\tcqp_info->cqp_cmd = IRDMA_OP_CQ_CREATE;\n+\tcqp_info->post_sq = 1;\n+\tcqp_info->in.u.cq_create.cq = cq;\n+\tcqp_info->in.u.cq_create.scratch = (uintptr_t)cqp_request;\n+\tstatus = irdma_handle_cqp_op(rf, cqp_request);\n+\tif (status)\n+\t\tdev_dbg(rfdev_to_dev(dev), \"ERR: CQP-OP Create CQ fail\");\n+\n+\treturn status;\n+}\n+\n+/**\n+ * irdma_cqp_qp_create_cmd - create a qp for the cqp\n+ * @dev: device pointer\n+ * @qp: pointer to created qp\n+ */\n+enum irdma_status_code irdma_cqp_qp_create_cmd(struct irdma_sc_dev *dev,\n+\t\t\t\t\t       struct irdma_sc_qp *qp)\n+{\n+\tstruct irdma_pci_f *rf = dev->back_dev;\n+\tstruct irdma_cqp *iwcqp = &rf->cqp;\n+\tstruct irdma_cqp_request *cqp_request;\n+\tstruct cqp_cmds_info *cqp_info;\n+\tstruct irdma_create_qp_info *qp_info;\n+\tenum irdma_status_code status;\n+\n+\tcqp_request = irdma_get_cqp_request(iwcqp, true);\n+\tif (!cqp_request)\n+\t\treturn IRDMA_ERR_NO_MEMORY;\n+\n+\tcqp_info = &cqp_request->info;\n+\tqp_info = &cqp_request->info.in.u.qp_create.info;\n+\tmemset(qp_info, 0, sizeof(*qp_info));\n+\tqp_info->cq_num_valid = true;\n+\tqp_info->next_iwarp_state = IRDMA_QP_STATE_RTS;\n+\tcqp_info->cqp_cmd = IRDMA_OP_QP_CREATE;\n+\tcqp_info->post_sq = 1;\n+\tcqp_info->in.u.qp_create.qp = qp;\n+\tcqp_info->in.u.qp_create.scratch = (uintptr_t)cqp_request;\n+\tstatus = irdma_handle_cqp_op(rf, cqp_request);\n+\tif (status)\n+\t\tdev_dbg(rfdev_to_dev(dev), \"ERR: CQP-OP QP create fail\");\n+\n+\treturn status;\n+}\n+\n+/**\n+ * irdma_dealloc_push_page - free a push page for qp\n+ * @rf: RDMA PCI function\n+ * @qp: hardware control qp\n+ */\n+static void irdma_dealloc_push_page(struct irdma_pci_f *rf,\n+\t\t\t\t    struct irdma_sc_qp *qp)\n+{\n+\tstruct irdma_cqp_request *cqp_request;\n+\tstruct cqp_cmds_info *cqp_info;\n+\tenum irdma_status_code status;\n+\n+\tif (qp->push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX)\n+\t\treturn;\n+\n+\tcqp_request = irdma_get_cqp_request(&rf->cqp, false);\n+\tif (!cqp_request)\n+\t\treturn;\n+\n+\tcqp_info = &cqp_request->info;\n+\tcqp_info->cqp_cmd = IRDMA_OP_MANAGE_PUSH_PAGE;\n+\tcqp_info->post_sq = 1;\n+\tcqp_info->in.u.manage_push_page.info.push_idx = qp->push_idx;\n+\tcqp_info->in.u.manage_push_page.info.qs_handle = qp->qs_handle;\n+\tcqp_info->in.u.manage_push_page.info.free_page = 1;\n+\tcqp_info->in.u.manage_push_page.info.push_page_type = 0;\n+\tcqp_info->in.u.manage_push_page.cqp = &rf->cqp.sc_cqp;\n+\tcqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request;\n+\tstatus = irdma_handle_cqp_op(rf, cqp_request);\n+\tif (!status)\n+\t\tqp->push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX;\n+\telse\n+\t\tdev_dbg(rfdev_to_dev(&rf->sc_dev),\n+\t\t\t\"ERR: CQP-OP dealloc Push page fail\");\n+}\n+\n+/**\n+ * irdma_free_qp_rsrc - free up memory resources for qp\n+ * @iwdev: iwarp device\n+ * @iwqp: qp ptr (user or kernel)\n+ * @qp_num: qp number assigned\n+ */\n+void irdma_free_qp_rsrc(struct irdma_device *iwdev, struct irdma_qp *iwqp,\n+\t\t\tu32 qp_num)\n+{\n+\tstruct irdma_pci_f *rf = iwdev->rf;\n+\n+\tirdma_ieq_cleanup_qp(iwdev->vsi.ieq, &iwqp->sc_qp);\n+\tirdma_dealloc_push_page(rf, &iwqp->sc_qp);\n+\tif (iwqp->sc_qp.vsi) {\n+\t\tirdma_qp_rem_qos(&iwqp->sc_qp);\n+\t\tiwqp->sc_qp.dev->ws_remove(iwqp->sc_qp.vsi,\n+\t\t\t\t\t   iwqp->sc_qp.user_pri);\n+\t}\n+\n+\tif (qp_num > 2)\n+\t\tirdma_free_rsrc(rf, rf->allocated_qps, qp_num);\n+\tdma_free_coherent(hw_to_dev(rf->sc_dev.hw), iwqp->q2_ctx_mem.size,\n+\t\t\t  iwqp->q2_ctx_mem.va, iwqp->q2_ctx_mem.pa);\n+\tiwqp->q2_ctx_mem.va = NULL;\n+\tdma_free_coherent(hw_to_dev(rf->sc_dev.hw), iwqp->kqp.dma_mem.size,\n+\t\t\t  iwqp->kqp.dma_mem.va, iwqp->kqp.dma_mem.pa);\n+\tiwqp->kqp.dma_mem.va = NULL;\n+\tkfree(iwqp->kqp.sq_wrid_mem);\n+\tiwqp->kqp.sq_wrid_mem = NULL;\n+\tkfree(iwqp->kqp.rq_wrid_mem);\n+\tiwqp->kqp.rq_wrid_mem = NULL;\n+\tkfree(iwqp);\n+}\n+\n+/**\n+ * irdma_cq_wq_destroy - send cq destroy cqp\n+ * @rf: RDMA PCI function\n+ * @cq: hardware control cq\n+ */\n+void irdma_cq_wq_destroy(struct irdma_pci_f *rf, struct irdma_sc_cq *cq)\n+{\n+\tenum irdma_status_code status;\n+\tstruct irdma_cqp_request *cqp_request;\n+\tstruct cqp_cmds_info *cqp_info;\n+\n+\tcqp_request = irdma_get_cqp_request(&rf->cqp, true);\n+\tif (!cqp_request)\n+\t\treturn;\n+\n+\tcqp_info = &cqp_request->info;\n+\tcqp_info->cqp_cmd = IRDMA_OP_CQ_DESTROY;\n+\tcqp_info->post_sq = 1;\n+\tcqp_info->in.u.cq_destroy.cq = cq;\n+\tcqp_info->in.u.cq_destroy.scratch = (uintptr_t)cqp_request;\n+\tstatus = irdma_handle_cqp_op(rf, cqp_request);\n+\tif (status)\n+\t\tdev_dbg(rfdev_to_dev(&rf->sc_dev),\n+\t\t\t\"ERR: CQP-OP Destroy CQ fail\");\n+}\n+\n+/**\n+ * irdma_hw_modify_qp_callback - handle state for modifyQPs that don't wait\n+ * @cqp_request: modify QP completion\n+ */\n+static void irdma_hw_modify_qp_callback(struct irdma_cqp_request *cqp_request)\n+{\n+\tstruct cqp_cmds_info *cqp_info;\n+\tstruct irdma_qp *iwqp;\n+\n+\tcqp_info = &cqp_request->info;\n+\tiwqp = cqp_info->in.u.qp_modify.qp->qp_uk.back_qp;\n+\tatomic_dec(&iwqp->hw_mod_qp_pend);\n+\twake_up(&iwqp->mod_qp_waitq);\n+}\n+\n+/**\n+ * irdma_hw_modify_qp - setup cqp for modify qp\n+ * @iwdev: RDMA device\n+ * @iwqp: qp ptr (user or kernel)\n+ * @info: info for modify qp\n+ * @wait: flag to wait or not for modify qp completion\n+ */\n+enum irdma_status_code irdma_hw_modify_qp(struct irdma_device *iwdev,\n+\t\t\t\t\t  struct irdma_qp *iwqp,\n+\t\t\t\t\t  struct irdma_modify_qp_info *info,\n+\t\t\t\t\t  bool wait)\n+{\n+\tenum irdma_status_code status;\n+\tstruct irdma_pci_f *rf = iwdev->rf;\n+\tstruct irdma_cqp_request *cqp_request;\n+\tstruct cqp_cmds_info *cqp_info;\n+\tstruct irdma_modify_qp_info *m_info;\n+\n+\tcqp_request = irdma_get_cqp_request(&rf->cqp, wait);\n+\tif (!cqp_request)\n+\t\treturn IRDMA_ERR_NO_MEMORY;\n+\n+\tif (!wait) {\n+\t\tcqp_request->callback_fcn = irdma_hw_modify_qp_callback;\n+\t\tatomic_inc(&iwqp->hw_mod_qp_pend);\n+\t}\n+\tcqp_info = &cqp_request->info;\n+\tm_info = &cqp_info->in.u.qp_modify.info;\n+\tmemcpy(m_info, info, sizeof(*m_info));\n+\tcqp_info->cqp_cmd = IRDMA_OP_QP_MODIFY;\n+\tcqp_info->post_sq = 1;\n+\tcqp_info->in.u.qp_modify.qp = &iwqp->sc_qp;\n+\tcqp_info->in.u.qp_modify.scratch = (uintptr_t)cqp_request;\n+\tstatus = irdma_handle_cqp_op(rf, cqp_request);\n+\tif (status) {\n+\t\tif (rdma_protocol_roce(&iwdev->iwibdev->ibdev, 1))\n+\t\t\treturn status;\n+\t\tswitch (m_info->next_iwarp_state) {\n+\t\t\tstruct irdma_gen_ae_info ae_info;\n+\n+\t\tcase IRDMA_QP_STATE_RTS:\n+\t\tcase IRDMA_QP_STATE_IDLE:\n+\t\tcase IRDMA_QP_STATE_TERMINATE:\n+\t\tcase IRDMA_QP_STATE_CLOSING:\n+\t\t\tif (info->curr_iwarp_state == IRDMA_QP_STATE_IDLE)\n+\t\t\t\tirdma_send_reset(iwqp->cm_node);\n+\t\t\telse\n+\t\t\t\tiwqp->sc_qp.term_flags = IRDMA_TERM_DONE;\n+\t\t\tif (!wait) {\n+\t\t\t\tae_info.ae_code = IRDMA_AE_BAD_CLOSE;\n+\t\t\t\tae_info.ae_src = 0;\n+\t\t\t\tirdma_gen_ae(rf, &iwqp->sc_qp, &ae_info, false);\n+\t\t\t} else {\n+\t\t\t\tcqp_request = irdma_get_cqp_request(&rf->cqp,\n+\t\t\t\t\t\t\t\t    wait);\n+\t\t\t\tif (!cqp_request)\n+\t\t\t\t\treturn IRDMA_ERR_NO_MEMORY;\n+\n+\t\t\t\tcqp_info = &cqp_request->info;\n+\t\t\t\tm_info = &cqp_info->in.u.qp_modify.info;\n+\t\t\t\tmemcpy(m_info, info, sizeof(*m_info));\n+\t\t\t\tcqp_info->cqp_cmd = IRDMA_OP_QP_MODIFY;\n+\t\t\t\tcqp_info->post_sq = 1;\n+\t\t\t\tcqp_info->in.u.qp_modify.qp = &iwqp->sc_qp;\n+\t\t\t\tcqp_info->in.u.qp_modify.scratch = (uintptr_t)cqp_request;\n+\t\t\t\tm_info->next_iwarp_state = IRDMA_QP_STATE_ERROR;\n+\t\t\t\tm_info->reset_tcp_conn = true;\n+\t\t\t\tirdma_handle_cqp_op(rf, cqp_request);\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase IRDMA_QP_STATE_ERROR:\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * irdma_cqp_cq_destroy_cmd - destroy the cqp cq\n+ * @dev: device pointer\n+ * @cq: pointer to cq\n+ */\n+void irdma_cqp_cq_destroy_cmd(struct irdma_sc_dev *dev, struct irdma_sc_cq *cq)\n+{\n+\tstruct irdma_pci_f *rf = dev->back_dev;\n+\n+\tirdma_cq_wq_destroy(rf, cq);\n+}\n+\n+/**\n+ * irdma_cqp_qp_destroy_cmd - destroy the cqp\n+ * @dev: device pointer\n+ * @qp: pointer to qp\n+ */\n+void irdma_cqp_qp_destroy_cmd(struct irdma_sc_dev *dev, struct irdma_sc_qp *qp)\n+{\n+\tstruct irdma_pci_f *rf = dev->back_dev;\n+\tstruct irdma_cqp *iwcqp = &rf->cqp;\n+\tstruct irdma_cqp_request *cqp_request;\n+\tstruct cqp_cmds_info *cqp_info;\n+\tenum irdma_status_code status;\n+\n+\tcqp_request = irdma_get_cqp_request(iwcqp, true);\n+\tif (!cqp_request)\n+\t\treturn;\n+\n+\tcqp_info = &cqp_request->info;\n+\tmemset(cqp_info, 0, sizeof(*cqp_info));\n+\tcqp_info->cqp_cmd = IRDMA_OP_QP_DESTROY;\n+\tcqp_info->post_sq = 1;\n+\tcqp_info->in.u.qp_destroy.qp = qp;\n+\tcqp_info->in.u.qp_destroy.scratch = (uintptr_t)cqp_request;\n+\tcqp_info->in.u.qp_destroy.remove_hash_idx = true;\n+\tstatus = irdma_handle_cqp_op(rf, cqp_request);\n+\tif (status)\n+\t\tdev_dbg(rfdev_to_dev(dev), \"ERR: CQP QP_DESTROY fail\");\n+}\n+\n+/**\n+ * irdma_ieq_mpa_crc_ae - generate AE for crc error\n+ * @dev: hardware control device structure\n+ * @qp: hardware control qp\n+ */\n+void irdma_ieq_mpa_crc_ae(struct irdma_sc_dev *dev, struct irdma_sc_qp *qp)\n+{\n+\tstruct irdma_gen_ae_info info = {};\n+\tstruct irdma_pci_f *rf = dev->back_dev;\n+\n+\tdev_dbg(rfdev_to_dev(dev), \"AEQ: Generate MPA CRC AE\\n\");\n+\tinfo.ae_code = IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR;\n+\tinfo.ae_src = IRDMA_AE_SOURCE_RQ;\n+\tirdma_gen_ae(rf, qp, &info, false);\n+}\n+\n+/**\n+ * irdma_init_hash_desc - initialize hash for crc calculation\n+ * @desc: cryption type\n+ */\n+enum irdma_status_code irdma_init_hash_desc(struct shash_desc **desc)\n+{\n+\tstruct crypto_shash *tfm;\n+\tstruct shash_desc *tdesc;\n+\n+\ttfm = crypto_alloc_shash(\"crc32c\", 0, 0);\n+\tif (IS_ERR(tfm))\n+\t\treturn IRDMA_ERR_MPA_CRC;\n+\n+\ttdesc = kzalloc(sizeof(*tdesc) + crypto_shash_descsize(tfm),\n+\t\t\tGFP_KERNEL);\n+\tif (!tdesc) {\n+\t\tcrypto_free_shash(tfm);\n+\t\treturn IRDMA_ERR_MPA_CRC;\n+\t}\n+\n+\ttdesc->tfm = tfm;\n+\t*desc = tdesc;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * irdma_free_hash_desc - free hash desc\n+ * @desc: to be freed\n+ */\n+void irdma_free_hash_desc(struct shash_desc *desc)\n+{\n+\tif (desc) {\n+\t\tcrypto_free_shash(desc->tfm);\n+\t\tkfree(desc);\n+\t}\n+}\n+\n+/**\n+ * irdma_ieq_check_mpacrc - check if mpa crc is OK\n+ * @desc: desc for hash\n+ * @addr: address of buffer for crc\n+ * @len: length of buffer\n+ * @val: value to be compared\n+ */\n+enum irdma_status_code irdma_ieq_check_mpacrc(struct shash_desc *desc,\n+\t\t\t\t\t      void *addr, u32 len, u32 val)\n+{\n+\tu32 crc = 0;\n+\tint ret;\n+\tenum irdma_status_code ret_code = 0;\n+\n+\tcrypto_shash_init(desc);\n+\tret = crypto_shash_update(desc, addr, len);\n+\tif (!ret)\n+\t\tcrypto_shash_final(desc, (u8 *)&crc);\n+\tif (crc != val) {\n+\t\tpr_err(\"mpa crc check fail\");\n+\t\tret_code = IRDMA_ERR_MPA_CRC;\n+\t}\n+\n+\treturn ret_code;\n+}\n+\n+/**\n+ * irdma_ieq_get_qp - get qp based on quad in puda buffer\n+ * @dev: hardware control device structure\n+ * @buf: receive puda buffer on exception q\n+ */\n+struct irdma_sc_qp *irdma_ieq_get_qp(struct irdma_sc_dev *dev,\n+\t\t\t\t     struct irdma_puda_buf *buf)\n+{\n+\tstruct irdma_qp *iwqp;\n+\tstruct irdma_cm_node *cm_node;\n+\tstruct irdma_device *iwdev = buf->vsi->back_vsi;\n+\tu32 loc_addr[4] = {};\n+\tu32 rem_addr[4] = {};\n+\tu16 loc_port, rem_port;\n+\tstruct ipv6hdr *ip6h;\n+\tstruct iphdr *iph = (struct iphdr *)buf->iph;\n+\tstruct tcphdr *tcph = (struct tcphdr *)buf->tcph;\n+\tstruct irdma_pci_f *rf = dev->back_dev;\n+\tstruct udphdr *udph;\n+\tstruct irdma_bth *bth;\n+\n+\tif (iph->protocol == IPPROTO_UDP) {\n+\t\tudph = (struct udphdr *)tcph;\n+\t\tbth = (struct irdma_bth *)udph + sizeof(*udph);\n+\t\tiwqp = rf->qp_table[be32_to_cpu(bth->qpn)];\n+\t\treturn &iwqp->sc_qp;\n+\t}\n+\n+\tif (iph->version == 4) {\n+\t\tloc_addr[0] = ntohl(iph->daddr);\n+\t\trem_addr[0] = ntohl(iph->saddr);\n+\t} else {\n+\t\tip6h = (struct ipv6hdr *)buf->iph;\n+\t\tirdma_copy_ip_ntohl(loc_addr, ip6h->daddr.in6_u.u6_addr32);\n+\t\tirdma_copy_ip_ntohl(rem_addr, ip6h->saddr.in6_u.u6_addr32);\n+\t}\n+\tloc_port = ntohs(tcph->dest);\n+\trem_port = ntohs(tcph->source);\n+\tcm_node = irdma_find_node(&iwdev->cm_core, rem_port, rem_addr, loc_port,\n+\t\t\t\t  loc_addr, false, true);\n+\tif (!cm_node)\n+\t\treturn NULL;\n+\n+\tiwqp = cm_node->iwqp;\n+\n+\treturn &iwqp->sc_qp;\n+}\n+\n+/**\n+ * irdma_send_ieq_ack - ACKs for duplicate or OOO partials FPDUs\n+ * @qp: qp ptr\n+ */\n+void irdma_send_ieq_ack(struct irdma_sc_qp *qp)\n+{\n+\tstruct irdma_cm_node *cm_node = ((struct irdma_qp *)qp->qp_uk.back_qp)->cm_node;\n+\tstruct irdma_puda_buf *buf = qp->pfpdu.lastrcv_buf;\n+\tstruct tcphdr *tcph = (struct tcphdr *)buf->tcph;\n+\n+\tcm_node->tcp_cntxt.rcv_nxt = qp->pfpdu.nextseqnum;\n+\tcm_node->tcp_cntxt.loc_seq_num = ntohl(tcph->ack_seq);\n+\n+\tirdma_send_ack(cm_node);\n+}\n+\n+/**\n+ * irdma_puda_ieq_get_ah_info - get AH info from IEQ buffer\n+ * @qp: qp pointer\n+ * @ah_info: AH info pointer\n+ */\n+void irdma_puda_ieq_get_ah_info(struct irdma_sc_qp *qp,\n+\t\t\t\tstruct irdma_ah_info *ah_info)\n+{\n+\tstruct irdma_puda_buf *buf = qp->pfpdu.ah_buf;\n+\tstruct iphdr *iph;\n+\tstruct ipv6hdr *ip6h;\n+\n+\tmemset(ah_info, 0, sizeof(*ah_info));\n+\tah_info->do_lpbk = true;\n+\tah_info->vlan_tag = buf->vlan_id;\n+\tah_info->insert_vlan_tag = buf->vlan_valid;\n+\tah_info->ipv4_valid = buf->ipv4;\n+\tah_info->vsi = qp->vsi;\n+\n+\tif (buf->smac_valid)\n+\t\tether_addr_copy(ah_info->mac_addr, buf->smac);\n+\n+\tif (buf->ipv4) {\n+\t\tah_info->ipv4_valid = true;\n+\t\tiph = (struct iphdr *)buf->iph;\n+\t\tah_info->hop_ttl = iph->ttl;\n+\t\tah_info->tc_tos = iph->tos;\n+\t\tah_info->dest_ip_addr[0] = ntohl(iph->daddr);\n+\t\tah_info->src_ip_addr[0] = ntohl(iph->saddr);\n+\t} else {\n+\t\tip6h = (struct ipv6hdr *)buf->iph;\n+\t\tah_info->hop_ttl = ip6h->hop_limit;\n+\t\tah_info->tc_tos = ip6h->priority;\n+\t\tirdma_copy_ip_ntohl(ah_info->dest_ip_addr,\n+\t\t\t\t    ip6h->daddr.in6_u.u6_addr32);\n+\t\tirdma_copy_ip_ntohl(ah_info->src_ip_addr,\n+\t\t\t\t    ip6h->saddr.in6_u.u6_addr32);\n+\t}\n+\n+\tah_info->dst_arpindex = irdma_arp_table(qp->dev->back_dev,\n+\t\t\t\t\t\tah_info->dest_ip_addr,\n+\t\t\t\t\t\tah_info->ipv4_valid,\n+\t\t\t\t\t\tNULL, IRDMA_ARP_RESOLVE);\n+}\n+\n+/**\n+ * irdma_gen1_ieq_update_tcpip_info - update tcpip in the buffer\n+ * @buf: puda to update\n+ * @len: length of buffer\n+ * @seqnum: seq number for tcp\n+ */\n+static void irdma_gen1_ieq_update_tcpip_info(struct irdma_puda_buf *buf,\n+\t\t\t\t\t     u16 len, u32 seqnum)\n+{\n+\tstruct tcphdr *tcph;\n+\tstruct iphdr *iph;\n+\tu16 iphlen;\n+\tu16 pktsize;\n+\tu8 *addr = buf->mem.va;\n+\n+\tiphlen = (buf->ipv4) ? 20 : 40;\n+\tiph = (struct iphdr *)(addr + buf->maclen);\n+\ttcph = (struct tcphdr *)(addr + buf->maclen + iphlen);\n+\tpktsize = len + buf->tcphlen + iphlen;\n+\tiph->tot_len = htons(pktsize);\n+\ttcph->seq = htonl(seqnum);\n+}\n+\n+/**\n+ * irdma_ieq_update_tcpip_info - update tcpip in the buffer\n+ * @buf: puda to update\n+ * @len: length of buffer\n+ * @seqnum: seq number for tcp\n+ */\n+void irdma_ieq_update_tcpip_info(struct irdma_puda_buf *buf, u16 len,\n+\t\t\t\t u32 seqnum)\n+{\n+\tstruct tcphdr *tcph;\n+\tu8 *addr;\n+\n+\tif (buf->vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)\n+\t\treturn irdma_gen1_ieq_update_tcpip_info(buf, len, seqnum);\n+\n+\taddr = buf->mem.va;\n+\ttcph = (struct tcphdr *)addr;\n+\ttcph->seq = htonl(seqnum);\n+}\n+\n+/**\n+ * irdma_gen1_puda_get_tcpip_info - get tcpip info from puda\n+ * buffer\n+ * @info: to get information\n+ * @buf: puda buffer\n+ */\n+static enum irdma_status_code\n+irdma_gen1_puda_get_tcpip_info(struct irdma_puda_cmpl_info *info,\n+\t\t\t       struct irdma_puda_buf *buf)\n+{\n+\tstruct iphdr *iph;\n+\tstruct ipv6hdr *ip6h;\n+\tstruct tcphdr *tcph;\n+\tu16 iphlen;\n+\tu16 pkt_len;\n+\tu8 *mem = buf->mem.va;\n+\tstruct ethhdr *ethh = buf->mem.va;\n+\n+\tif (ethh->h_proto == htons(0x8100)) {\n+\t\tinfo->vlan_valid = true;\n+\t\tbuf->vlan_id = ntohs(((struct vlan_ethhdr *)ethh)->h_vlan_TCI) &\n+\t\t\t       VLAN_VID_MASK;\n+\t}\n+\n+\tbuf->maclen = (info->vlan_valid) ? 18 : 14;\n+\tiphlen = (info->l3proto) ? 40 : 20;\n+\tbuf->ipv4 = (info->l3proto) ? false : true;\n+\tbuf->iph = mem + buf->maclen;\n+\tiph = (struct iphdr *)buf->iph;\n+\tbuf->tcph = buf->iph + iphlen;\n+\ttcph = (struct tcphdr *)buf->tcph;\n+\n+\tif (buf->ipv4) {\n+\t\tpkt_len = ntohs(iph->tot_len);\n+\t} else {\n+\t\tip6h = (struct ipv6hdr *)buf->iph;\n+\t\tpkt_len = ntohs(ip6h->payload_len) + iphlen;\n+\t}\n+\n+\tbuf->totallen = pkt_len + buf->maclen;\n+\n+\tif (info->payload_len < buf->totallen) {\n+\t\tdev_dbg(rfdev_to_dev(buf->vsi->dev),\n+\t\t\t\"ERR: payload_len = 0x%x totallen expected0x%x\\n\",\n+\t\t\tinfo->payload_len, buf->totallen);\n+\t\treturn IRDMA_ERR_INVALID_SIZE;\n+\t}\n+\n+\tbuf->tcphlen = tcph->doff << 2;\n+\tbuf->datalen = pkt_len - iphlen - buf->tcphlen;\n+\tbuf->data = buf->datalen ? buf->tcph + buf->tcphlen : NULL;\n+\tbuf->hdrlen = buf->maclen + iphlen + buf->tcphlen;\n+\tbuf->seqnum = ntohl(tcph->seq);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * irdma_puda_get_tcpip_info - get tcpip info from puda buffer\n+ * @info: to get information\n+ * @buf: puda buffer\n+ */\n+enum irdma_status_code\n+irdma_puda_get_tcpip_info(struct irdma_puda_cmpl_info *info,\n+\t\t\t  struct irdma_puda_buf *buf)\n+{\n+\tstruct tcphdr *tcph;\n+\tu32 pkt_len;\n+\tu8 *mem;\n+\n+\tif (buf->vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)\n+\t\treturn irdma_gen1_puda_get_tcpip_info(info, buf);\n+\n+\tmem = buf->mem.va;\n+\tbuf->vlan_valid = info->vlan_valid;\n+\tif (info->vlan_valid)\n+\t\tbuf->vlan_id = info->vlan;\n+\n+\tbuf->ipv4 = info->ipv4;\n+\tif (buf->ipv4)\n+\t\tbuf->iph = mem + IRDMA_IPV4_PAD;\n+\telse\n+\t\tbuf->iph = mem;\n+\n+\tbuf->tcph = mem + IRDMA_TCP_OFFSET;\n+\ttcph = (struct tcphdr *)buf->tcph;\n+\tpkt_len = info->payload_len;\n+\tbuf->totallen = pkt_len;\n+\tbuf->tcphlen = tcph->doff << 2;\n+\tbuf->datalen = pkt_len - IRDMA_TCP_OFFSET - buf->tcphlen;\n+\tbuf->data = buf->datalen ? buf->tcph + buf->tcphlen : NULL;\n+\tbuf->hdrlen = IRDMA_TCP_OFFSET + buf->tcphlen;\n+\tbuf->seqnum = ntohl(tcph->seq);\n+\n+\tif (info->smac_valid) {\n+\t\tether_addr_copy(buf->smac, info->smac);\n+\t\tbuf->smac_valid = true;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * irdma_process_stats - Checking for wrap and update stats\n+ *\n+ * @pestat: stats structure pointer\n+ */\n+static void irdma_process_stats(struct irdma_vsi_pestat *pestat)\n+{\n+\tstruct irdma_gather_stats *gather_stats =\n+\t\tpestat->gather_info.gather_stats;\n+\tstruct irdma_gather_stats *last_gather_stats =\n+\t\tpestat->gather_info.last_gather_stats;\n+\tirdma_update_stats(&pestat->hw_stats, gather_stats, last_gather_stats);\n+}\n+\n+/**\n+ * irdma_cqp_gather_stats_gen1 - Gather stats\n+ * @dev: pointer to device structure\n+ * @pestat: statistics structure\n+ */\n+static void irdma_cqp_gather_stats_gen1(struct irdma_sc_dev *dev,\n+\t\t\t\t\tstruct irdma_vsi_pestat *pestat)\n+{\n+\tstruct irdma_gather_stats *gather_stats =\n+\t\tpestat->gather_info.gather_stats;\n+\tu32 stats_inst_offset_32;\n+\tu32 stats_inst_offset_64;\n+\n+\tstats_inst_offset_32 = (pestat->gather_info.use_stats_inst) ?\n+\t\t\t\t       pestat->gather_info.stats_inst_index :\n+\t\t\t\t       pestat->hw->hmc.hmc_fn_id;\n+\tstats_inst_offset_32 *= 4;\n+\tstats_inst_offset_64 = stats_inst_offset_32 * 2;\n+\n+\tgather_stats->rxvlanerr =\n+\t\trd32(dev->hw,\n+\t\t     dev->hw_stats_regs_32[IRDMA_HW_STAT_INDEX_RXVLANERR]\n+\t\t     + stats_inst_offset_32);\n+\tgather_stats->ip4rxdiscard =\n+\t\trd32(dev->hw,\n+\t\t     dev->hw_stats_regs_32[IRDMA_HW_STAT_INDEX_IP4RXDISCARD]\n+\t\t     + stats_inst_offset_32);\n+\tgather_stats->ip4rxtrunc =\n+\t\trd32(dev->hw,\n+\t\t     dev->hw_stats_regs_32[IRDMA_HW_STAT_INDEX_IP4RXTRUNC]\n+\t\t     + stats_inst_offset_32);\n+\tgather_stats->ip4txnoroute =\n+\t\trd32(dev->hw,\n+\t\t     dev->hw_stats_regs_32[IRDMA_HW_STAT_INDEX_IP4TXNOROUTE]\n+\t\t     + stats_inst_offset_32);\n+\tgather_stats->ip6rxdiscard =\n+\t\trd32(dev->hw,\n+\t\t     dev->hw_stats_regs_32[IRDMA_HW_STAT_INDEX_IP6RXDISCARD]\n+\t\t     + stats_inst_offset_32);\n+\tgather_stats->ip6rxtrunc =\n+\t\trd32(dev->hw,\n+\t\t     dev->hw_stats_regs_32[IRDMA_HW_STAT_INDEX_IP6RXTRUNC]\n+\t\t     + stats_inst_offset_32);\n+\tgather_stats->ip6txnoroute =\n+\t\trd32(dev->hw,\n+\t\t     dev->hw_stats_regs_32[IRDMA_HW_STAT_INDEX_IP6TXNOROUTE]\n+\t\t     + stats_inst_offset_32);\n+\tgather_stats->tcprtxseg =\n+\t\trd32(dev->hw,\n+\t\t     dev->hw_stats_regs_32[IRDMA_HW_STAT_INDEX_TCPRTXSEG]\n+\t\t     + stats_inst_offset_32);\n+\tgather_stats->tcprxopterr =\n+\t\trd32(dev->hw,\n+\t\t     dev->hw_stats_regs_32[IRDMA_HW_STAT_INDEX_TCPRXOPTERR]\n+\t\t     + stats_inst_offset_32);\n+\n+\tgather_stats->ip4rxocts =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP4RXOCTS]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->ip4rxpkts =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP4RXPKTS]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->ip4txfrag =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP4RXFRAGS]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->ip4rxmcpkts =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP4RXMCPKTS]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->ip4txocts =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP4TXOCTS]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->ip4txpkts =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP4TXPKTS]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->ip4txfrag =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP4TXFRAGS]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->ip4txmcpkts =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP4TXMCPKTS]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->ip6rxocts =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP6RXOCTS]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->ip6rxpkts =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP6RXPKTS]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->ip6txfrags =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP6RXFRAGS]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->ip6rxmcpkts =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP6RXMCPKTS]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->ip6txocts =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP6TXOCTS]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->ip6txpkts =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP6TXPKTS]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->ip6txfrags =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP6TXFRAGS]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->ip6txmcpkts =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_IP6TXMCPKTS]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->tcprxsegs =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_TCPRXSEGS]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->tcptxsegs =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_TCPTXSEG]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->rdmarxrds =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_RDMARXRDS]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->rdmarxsnds =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_RDMARXSNDS]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->rdmarxwrs =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_RDMARXWRS]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->rdmatxrds =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_RDMATXRDS]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->rdmatxsnds =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_RDMATXSNDS]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->rdmatxwrs =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_RDMATXWRS]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->rdmavbn =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_RDMAVBND]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->rdmavinv =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_RDMAVINV]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->udprxpkts =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_UDPRXPKTS]\n+\t\t     + stats_inst_offset_64);\n+\tgather_stats->udptxpkts =\n+\t\trd64(dev->hw,\n+\t\t     dev->hw_stats_regs_64[IRDMA_HW_STAT_INDEX_UDPTXPKTS]\n+\t\t     + stats_inst_offset_64);\n+\n+\tirdma_process_stats(pestat);\n+}\n+\n+/**\n+ * irdma_process_cqp_stats - Checking for wrap and update stats\n+ * @cqp_request: cqp_request structure pointer\n+ */\n+static void irdma_process_cqp_stats(struct irdma_cqp_request *cqp_request)\n+{\n+\tstruct irdma_vsi_pestat *pestat = cqp_request->param;\n+\n+\tirdma_process_stats(pestat);\n+}\n+\n+/**\n+ * irdma_cqp_gather_stats_cmd - Gather stats\n+ * @dev: pointer to device structure\n+ * @pestat: pointer to stats info\n+ * @wait: flag to wait or not wait for stats\n+ */\n+enum irdma_status_code\n+irdma_cqp_gather_stats_cmd(struct irdma_sc_dev *dev,\n+\t\t\t   struct irdma_vsi_pestat *pestat, bool wait)\n+\n+{\n+\tstruct irdma_pci_f *rf = dev->back_dev;\n+\tstruct irdma_cqp *iwcqp = &rf->cqp;\n+\tstruct irdma_cqp_request *cqp_request;\n+\tstruct cqp_cmds_info *cqp_info;\n+\tenum irdma_status_code status;\n+\n+\tcqp_request = irdma_get_cqp_request(iwcqp, wait);\n+\tif (!cqp_request)\n+\t\treturn IRDMA_ERR_NO_MEMORY;\n+\n+\tcqp_info = &cqp_request->info;\n+\tmemset(cqp_info, 0, sizeof(*cqp_info));\n+\tcqp_info->cqp_cmd = IRDMA_OP_STATS_GATHER;\n+\tcqp_info->post_sq = 1;\n+\tcqp_info->in.u.stats_gather.info = pestat->gather_info;\n+\tcqp_info->in.u.stats_gather.scratch = (uintptr_t)cqp_request;\n+\tcqp_info->in.u.stats_gather.cqp = &rf->cqp.sc_cqp;\n+\tcqp_request->param = pestat;\n+\tif (!wait)\n+\t\tcqp_request->callback_fcn = irdma_process_cqp_stats;\n+\tstatus = irdma_handle_cqp_op(rf, cqp_request);\n+\tif (status)\n+\t\tdev_dbg(rfdev_to_dev(dev), \"ERR: CQP STATS_GATHER fail\");\n+\telse if (wait)\n+\t\tirdma_process_stats(pestat);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * irdma_hw_stats_timeout - Stats timer-handler which updates all HW stats\n+ * @t: timer_list pointer\n+ */\n+static void irdma_hw_stats_timeout(struct timer_list *t)\n+{\n+\tstruct irdma_vsi_pestat *pf_devstat =\n+\t\tfrom_timer(pf_devstat, t, stats_timer);\n+\tstruct irdma_sc_vsi *sc_vsi = pf_devstat->vsi;\n+\tstruct irdma_device *iwdev = sc_vsi->back_vsi;\n+\n+\tif (iwdev->init_state != RDMA_DEV_REGISTERED)\n+\t\tgoto exit;\n+\tif (sc_vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1)\n+\t\tirdma_cqp_gather_stats_gen1(sc_vsi->dev, sc_vsi->pestat);\n+\telse\n+\t\tirdma_cqp_gather_stats_cmd(sc_vsi->dev, sc_vsi->pestat, false);\n+\n+exit:\n+\tmod_timer(&pf_devstat->stats_timer,\n+\t\t  jiffies + msecs_to_jiffies(STATS_TIMER_DELAY));\n+}\n+\n+/**\n+ * irdma_hw_stats_start_timer - Start periodic stats timer\n+ * @vsi: vsi structure pointer\n+ */\n+void irdma_hw_stats_start_timer(struct irdma_sc_vsi *vsi)\n+{\n+\tstruct irdma_vsi_pestat *devstat = vsi->pestat;\n+\n+\ttimer_setup(&devstat->stats_timer, irdma_hw_stats_timeout, 0);\n+\tmod_timer(&devstat->stats_timer,\n+\t\t  jiffies + msecs_to_jiffies(STATS_TIMER_DELAY));\n+}\n+\n+/**\n+ * irdma_hw_stats_del_timer - Delete periodic stats timer\n+ * @vsi: pointer to vsi structure\n+ */\n+void irdma_hw_stats_stop_timer(struct irdma_sc_vsi *vsi)\n+{\n+\tstruct irdma_vsi_pestat *devstat = vsi->pestat;\n+\n+\tdel_timer_sync(&devstat->stats_timer);\n+}\n+\n+/**\n+ * irdma_cqp_stats_inst_cmd - Allocate/free stats instance\n+ * @vsi: pointer to vsi structure\n+ * @cmd: command to allocate or free\n+ * @stats_info: pointer to allocate stats info\n+ */\n+enum irdma_status_code\n+irdma_cqp_stats_inst_cmd(struct irdma_sc_vsi *vsi, u8 cmd,\n+\t\t\t struct irdma_stats_inst_info *stats_info)\n+{\n+\tstruct irdma_pci_f *rf = vsi->dev->back_dev;\n+\tstruct irdma_cqp *iwcqp = &rf->cqp;\n+\tstruct irdma_cqp_request *cqp_request;\n+\tstruct cqp_cmds_info *cqp_info;\n+\tenum irdma_status_code status;\n+\tbool wait = false;\n+\n+\tif (cmd == IRDMA_OP_STATS_ALLOCATE)\n+\t\twait = true;\n+\tcqp_request = irdma_get_cqp_request(iwcqp, wait);\n+\tif (!cqp_request)\n+\t\treturn IRDMA_ERR_NO_MEMORY;\n+\n+\tcqp_info = &cqp_request->info;\n+\tmemset(cqp_info, 0, sizeof(*cqp_info));\n+\tcqp_info->cqp_cmd = cmd;\n+\tcqp_info->post_sq = 1;\n+\tcqp_info->in.u.stats_manage.info = *stats_info;\n+\tcqp_info->in.u.stats_manage.scratch = (uintptr_t)cqp_request;\n+\tcqp_info->in.u.stats_manage.cqp = &rf->cqp.sc_cqp;\n+\tstatus = irdma_handle_cqp_op(rf, cqp_request);\n+\tif (status)\n+\t\tdev_dbg(rfdev_to_dev(&rf->sc_dev),\n+\t\t\t\"ERR: CQP MANAGE_STATS fail\");\n+\telse if (wait)\n+\t\tstats_info->stats_idx = cqp_request->compl_info.op_ret_val;\n+\n+\treturn status;\n+}\n+\n+/**\n+ * irdma_cqp_ceq_cmd - Create/Destroy CEQ's after CEQ 0\n+ * @dev: pointer to device info\n+ * @sc_ceq: pointer to ceq structure\n+ * @op: Create or Destroy\n+ */\n+enum irdma_status_code irdma_cqp_ceq_cmd(struct irdma_sc_dev *dev,\n+\t\t\t\t\t struct irdma_sc_ceq *sc_ceq, u8 op)\n+{\n+\tstruct irdma_cqp_request *cqp_request;\n+\tstruct cqp_cmds_info *cqp_info;\n+\tstruct irdma_pci_f *rf = dev->back_dev;\n+\n+\tcqp_request = irdma_get_cqp_request(&rf->cqp, true);\n+\tif (!cqp_request)\n+\t\treturn IRDMA_ERR_NO_MEMORY;\n+\n+\tcqp_info = &cqp_request->info;\n+\tcqp_info->post_sq = 1;\n+\tcqp_info->cqp_cmd = op;\n+\tcqp_info->in.u.ceq_create.ceq = sc_ceq;\n+\tcqp_info->in.u.ceq_create.scratch = (uintptr_t)cqp_request;\n+\n+\treturn irdma_handle_cqp_op(rf, cqp_request);\n+}\n+\n+/**\n+ * irdma_cqp_ws_node_cmd - Add/modify/delete ws node\n+ * @dev: pointer to device structure\n+ * @cmd: Add, modify or delete\n+ * @node_info: pointer to ws node info\n+ */\n+enum irdma_status_code\n+irdma_cqp_ws_node_cmd(struct irdma_sc_dev *dev, u8 cmd,\n+\t\t      struct irdma_ws_node_info *node_info)\n+{\n+\tstruct irdma_pci_f *rf = dev->back_dev;\n+\tstruct irdma_cqp *iwcqp = &rf->cqp;\n+\tstruct irdma_sc_cqp *cqp = &iwcqp->sc_cqp;\n+\tstruct irdma_cqp_request *cqp_request;\n+\tstruct cqp_cmds_info *cqp_info;\n+\tenum irdma_status_code status;\n+\tbool poll;\n+\n+\tif (!rf->sc_dev.ceq_valid)\n+\t\tpoll = true;\n+\telse\n+\t\tpoll = false;\n+\n+\tcqp_request = irdma_get_cqp_request(iwcqp, !poll);\n+\tif (!cqp_request)\n+\t\treturn IRDMA_ERR_NO_MEMORY;\n+\n+\tcqp_info = &cqp_request->info;\n+\tmemset(cqp_info, 0, sizeof(*cqp_info));\n+\tcqp_info->cqp_cmd = cmd;\n+\tcqp_info->post_sq = 1;\n+\tcqp_info->in.u.ws_node.info = *node_info;\n+\tcqp_info->in.u.ws_node.cqp = cqp;\n+\tcqp_info->in.u.ws_node.scratch = (uintptr_t)cqp_request;\n+\tstatus = irdma_handle_cqp_op(rf, cqp_request);\n+\tif (status) {\n+\t\tdev_dbg(rfdev_to_dev(dev), \"ERR: CQP WS_NODE fail\\n\");\n+\t\treturn status;\n+\t}\n+\n+\tif (poll) {\n+\t\tstruct irdma_ccq_cqe_info compl_info;\n+\n+\t\tstatus = cqp->dev->cqp_ops->poll_for_cqp_op_done(cqp,\n+\t\t\t\t\t\t\t\t IRDMA_CQP_OP_WORK_SCHED_NODE,\n+\t\t\t\t\t\t\t\t &compl_info);\n+\t\tnode_info->qs_handle = compl_info.op_ret_val;\n+\t\tdev_dbg(rfdev_to_dev(cqp->dev),\n+\t\t\t\"DCB: opcode=%d, compl_info.retval=%d\\n\",\n+\t\t\tcompl_info.op_code, compl_info.op_ret_val);\n+\t} else {\n+\t\tnode_info->qs_handle = cqp_request->compl_info.op_ret_val;\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * irdma_cqp_up_map_cmd - Set the up-up mapping\n+ * @dev: pointer to device structure\n+ * @cmd: map command\n+ * @map_info: pointer to up map info\n+ */\n+enum irdma_status_code irdma_cqp_up_map_cmd(struct irdma_sc_dev *dev, u8 cmd,\n+\t\t\t\t\t    struct irdma_up_info *map_info)\n+{\n+\tstruct irdma_pci_f *rf = dev->back_dev;\n+\tstruct irdma_cqp *iwcqp = &rf->cqp;\n+\tstruct irdma_sc_cqp *cqp = &iwcqp->sc_cqp;\n+\tstruct irdma_cqp_request *cqp_request;\n+\tstruct cqp_cmds_info *cqp_info;\n+\tenum irdma_status_code status;\n+\n+\tcqp_request = irdma_get_cqp_request(iwcqp, false);\n+\tif (!cqp_request)\n+\t\treturn IRDMA_ERR_NO_MEMORY;\n+\n+\tcqp_info = &cqp_request->info;\n+\tmemset(cqp_info, 0, sizeof(*cqp_info));\n+\tcqp_info->cqp_cmd = cmd;\n+\tcqp_info->post_sq = 1;\n+\tcqp_info->in.u.up_map.info = *map_info;\n+\tcqp_info->in.u.up_map.cqp = cqp;\n+\tcqp_info->in.u.up_map.scratch = (uintptr_t)cqp_request;\n+\tstatus = irdma_handle_cqp_op(rf, cqp_request);\n+\tif (status)\n+\t\tdev_dbg(rfdev_to_dev(dev), \"ERR: CQP UP MAP fail\\n\");\n+\n+\treturn status;\n+}\n+\n+/**\n+ * irdma_ah_cqp_op - perform an AH cqp operation\n+ * @rf: RDMA PCI function\n+ * @sc_ah: address handle\n+ * @cmd: AH operation\n+ * @wait: wait if true\n+ * @callback_fcn: Callback function on CQP op completion\n+ * @cb_param: parameter for callback function\n+ *\n+ * returns errno\n+ */\n+int irdma_ah_cqp_op(struct irdma_pci_f *rf, struct irdma_sc_ah *sc_ah, u8 cmd,\n+\t\t    bool wait,\n+\t\t    void (*callback_fcn)(struct irdma_cqp_request *),\n+\t\t    void *cb_param)\n+{\n+\tstruct irdma_cqp_request *cqp_request;\n+\tstruct cqp_cmds_info *cqp_info;\n+\tenum irdma_status_code status;\n+\n+\tcqp_request = irdma_get_cqp_request(&rf->cqp, wait);\n+\tif (!cqp_request)\n+\t\treturn -ENOMEM;\n+\n+\tcqp_info = &cqp_request->info;\n+\tcqp_info->cqp_cmd = cmd;\n+\tcqp_info->post_sq = 1;\n+\tif (cmd == IRDMA_OP_AH_CREATE) {\n+\t\tcqp_info->in.u.ah_create.info = sc_ah->ah_info;\n+\t\tcqp_info->in.u.ah_create.scratch = (uintptr_t)cqp_request;\n+\t\tcqp_info->in.u.ah_create.cqp = &rf->cqp.sc_cqp;\n+\t} else if (cmd == IRDMA_OP_AH_DESTROY) {\n+\t\tcqp_info->in.u.ah_destroy.info = sc_ah->ah_info;\n+\t\tcqp_info->in.u.ah_destroy.scratch = (uintptr_t)cqp_request;\n+\t\tcqp_info->in.u.ah_destroy.cqp = &rf->cqp.sc_cqp;\n+\t} else {\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tif (!wait) {\n+\t\tcqp_request->callback_fcn = callback_fcn;\n+\t\tcqp_request->param = cb_param;\n+\t}\n+\tstatus = irdma_handle_cqp_op(rf, cqp_request);\n+\tif (!status) {\n+\t\tif (wait) {\n+\t\t\tif (cmd == IRDMA_OP_AH_CREATE)\n+\t\t\t\tsc_ah->ah_info.ah_valid = true;\n+\t\t\telse\n+\t\t\t\tsc_ah->ah_info.ah_valid = false;\n+\t\t}\n+\t} else {\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * irdma_ieq_ah_cb - callback after creation of AH for IEQ\n+ * @cqp_request: pointer to cqp_request of create AH\n+ */\n+static void irdma_ieq_ah_cb(struct irdma_cqp_request *cqp_request)\n+{\n+\tstruct irdma_sc_qp *qp = cqp_request->param;\n+\tstruct irdma_sc_ah *sc_ah = qp->pfpdu.ah;\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&qp->pfpdu.lock, flags);\n+\tif (!cqp_request->compl_info.op_ret_val) {\n+\t\tsc_ah->ah_info.ah_valid = true;\n+\t\tirdma_ieq_process_fpdus(qp, qp->vsi->ieq);\n+\t} else {\n+\t\tsc_ah->ah_info.ah_valid = false;\n+\t\tirdma_ieq_cleanup_qp(qp->vsi->ieq, qp);\n+\t}\n+\tspin_unlock_irqrestore(&qp->pfpdu.lock, flags);\n+}\n+\n+/**\n+ * irdma_ilq_ah_cb - callback after creation of AH for ILQ\n+ * @cqp_request: pointer to cqp_request of create AH\n+ */\n+static void irdma_ilq_ah_cb(struct irdma_cqp_request *cqp_request)\n+{\n+\tstruct irdma_cm_node *cm_node = cqp_request->param;\n+\tstruct irdma_sc_ah *sc_ah = cm_node->ah;\n+\n+\tif (!cqp_request->compl_info.op_ret_val)\n+\t\tsc_ah->ah_info.ah_valid = true;\n+\telse\n+\t\tsc_ah->ah_info.ah_valid = false;\n+}\n+\n+/**\n+ * irdma_puda_create_ah - create AH for ILQ/IEQ qp's\n+ * @dev: device pointer\n+ * @ah_info: Address handle info\n+ * @wait: When true will wait for operation to complete\n+ * @type: ILQ/IEQ\n+ * @cb_param: Callback param when not waiting\n+ * @ah_ret: Returned pointer to address handle if created\n+ *\n+ */\n+enum irdma_status_code irdma_puda_create_ah(struct irdma_sc_dev *dev,\n+\t\t\t\t\t    struct irdma_ah_info *ah_info,\n+\t\t\t\t\t    bool wait, enum puda_rsrc_type type,\n+\t\t\t\t\t    void *cb_param,\n+\t\t\t\t\t    struct irdma_sc_ah **ah_ret)\n+{\n+\tstruct irdma_sc_ah *ah;\n+\tstruct irdma_pci_f *rf = dev->back_dev;\n+\tint err;\n+\n+\tah = kzalloc(sizeof(*ah), GFP_ATOMIC);\n+\t*ah_ret = ah;\n+\tif (!ah)\n+\t\treturn IRDMA_ERR_NO_MEMORY;\n+\n+\terr = irdma_alloc_rsrc(rf, rf->allocated_ahs, rf->max_ah,\n+\t\t\t       &ah_info->ah_idx, &rf->next_ah);\n+\tif (err)\n+\t\tgoto err_free;\n+\n+\tah->dev = dev;\n+\tah->ah_info = *ah_info;\n+\n+\tif (type == IRDMA_PUDA_RSRC_TYPE_ILQ)\n+\t\terr = irdma_ah_cqp_op(rf, ah, IRDMA_OP_AH_CREATE, wait,\n+\t\t\t\t      irdma_ilq_ah_cb, cb_param);\n+\telse\n+\t\terr = irdma_ah_cqp_op(rf, ah, IRDMA_OP_AH_CREATE, wait,\n+\t\t\t\t      irdma_ieq_ah_cb, cb_param);\n+\n+\tif (err)\n+\t\tgoto error;\n+\treturn 0;\n+\n+error:\n+\tirdma_free_rsrc(rf, rf->allocated_ahs, ah->ah_info.ah_idx);\n+err_free:\n+\tkfree(ah);\n+\t*ah_ret = NULL;\n+\treturn IRDMA_ERR_NO_MEMORY;\n+}\n+\n+/**\n+ * irdma_puda_free_ah - free a puda address handle\n+ * @dev: device pointer\n+ * @ah: The address handle to free\n+ */\n+void irdma_puda_free_ah(struct irdma_sc_dev *dev, struct irdma_sc_ah *ah)\n+{\n+\tstruct irdma_pci_f *rf = dev->back_dev;\n+\n+\tif (!ah)\n+\t\treturn;\n+\n+\tif (ah->ah_info.ah_valid) {\n+\t\tirdma_ah_cqp_op(rf, ah, IRDMA_OP_AH_DESTROY, false, NULL, NULL);\n+\t\tirdma_free_rsrc(rf, rf->allocated_ahs, ah->ah_info.ah_idx);\n+\t}\n+\n+\tkfree(ah);\n+}\n+\n+/**\n+ * irdma_gsi_ud_qp_ah_cb - callback after creation of AH for GSI/ID QP\n+ * @cqp_request: pointer to cqp_request of create AH\n+ */\n+void irdma_gsi_ud_qp_ah_cb(struct irdma_cqp_request *cqp_request)\n+{\n+\tstruct irdma_sc_ah *sc_ah = cqp_request->param;\n+\n+\tif (!cqp_request->compl_info.op_ret_val)\n+\t\tsc_ah->ah_info.ah_valid = true;\n+\telse\n+\t\tsc_ah->ah_info.ah_valid = false;\n+}\n+\n+/**\n+ * irdma_prm_add_pble_mem - add moemory to pble resources\n+ * @pprm: pble resource manager\n+ * @pchunk: chunk of memory to add\n+ */\n+enum irdma_status_code irdma_prm_add_pble_mem(struct irdma_pble_prm *pprm,\n+\t\t\t\t\t      struct irdma_chunk *pchunk)\n+{\n+\tu64 sizeofbitmap;\n+\n+\tif (pchunk->size & 0xfff)\n+\t\treturn IRDMA_ERR_PARAM;\n+\n+\tsizeofbitmap = (u64)pchunk->size >> pprm->pble_shift;\n+\n+\tpchunk->bitmapmem.size = sizeofbitmap >> 3;\n+\tpchunk->bitmapmem.va = kzalloc(pchunk->bitmapmem.size, GFP_ATOMIC);\n+\n+\tif (!pchunk->bitmapmem.va)\n+\t\treturn IRDMA_ERR_NO_MEMORY;\n+\n+\tpchunk->bitmapbuf = pchunk->bitmapmem.va;\n+\tbitmap_zero(pchunk->bitmapbuf, sizeofbitmap);\n+\n+\tpchunk->sizeofbitmap = sizeofbitmap;\n+\t/* each pble is 8 bytes hence shift by 3 */\n+\tpprm->total_pble_alloc += pchunk->size >> 3;\n+\tpprm->free_pble_cnt += pchunk->size >> 3;\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * irdma_prm_add_pble_mem - get pble's from prm\n+ * @pprm: pble resource manager\n+ * @chunkinfo: nformation about chunk where pble's were acquired\n+ * @mem_size: size of pble memory needed\n+ * @vaddr: returns virtual address of pble memory\n+ * @fpm_addr: returns fpm address of pble memory\n+ */\n+enum irdma_status_code\n+irdma_prm_get_pbles(struct irdma_pble_prm *pprm,\n+\t\t    struct irdma_pble_chunkinfo *chunkinfo, u32 mem_size,\n+\t\t    u64 *vaddr, u64 *fpm_addr)\n+{\n+\tu64 bits_needed;\n+\tu64 bit_idx = PBLE_INVALID_IDX;\n+\tstruct irdma_chunk *pchunk = NULL;\n+\tstruct list_head *chunk_entry = pprm->clist.next;\n+\tu32 offset;\n+\tunsigned long flags;\n+\t*vaddr = 0;\n+\t*fpm_addr = 0;\n+\n+\tbits_needed = (mem_size + (1 << pprm->pble_shift) - 1) >> pprm->pble_shift;\n+\n+\tspin_lock_irqsave(&pprm->prm_lock, flags);\n+\twhile (chunk_entry != &pprm->clist) {\n+\t\tpchunk = (struct irdma_chunk *)chunk_entry;\n+\t\tbit_idx = bitmap_find_next_zero_area(pchunk->bitmapbuf,\n+\t\t\t\t\t\t     pchunk->sizeofbitmap, 0,\n+\t\t\t\t\t\t     bits_needed, 0);\n+\t\tif (bit_idx < pchunk->sizeofbitmap)\n+\t\t\tbreak;\n+\n+\t\t/* list.next used macro */\n+\t\tchunk_entry = pchunk->list.next;\n+\t}\n+\n+\tif (!pchunk || bit_idx >= pchunk->sizeofbitmap) {\n+\t\tspin_unlock_irqrestore(&pprm->prm_lock, flags);\n+\t\treturn IRDMA_ERR_NO_MEMORY;\n+\t}\n+\n+\tbitmap_set(pchunk->bitmapbuf, bit_idx, bits_needed);\n+\toffset = bit_idx << pprm->pble_shift;\n+\t*vaddr = pchunk->vaddr + offset;\n+\t*fpm_addr = pchunk->fpm_addr + offset;\n+\n+\tchunkinfo->pchunk = pchunk;\n+\tchunkinfo->bit_idx = bit_idx;\n+\tchunkinfo->bits_used = bits_needed;\n+\t/* 3 is sizeof pble divide */\n+\tpprm->free_pble_cnt -= chunkinfo->bits_used << (pprm->pble_shift - 3);\n+\tspin_unlock_irqrestore(&pprm->prm_lock, flags);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * irdma_prm_return pbles - return pbles back to prm\n+ * @pprm: pble resource manager\n+ * @chunkinfo: chunk where pble's were acquired and to be freed\n+ */\n+void irdma_prm_return_pbles(struct irdma_pble_prm *pprm,\n+\t\t\t    struct irdma_pble_chunkinfo *chunkinfo)\n+{\n+\tunsigned long flags;\n+\n+\tspin_lock_irqsave(&pprm->prm_lock, flags);\n+\tpprm->free_pble_cnt += chunkinfo->bits_used << (pprm->pble_shift - 3);\n+\tbitmap_clear(chunkinfo->pchunk->bitmapbuf, chunkinfo->bit_idx,\n+\t\t     chunkinfo->bits_used);\n+\tspin_unlock_irqrestore(&pprm->prm_lock, flags);\n+}\n+\n+/**\n+ * irdma_free_paged_mem - free virtual paged memory back to system\n+ * @chunk: chunk to free with paged memory\n+ */\n+void irdma_pble_free_paged_mem(struct irdma_chunk *chunk)\n+{\n+\tstruct pci_dev *pcidev = chunk->dev->hw->pdev;\n+\tint i;\n+\n+\tif (!chunk->pg_cnt)\n+\t\tgoto done;\n+\n+\tfor (i = 0; i < chunk->pg_cnt; i++)\n+\t\tdma_unmap_page(&pcidev->dev, chunk->dmainfo.dmaaddrs[i],\n+\t\t\t       PAGE_SIZE, DMA_BIDIRECTIONAL);\n+\n+done:\n+\tkfree(chunk->dmainfo.dmaaddrs);\n+\tchunk->dmainfo.dmaaddrs = NULL;\n+\tvfree((void *)(uintptr_t)chunk->vaddr);\n+\tchunk->vaddr = 0;\n+\tchunk->type = 0;\n+}\n+\n+/**\n+ * irdma_pble_get_paged_mem -allocate paged memory for pbles\n+ * @chunk: chunk to add for paged memory\n+ * @pg_cnt: number of pages needed\n+ */\n+enum irdma_status_code irdma_pble_get_paged_mem(struct irdma_chunk *chunk,\n+\t\t\t\t\t\tint pg_cnt)\n+{\n+\tstruct pci_dev *pcidev = chunk->dev->hw->pdev;\n+\tstruct page *page;\n+\tu8 *addr;\n+\tu32 size;\n+\tint i;\n+\n+\tchunk->dmainfo.dmaaddrs = kzalloc(pg_cnt << 3, GFP_KERNEL);\n+\tif (!chunk->dmainfo.dmaaddrs)\n+\t\treturn IRDMA_ERR_NO_MEMORY;\n+\n+\tsize = PAGE_SIZE * pg_cnt;\n+\tchunk->vaddr = (uintptr_t)vmalloc(size);\n+\tif (!chunk->vaddr) {\n+\t\tkfree(chunk->dmainfo.dmaaddrs);\n+\t\tchunk->dmainfo.dmaaddrs = NULL;\n+\t\treturn IRDMA_ERR_NO_MEMORY;\n+\t}\n+\n+\tchunk->size = size;\n+\taddr = (u8 *)(uintptr_t)chunk->vaddr;\n+\n+\tfor (i = 0; i < pg_cnt; i++) {\n+\t\tpage = vmalloc_to_page((void *)addr);\n+\t\tif (!page)\n+\t\t\tbreak;\n+\n+\t\tchunk->dmainfo.dmaaddrs[i] = dma_map_page(&pcidev->dev, page, 0,\n+\t\t\t\t\t\t\t  PAGE_SIZE,\n+\t\t\t\t\t\t\t  DMA_BIDIRECTIONAL);\n+\t\tif (dma_mapping_error(&pcidev->dev, chunk->dmainfo.dmaaddrs[i]))\n+\t\t\tbreak;\n+\n+\t\taddr += PAGE_SIZE;\n+\t}\n+\n+\tchunk->pg_cnt = i;\n+\tchunk->type = PBLE_SD_PAGED;\n+\tif (i == pg_cnt)\n+\t\treturn 0;\n+\n+\tirdma_pble_free_paged_mem(chunk);\n+\n+\treturn IRDMA_ERR_NO_MEMORY;\n+}\n+\n+/**\n+ * irdma_alloc_ws_node_id - Allocate a tx scheduler node ID\n+ * @dev: device pointer\n+ */\n+u16 irdma_alloc_ws_node_id(struct irdma_sc_dev *dev)\n+{\n+\tstruct irdma_pci_f *rf = dev->back_dev;\n+\tu32 next = 1;\n+\tu32 node_id;\n+\n+\tif (irdma_alloc_rsrc(rf, rf->allocated_ws_nodes, rf->max_ws_node_id,\n+\t\t\t     &node_id, &next))\n+\t\treturn IRDMA_WS_NODE_INVALID;\n+\n+\treturn (u16)node_id;\n+}\n+\n+/**\n+ * irdma_free_ws_node_id - Free a tx scheduler node ID\n+ * @dev: device pointer\n+ * @node_id: Work scheduler node ID\n+ */\n+void irdma_free_ws_node_id(struct irdma_sc_dev *dev, u16 node_id)\n+{\n+\tstruct irdma_pci_f *rf = dev->back_dev;\n+\n+\tirdma_free_rsrc(rf, rf->allocated_ws_nodes, (u32)node_id);\n+}\n+\n+/**\n+ * irdma_modify_qp_to_err - Modify a QP to error\n+ * @sc_qp: qp structure\n+ */\n+void irdma_modify_qp_to_err(struct irdma_sc_qp *sc_qp)\n+{\n+\tstruct irdma_qp *qp = sc_qp->qp_uk.back_qp;\n+\tstruct ib_qp_attr attr;\n+\n+\tattr.qp_state = IB_QPS_ERR;\n+\tirdma_modify_qp(&qp->ibqp, &attr, IB_QP_STATE, NULL);\n+}\n",
    "prefixes": [
        "rdma-nxt",
        "12/16"
    ]
}