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GET /api/patches/1165379/?format=api
{ "id": 1165379, "url": "http://patchwork.ozlabs.org/api/patches/1165379/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190920091724.51767-7-alice.michael@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190920091724.51767-7-alice.michael@intel.com>", "list_archive_url": null, "date": "2019-09-20T09:17:21", "name": "[next,S10,07/10] i40e: initialize ITRN registers with correct values", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "f020c3192e44e429f358538e7ea974a4caae8b98", "submitter": { "id": 71123, "url": "http://patchwork.ozlabs.org/api/people/71123/?format=api", "name": "Michael, Alice", "email": "alice.michael@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190920091724.51767-7-alice.michael@intel.com/mbox/", "series": [ { "id": 131822, "url": "http://patchwork.ozlabs.org/api/series/131822/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=131822", "date": "2019-09-20T09:17:21", "name": null, "version": 1, "mbox": "http://patchwork.ozlabs.org/series/131822/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1165379/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1165379/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.137; helo=fraxinus.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 46Zgw01XJcz9sNf\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 21 Sep 2019 03:39:59 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 2365F85764;\n\tFri, 20 Sep 2019 17:39:58 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id pEnbNsZLnytj; Fri, 20 Sep 2019 17:39:57 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 94313857B0;\n\tFri, 20 Sep 2019 17:39:57 +0000 (UTC)", "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\tby ash.osuosl.org (Postfix) with ESMTP id F06F11BF9AF\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 20 Sep 2019 17:39:53 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id EDB3E857D8\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 20 Sep 2019 17:39:53 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id Ot6zX4MsuaMV for <intel-wired-lan@lists.osuosl.org>;\n\tFri, 20 Sep 2019 17:39:53 +0000 (UTC)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby fraxinus.osuosl.org (Postfix) with ESMTPS id 40F7A85764\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 20 Sep 2019 17:39:53 +0000 (UTC)", "from fmsmga004.fm.intel.com ([10.253.24.48])\n\tby orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t20 Sep 2019 10:39:52 -0700", "from alicemic-1.jf.intel.com ([10.166.17.62])\n\tby fmsmga004.fm.intel.com with ESMTP; 20 Sep 2019 10:39:51 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,529,1559545200\"; d=\"scan'208\";a=\"212635338\"", "From": "Alice Michael <alice.michael@intel.com>", "To": "alice.michael@intel.com,\n\tintel-wired-lan@lists.osuosl.org", "Date": "Fri, 20 Sep 2019 02:17:21 -0700", "Message-Id": "<20190920091724.51767-7-alice.michael@intel.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190920091724.51767-1-alice.michael@intel.com>", "References": "<20190920091724.51767-1-alice.michael@intel.com>", "MIME-Version": "1.0", "Subject": "[Intel-wired-lan] [next PATCH S10 07/10] i40e: initialize ITRN\n\tregisters with correct values", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Nicholas Nunley <nicholas.d.nunley@intel.com>\n\nSince commit 92418fb14750 (\"i40e/i40evf: Use usec value instead of reg\nvalue for ITR defines\") the driver tracks the interrupt throttling\nintervals in single usec units, although the actual ITRN/ITR0 registers are\nprogrammed in 2 usec units. Most register programming flows in the driver\ncorrectly handle the conversion, although it is currently not applied when\nthe registers are initialized to their default values. Most of the time\nthis doesn't present a problem since the default values are usually\nimmediately overwritten through the standard adaptive throttling mechanism,\nor updated manually by the user, but if adaptive throttling is disabled and\nthe interval values are left alone then the incorrect value will persist.\n\nSince the intended default interval of 50 usecs (vs. 100 usecs as\nprogrammed) performs better for most traffic workloads, this can lead to\nperformance regressions.\n\nThis patch adds the correct conversion when writing the initial values to\nthe ITRN registers.\n\nSigned-off-by: Nicholas Nunley <nicholas.d.nunley@intel.com>\n---\n drivers/net/ethernet/intel/i40e/i40e_main.c | 10 +++++-----\n 1 file changed, 5 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c\nindex f158760511ab..22394da6cb94 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_main.c\n+++ b/drivers/net/ethernet/intel/i40e/i40e_main.c\n@@ -3534,14 +3534,14 @@ static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)\n \t\tq_vector->rx.target_itr =\n \t\t\tITR_TO_REG(vsi->rx_rings[i]->itr_setting);\n \t\twr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),\n-\t\t q_vector->rx.target_itr);\n+\t\t q_vector->rx.target_itr >> 1);\n \t\tq_vector->rx.current_itr = q_vector->rx.target_itr;\n \n \t\tq_vector->tx.next_update = jiffies + 1;\n \t\tq_vector->tx.target_itr =\n \t\t\tITR_TO_REG(vsi->tx_rings[i]->itr_setting);\n \t\twr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),\n-\t\t q_vector->tx.target_itr);\n+\t\t q_vector->tx.target_itr >> 1);\n \t\tq_vector->tx.current_itr = q_vector->tx.target_itr;\n \n \t\twr32(hw, I40E_PFINT_RATEN(vector - 1),\n@@ -3646,11 +3646,11 @@ static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)\n \t/* set the ITR configuration */\n \tq_vector->rx.next_update = jiffies + 1;\n \tq_vector->rx.target_itr = ITR_TO_REG(vsi->rx_rings[0]->itr_setting);\n-\twr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.target_itr);\n+\twr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.target_itr >> 1);\n \tq_vector->rx.current_itr = q_vector->rx.target_itr;\n \tq_vector->tx.next_update = jiffies + 1;\n \tq_vector->tx.target_itr = ITR_TO_REG(vsi->tx_rings[0]->itr_setting);\n-\twr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.target_itr);\n+\twr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.target_itr >> 1);\n \tq_vector->tx.current_itr = q_vector->tx.target_itr;\n \n \ti40e_enable_misc_int_causes(pf);\n@@ -11396,7 +11396,7 @@ static int i40e_setup_misc_vector(struct i40e_pf *pf)\n \n \t/* associate no queues to the misc vector */\n \twr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);\n-\twr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);\n+\twr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K >> 1);\n \n \ti40e_flush(hw);\n \n", "prefixes": [ "next", "S10", "07/10" ] }