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GET /api/patches/1162631/?format=api
{ "id": 1162631, "url": "http://patchwork.ozlabs.org/api/patches/1162631/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190916065240.41486-1-sasha.neftin@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190916065240.41486-1-sasha.neftin@intel.com>", "list_archive_url": null, "date": "2019-09-16T06:52:40", "name": "[v1] e1000e: Add support for S0ix", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "2b8c997d6f025820da31235517030f8ad87cd4b0", "submitter": { "id": 69860, "url": "http://patchwork.ozlabs.org/api/people/69860/?format=api", "name": "Sasha Neftin", "email": "sasha.neftin@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190916065240.41486-1-sasha.neftin@intel.com/mbox/", "series": [ { "id": 130771, "url": "http://patchwork.ozlabs.org/api/series/130771/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=130771", "date": "2019-09-16T06:52:40", "name": "[v1] e1000e: Add support for S0ix", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/130771/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1162631/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1162631/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.136; helo=silver.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 46WxlB5zdKz9sNF\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 16 Sep 2019 16:52:52 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 5436A20524;\n\tMon, 16 Sep 2019 06:52:51 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id vvRRvASzpu5D; Mon, 16 Sep 2019 06:52:47 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby silver.osuosl.org (Postfix) with ESMTP id 550052043E;\n\tMon, 16 Sep 2019 06:52:47 +0000 (UTC)", "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\tby ash.osuosl.org (Postfix) with ESMTP id 6F0361BF94D\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 16 Sep 2019 06:52:45 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 3172385582\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 16 Sep 2019 06:52:45 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id m8e9uO870o4r for <intel-wired-lan@lists.osuosl.org>;\n\tMon, 16 Sep 2019 06:52:43 +0000 (UTC)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n\tby whitealder.osuosl.org (Postfix) with ESMTPS id 170B58555A\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tMon, 16 Sep 2019 06:52:43 +0000 (UTC)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t15 Sep 2019 23:52:42 -0700", "from ccdlinuxdev08.iil.intel.com ([143.185.161.150])\n\tby fmsmga002.fm.intel.com with ESMTP; 15 Sep 2019 23:52:40 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,510,1559545200\"; d=\"scan'208\";a=\"216108925\"", "From": "Sasha Neftin <sasha.neftin@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Mon, 16 Sep 2019 09:52:40 +0300", "Message-Id": "<20190916065240.41486-1-sasha.neftin@intel.com>", "X-Mailer": "git-send-email 2.11.0", "Subject": "[Intel-wired-lan] [PATCH v1] e1000e: Add support for S0ix", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Cc": "Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "Implement flow for S0ix support. Modern SoCs support S0ix low power\nstates during idle periods, which are sub-states of ACPI S0 that increase\npower saving while supporting an instant-on experience for providing\nlower latency that ACPI S0. The S0ix states shut off parts of the SoC\nwhen they are not in use, while still maintaning optimal performance.\nThis patch add support for S0ix started from an Ice Lake platform.\n\nSuggested-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>\nSigned-off-by: Vitaly Lifshits <vitaly.lifshits@intel.com>\nSigned-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com>\nSigned-off-by: Sasha Neftin <sasha.neftin@intel.com>\n---\n drivers/net/ethernet/intel/e1000e/netdev.c | 186 +++++++++++++++++++++++++++++\n drivers/net/ethernet/intel/e1000e/regs.h | 4 +\n 2 files changed, 190 insertions(+)", "diff": "diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c\nindex d7d56e42a6aa..cc4363e67072 100644\n--- a/drivers/net/ethernet/intel/e1000e/netdev.c\n+++ b/drivers/net/ethernet/intel/e1000e/netdev.c\n@@ -6294,6 +6294,178 @@ static void e1000e_flush_lpic(struct pci_dev *pdev)\n \tpm_runtime_put_sync(netdev->dev.parent);\n }\n \n+/* S0ix implementation */\n+static int e1000e_s0ix_entry_flow(struct e1000_adapter *adapter)\n+{\n+\tstruct e1000_hw *hw = &adapter->hw;\n+\tu32 mac_data;\n+\tu16 phy_data;\n+\n+\t/* Disable the periodic inband message,\n+\t * don't request PCIe clock in K1 page770_17[10:9] = 10b\n+\t */\n+\te1e_rphy(hw, HV_PM_CTRL, &phy_data);\n+\tphy_data &= ~HV_PM_CTRL_K1_CLK_REQ;\n+\tphy_data |= BIT(10);\n+\te1e_wphy(hw, HV_PM_CTRL, phy_data);\n+\n+\t/* Make sure we don't exit K1 every time a new packet arrives\n+\t * 772_29[5] = 1 CS_Mode_Stay_In_K1\n+\t */\n+\te1e_rphy(hw, I217_CGFREG, &phy_data);\n+\tphy_data |= BIT(5);\n+\te1e_wphy(hw, I217_CGFREG, phy_data);\n+\n+\t/* Change the MAC/PHY interface to SMBus\n+\t * Force the SMBus in PHY page769_23[0] = 1\n+\t * Force the SMBus in MAC CTRL_EXT[11] = 1\n+\t */\n+\te1e_rphy(hw, CV_SMB_CTRL, &phy_data);\n+\tphy_data |= CV_SMB_CTRL_FORCE_SMBUS;\n+\te1e_wphy(hw, CV_SMB_CTRL, phy_data);\n+\tmac_data = er32(CTRL_EXT);\n+\tmac_data |= E1000_CTRL_EXT_FORCE_SMBUS;\n+\tew32(CTRL_EXT, mac_data);\n+\n+\t/* DFT control: PHY bit: page769_20[0] = 1\n+\t * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1\n+\t */\n+\te1e_rphy(hw, I82579_DFT_CTRL, &phy_data);\n+\tphy_data |= BIT(0);\n+\te1e_wphy(hw, I82579_DFT_CTRL, phy_data);\n+\n+\tmac_data = er32(EXTCNF_CTRL);\n+\tmac_data |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;\n+\tew32(EXTCNF_CTRL, mac_data);\n+\n+\t/* Check MAC Tx/Rx packet buffer pointers.\n+\t * Reset MAC Tx/Rx packet buffer pointers to suppress any\n+\t * pending traffic indication that would prevent power gating.\n+\t */\n+\tmac_data = er32(TDFH);\n+\tif (mac_data)\n+\t\tew32(TDFH, 0);\n+\tmac_data = er32(TDFT);\n+\tif (mac_data)\n+\t\tew32(TDFT, 0);\n+\tmac_data = er32(TDFHS);\n+\tif (mac_data)\n+\t\tew32(TDFHS, 0);\n+\tmac_data = er32(TDFTS);\n+\tif (mac_data)\n+\t\tew32(TDFTS, 0);\n+\tmac_data = er32(TDFPC);\n+\tif (mac_data)\n+\t\tew32(TDFPC, 0);\n+\tmac_data = er32(RDFH);\n+\tif (mac_data)\n+\t\tew32(RDFH, 0);\n+\tmac_data = er32(RDFT);\n+\tif (mac_data)\n+\t\tew32(RDFT, 0);\n+\tmac_data = er32(RDFHS);\n+\tif (mac_data)\n+\t\tew32(RDFHS, 0);\n+\tmac_data = er32(RDFTS);\n+\tif (mac_data)\n+\t\tew32(RDFTS, 0);\n+\tmac_data = er32(RDFPC);\n+\tif (mac_data)\n+\t\tew32(RDFPC, 0);\n+\n+\t/* Enable the Dynamic Power Gating in the MAC */\n+\tmac_data = er32(FEXTNVM7);\n+\tmac_data |= BIT(22);\n+\tew32(FEXTNVM7, mac_data);\n+\n+\t/* Disable the time synchronization clock */\n+\tmac_data = er32(FEXTNVM7);\n+\tmac_data |= BIT(31);\n+\tmac_data &= ~BIT(0);\n+\tew32(FEXTNVM7, mac_data);\n+\n+\t/* Dynamic Power Gating Enable */\n+\tmac_data = er32(CTRL_EXT);\n+\tmac_data |= BIT(3);\n+\tew32(CTRL_EXT, mac_data);\n+\n+\t/* Enable the Dynamic Clock Gating in the DMA and MAC */\n+\tmac_data = er32(CTRL_EXT);\n+\tmac_data |= E1000_CTRL_EXT_DMA_DYN_CLK_EN;\n+\tew32(CTRL_EXT, mac_data);\n+\n+\t/* No MAC DPG gating SLP_S0 in modern standby\n+\t * Switch the logic of the lanphypc to use PMC counter\n+\t */\n+\tmac_data = er32(FEXTNVM5);\n+\tmac_data |= BIT(7);\n+\tew32(FEXTNVM5, mac_data);\n+\n+\treturn 0;\n+}\n+\n+static int e1000e_s0ix_exit_flow(struct e1000_adapter *adapter)\n+{\n+\tstruct e1000_hw *hw = &adapter->hw;\n+\tu32 mac_data;\n+\tu16 phy_data;\n+\n+\t/* Disable the Dynamic Power Gating in the MAC */\n+\tmac_data = er32(FEXTNVM7);\n+\tmac_data &= 0xFFBFFFFF;\n+\tew32(FEXTNVM7, mac_data);\n+\n+\t/* Enable the time synchronization clock */\n+\tmac_data = er32(FEXTNVM7);\n+\tmac_data |= BIT(0);\n+\tew32(FEXTNVM7, mac_data);\n+\n+\t/* Disable Dynamic Power Gating */\n+\tmac_data = er32(CTRL_EXT);\n+\tmac_data &= 0xFFFFFFF7;\n+\tew32(CTRL_EXT, mac_data);\n+\n+\t/* Disable the Dynamic Clock Gating in the DMA and MAC */\n+\tmac_data = er32(CTRL_EXT);\n+\tmac_data &= 0xFFF7FFFF;\n+\tew32(CTRL_EXT, mac_data);\n+\n+\t/* Revert the lanphypc logic to use the internal Gbe counter\n+\t * and not the PMC counter\n+\t */\n+\tmac_data = er32(FEXTNVM5);\n+\tmac_data &= 0xFFFFFF7F;\n+\tew32(FEXTNVM5, mac_data);\n+\n+\t/* Enable the periodic inband message,\n+\t * Request PCIe clock in K1 page770_17[10:9] =01b\n+\t */\n+\te1e_rphy(hw, HV_PM_CTRL, &phy_data);\n+\tphy_data &= 0xFBFF;\n+\tphy_data |= HV_PM_CTRL_K1_CLK_REQ;\n+\te1e_wphy(hw, HV_PM_CTRL, phy_data);\n+\n+\t/* Return back configuration\n+\t * 772_29[5] = 0 CS_Mode_Stay_In_K1\n+\t */\n+\te1e_rphy(hw, I217_CGFREG, &phy_data);\n+\tphy_data &= 0xFFDF;\n+\te1e_wphy(hw, I217_CGFREG, phy_data);\n+\n+\t/* Change the MAC/PHY interface to Kumeran\n+\t * Unforce the SMBus in PHY page769_23[0] = 0\n+\t * Unforce the SMBus in MAC CTRL_EXT[11] = 0\n+\t */\n+\te1e_rphy(hw, CV_SMB_CTRL, &phy_data);\n+\tphy_data &= ~CV_SMB_CTRL_FORCE_SMBUS;\n+\te1e_wphy(hw, CV_SMB_CTRL, phy_data);\n+\tmac_data = er32(CTRL_EXT);\n+\tmac_data &= ~E1000_CTRL_EXT_FORCE_SMBUS;\n+\tew32(CTRL_EXT, mac_data);\n+\n+\treturn 0;\n+}\n+\n static int e1000e_pm_freeze(struct device *dev)\n {\n \tstruct net_device *netdev = dev_get_drvdata(dev);\n@@ -6650,6 +6822,9 @@ static int e1000e_pm_thaw(struct device *dev)\n static int e1000e_pm_suspend(struct device *dev)\n {\n \tstruct pci_dev *pdev = to_pci_dev(dev);\n+\tstruct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));\n+\tstruct e1000_adapter *adapter = netdev_priv(netdev);\n+\tstruct e1000_hw *hw = &adapter->hw;\n \tint rc;\n \n \te1000e_flush_lpic(pdev);\n@@ -6660,14 +6835,25 @@ static int e1000e_pm_suspend(struct device *dev)\n \tif (rc)\n \t\te1000e_pm_thaw(dev);\n \n+\t/* Introduce S0ix implementation */\n+\tif (hw->mac.type >= e1000_pch_cnp)\n+\t\te1000e_s0ix_entry_flow(adapter);\n+\n \treturn rc;\n }\n \n static int e1000e_pm_resume(struct device *dev)\n {\n \tstruct pci_dev *pdev = to_pci_dev(dev);\n+\tstruct net_device *netdev = pci_get_drvdata(to_pci_dev(dev));\n+\tstruct e1000_adapter *adapter = netdev_priv(netdev);\n+\tstruct e1000_hw *hw = &adapter->hw;\n \tint rc;\n \n+\t/* Introduce S0ix implementation */\n+\tif (hw->mac.type >= e1000_pch_cnp)\n+\t\te1000e_s0ix_exit_flow(adapter);\n+\n \trc = __e1000_resume(pdev);\n \tif (rc)\n \t\treturn rc;\ndiff --git a/drivers/net/ethernet/intel/e1000e/regs.h b/drivers/net/ethernet/intel/e1000e/regs.h\nindex 47f5ca793970..df59fd1d660c 100644\n--- a/drivers/net/ethernet/intel/e1000e/regs.h\n+++ b/drivers/net/ethernet/intel/e1000e/regs.h\n@@ -18,6 +18,7 @@\n #define E1000_FEXTNVM\t0x00028\t/* Future Extended NVM - RW */\n #define E1000_FEXTNVM3\t0x0003C\t/* Future Extended NVM 3 - RW */\n #define E1000_FEXTNVM4\t0x00024\t/* Future Extended NVM 4 - RW */\n+#define E1000_FEXTNVM5\t0x00014\t/* Future Extended NVM 5 - RW */\n #define E1000_FEXTNVM6\t0x00010\t/* Future Extended NVM 6 - RW */\n #define E1000_FEXTNVM7\t0x000E4\t/* Future Extended NVM 7 - RW */\n #define E1000_FEXTNVM9\t0x5BB4\t/* Future Extended NVM 9 - RW */\n@@ -234,4 +235,7 @@\n #define E1000_RXMTRL\t0x0B634\t/* Time sync Rx EtherType and Msg Type - RW */\n #define E1000_RXUDP\t0x0B638\t/* Time Sync Rx UDP Port - RW */\n \n+/* PHY registers */\n+#define I82579_DFT_CTRL\tPHY_REG(769, 20)\n+\n #endif\n", "prefixes": [ "v1" ] }