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GET /api/patches/115921/?format=api
{ "id": 115921, "url": "http://patchwork.ozlabs.org/api/patches/115921/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-imx/patch/1316684408-12196-1-git-send-email-jason77.wang@gmail.com/", "project": { "id": 19, "url": "http://patchwork.ozlabs.org/api/projects/19/?format=api", "name": "Linux IMX development", "link_name": "linux-imx", "list_id": "linux-imx-kernel.lists.patchwork.ozlabs.org", "list_email": "linux-imx-kernel@lists.patchwork.ozlabs.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1316684408-12196-1-git-send-email-jason77.wang@gmail.com>", "list_archive_url": null, "date": "2011-09-22T09:40:08", "name": "ARM i.MX avic: convert to use generic irq chip", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "39b044957e0a86f56444956388cc3df5410fa049", "submitter": { "id": 6305, "url": "http://patchwork.ozlabs.org/api/people/6305/?format=api", "name": "Jason Wang", "email": "jason77.wang@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-imx/patch/1316684408-12196-1-git-send-email-jason77.wang@gmail.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/115921/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/115921/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming-imx@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-imx@bilbo.ozlabs.org", "Received": [ "from merlin.infradead.org (merlin.infradead.org\n\t[IPv6:2001:4978:20e::2])\n\t(using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits))\n\t(Client did not present a certificate)\n\tby ozlabs.org (Postfix) with ESMTPS id CB3A1B6F87\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tThu, 22 Sep 2011 19:40:20 +1000 (EST)", "from canuck.infradead.org ([2001:4978:20e::1])\n\tby merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux))\n\tid 1R6flO-0000Tg-El; Thu, 22 Sep 2011 09:40:14 +0000", "from localhost ([127.0.0.1] helo=canuck.infradead.org)\n\tby canuck.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux))\n\tid 1R6flO-0005Jx-1D; Thu, 22 Sep 2011 09:40:14 +0000", "from mail.windriver.com ([147.11.1.11])\n\tby canuck.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux))\n\tid 1R6flL-0005Je-3l for linux-arm-kernel@lists.infradead.org;\n\tThu, 22 Sep 2011 09:40:12 +0000", "from ALA-HCA.corp.ad.wrs.com (ala-hca [147.11.189.40])\n\tby mail.windriver.com (8.14.3/8.14.3) with ESMTP id p8M9e6oo015132\n\t(version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=FAIL);\n\tThu, 22 Sep 2011 02:40:07 -0700 (PDT)", "from localhost.localdomain (128.224.163.220) by\n\tALA-HCA.corp.ad.wrs.com (147.11.189.50) with Microsoft SMTP Server id\n\t14.1.255.0; Thu, 22 Sep 2011 02:40:06 -0700" ], "From": "Hui Wang <jason77.wang@gmail.com>", "To": "<s.hauer@pengutronix.de>, <u.kleine-koenig@pengutronix.de>", "Subject": "[PATCH] ARM i.MX avic: convert to use generic irq chip", "Date": "Thu, 22 Sep 2011 17:40:08 +0800", "Message-ID": "<1316684408-12196-1-git-send-email-jason77.wang@gmail.com>", "X-Mailer": "git-send-email 1.5.6.5", "MIME-Version": "1.0", "X-CRM114-Version": "20090807-BlameThorstenAndJenny ( TRE 0.7.6 (BSD) )\n\tMR-646709E3 ", "X-CRM114-CacheID": "sfid-20110922_054011_354952_33297E7F ", "X-CRM114-Status": "GOOD ( 19.10 )", "X-Spam-Score": "0.5 (/)", "X-Spam-Report": "SpamAssassin version 3.3.1 on canuck.infradead.org summary:\n\tContent analysis details: (0.5 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/,\n\tlow trust [147.11.1.11 listed in list.dnswl.org]\n\t0.0 FREEMAIL_FROM Sender email is commonly abused enduser mail\n\tprovider (jason77.wang[at]gmail.com)\n\t0.0 DKIM_ADSP_CUSTOM_MED No valid author signature, adsp_override is\n\tCUSTOM_MED 1.2 NML_ADSP_CUSTOM_MED ADSP custom_med hit,\n\tand not from a mailing list", "Cc": "linux-arm-kernel@lists.infradead.org", "X-BeenThere": "linux-arm-kernel@lists.infradead.org", "X-Mailman-Version": "2.1.12", "Precedence": "list", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/linux-arm-kernel/>", "List-Post": "<mailto:linux-arm-kernel@lists.infradead.org>", "List-Help": "<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "linux-arm-kernel-bounces@lists.infradead.org", "Errors-To": "linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org", "List-Id": "linux-imx-kernel.lists.patchwork.ozlabs.org" }, "content": "Convert i.MX avic irq handler to use generic irq chip. This not only\nprovides a cleanup implementation of irq chip handler, but also\nimplements suspend/resume interface with the help of generic irq chip\ninterface.\n\nChange mxc_irq_chip to a new structure mxc_extra_irq to handle fiq\nand priority functions.\n\nSigned-off-by: Hui Wang <jason77.wang@gmail.com>\n---\n\nThis patch is basing on imx-features branch of linux-pengu. Have\nvalidated this patch on 31pdk and 35pdk platforms, while have no\nchance to validate it on mx2 and mx1 platforms since we don't have\nthose hardwares.\n\nThe purpose of changing avic to use generic irq chip is because i\nadded suspend/resume functions for 35pdk, and generic irq chip\nnaturally has suspend/resume interface. If this patch can be\naccepted, i will continue to send out those 35pdk pm patches.\n\n arch/arm/plat-mxc/avic.c | 79 ++++++++++++++++++++++++++++------------\n arch/arm/plat-mxc/irq-common.c | 21 ++++++-----\n arch/arm/plat-mxc/irq-common.h | 3 +-\n arch/arm/plat-mxc/tzic.c | 8 ++++-\n 4 files changed, 75 insertions(+), 36 deletions(-)", "diff": "diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c\nindex 55d2534..846636a 100644\n--- a/arch/arm/plat-mxc/avic.c\n+++ b/arch/arm/plat-mxc/avic.c\n@@ -50,6 +50,8 @@\n \n void __iomem *avic_base;\n \n+static u32 avic_saved_mask_reg[2];\n+\n #ifdef CONFIG_MXC_IRQ_PRIOR\n static int avic_irq_set_priority(unsigned char irq, unsigned char prio)\n {\n@@ -90,24 +92,8 @@ static int avic_set_irq_fiq(unsigned int irq, unsigned int type)\n }\n #endif /* CONFIG_FIQ */\n \n-/* Disable interrupt number \"irq\" in the AVIC */\n-static void mxc_mask_irq(struct irq_data *d)\n-{\n-\t__raw_writel(d->irq, avic_base + AVIC_INTDISNUM);\n-}\n-\n-/* Enable interrupt number \"irq\" in the AVIC */\n-static void mxc_unmask_irq(struct irq_data *d)\n-{\n-\t__raw_writel(d->irq, avic_base + AVIC_INTENNUM);\n-}\n \n-static struct mxc_irq_chip mxc_avic_chip = {\n-\t.base = {\n-\t\t.irq_ack = mxc_mask_irq,\n-\t\t.irq_mask = mxc_mask_irq,\n-\t\t.irq_unmask = mxc_unmask_irq,\n-\t},\n+static struct mxc_extra_irq avic_extra_irq = {\n #ifdef CONFIG_MXC_IRQ_PRIOR\n \t.set_priority = avic_irq_set_priority,\n #endif\n@@ -116,6 +102,56 @@ static struct mxc_irq_chip mxc_avic_chip = {\n #endif\n };\n \n+\n+#ifdef CONFIG_PM\n+static void avic_irq_suspend(struct irq_data *d)\n+{\n+\tstruct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);\n+\tstruct irq_chip_type *ct = gc->chip_types;\n+\tint idx = gc->irq_base >> 5;\n+\n+\tavic_saved_mask_reg[idx] = __raw_readl(avic_base + ct->regs.mask);\n+\t__raw_writel(gc->wake_active, avic_base + ct->regs.mask);\n+}\n+\n+static void avic_irq_resume(struct irq_data *d)\n+{\n+\tstruct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);\n+\tstruct irq_chip_type *ct = gc->chip_types;\n+\tint idx = gc->irq_base >> 5;\n+\n+\t__raw_writel(avic_saved_mask_reg[idx], avic_base + ct->regs.mask);\n+}\n+\n+#else\n+#define avic_irq_suspend NULL\n+#define avic_irq_resume NULL\n+#endif\n+\n+static __init void avic_init_gc(unsigned int irq_start)\n+{\n+\tstruct irq_chip_generic *gc;\n+\tstruct irq_chip_type *ct;\n+\tint idx = irq_start >> 5;\n+\n+\tgc = irq_alloc_generic_chip(\"mxc-avic\", 1, irq_start, avic_base,\n+\t\t\t\t handle_level_irq);\n+\tgc->private = &avic_extra_irq;\n+\tgc->wake_enabled = IRQ_MSK(32);\n+\n+\tct = gc->chip_types;\n+\tct->chip.irq_mask = irq_gc_mask_clr_bit;\n+\tct->chip.irq_unmask = irq_gc_mask_set_bit;\n+\tct->chip.irq_ack = irq_gc_mask_clr_bit;\n+\tct->chip.irq_set_wake = irq_gc_set_wake;\n+\tct->chip.irq_suspend = avic_irq_suspend;\n+\tct->chip.irq_resume = avic_irq_resume;\n+\tct->regs.mask = !idx ? AVIC_INTENABLEL : AVIC_INTENABLEH;\n+\tct->regs.ack = ct->regs.mask;\n+\n+\tirq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);\n+}\n+\n /*\n * This function initializes the AVIC hardware and disables all the\n * interrupts. It registers the interrupt enable and disable functions\n@@ -140,11 +176,9 @@ void __init mxc_init_irq(void __iomem *irqbase)\n \t/* all IRQ no FIQ */\n \t__raw_writel(0, avic_base + AVIC_INTTYPEH);\n \t__raw_writel(0, avic_base + AVIC_INTTYPEL);\n-\tfor (i = 0; i < AVIC_NUM_IRQS; i++) {\n-\t\tirq_set_chip_and_handler(i, &mxc_avic_chip.base,\n-\t\t\t\t\t handle_level_irq);\n-\t\tset_irq_flags(i, IRQF_VALID);\n-\t}\n+\n+\tfor (i = 0; i < AVIC_NUM_IRQS; i += 32)\n+\t\tavic_init_gc(i);\n \n \t/* Set default priority value (0) for all IRQ's */\n \tfor (i = 0; i < 8; i++)\n@@ -157,4 +191,3 @@ void __init mxc_init_irq(void __iomem *irqbase)\n \n \tprintk(KERN_INFO \"MXC IRQ initialized\\n\");\n }\n-\ndiff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c\nindex 96953e2..b6e1145 100644\n--- a/arch/arm/plat-mxc/irq-common.c\n+++ b/arch/arm/plat-mxc/irq-common.c\n@@ -23,17 +23,17 @@\n \n int imx_irq_set_priority(unsigned char irq, unsigned char prio)\n {\n-\tstruct mxc_irq_chip *chip;\n-\tstruct irq_chip *base;\n+\tstruct irq_chip_generic *gc;\n+\tstruct mxc_extra_irq *exirq;\n \tint ret;\n \n \tret = -ENOSYS;\n \n-\tbase = irq_get_chip(irq);\n-\tif (base) {\n-\t\tchip = container_of(base, struct mxc_irq_chip, base);\n-\t\tif (chip->set_priority)\n-\t\t\tret = chip->set_priority(irq, prio);\n+\tgc = irq_get_chip_data(irq);\n+\tif (gc && gc->private) {\n+\t\texirq = gc->private;\n+\t\tif (exirq->set_priority)\n+\t\t\tret = exirq->set_priority(irq, prio);\n \t}\n \n \treturn ret;\n@@ -43,15 +43,16 @@ EXPORT_SYMBOL(imx_irq_set_priority);\n int mxc_set_irq_fiq(unsigned int irq, unsigned int type)\n {\n \tstruct irq_chip_generic *gc;\n-\tint (*set_irq_fiq)(unsigned int, unsigned int);\n+\tstruct mxc_extra_irq *exirq;\n \tint ret;\n \n \tret = -ENOSYS;\n \n \tgc = irq_get_chip_data(irq);\n \tif (gc && gc->private) {\n-\t\tset_irq_fiq = gc->private;\n-\t\tret = set_irq_fiq(irq, type);\n+\t\texirq = gc->private;\n+\t\tif (exirq->set_irq_fiq)\n+\t\t\tret = exirq->set_irq_fiq(irq, type);\n \t}\n \n \treturn ret;\ndiff --git a/arch/arm/plat-mxc/irq-common.h b/arch/arm/plat-mxc/irq-common.h\nindex 7203543..6ccb3a1 100644\n--- a/arch/arm/plat-mxc/irq-common.h\n+++ b/arch/arm/plat-mxc/irq-common.h\n@@ -19,9 +19,8 @@\n #ifndef __PLAT_MXC_IRQ_COMMON_H__\n #define __PLAT_MXC_IRQ_COMMON_H__\n \n-struct mxc_irq_chip\n+struct mxc_extra_irq\n {\n-\tstruct irq_chip\tbase;\n \tint (*set_priority)(unsigned char irq, unsigned char prio);\n \tint (*set_irq_fiq)(unsigned int irq, unsigned int type);\n };\ndiff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c\nindex f257fcc..a580750 100644\n--- a/arch/arm/plat-mxc/tzic.c\n+++ b/arch/arm/plat-mxc/tzic.c\n@@ -74,6 +74,12 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)\n \n static unsigned int *wakeup_intr[4];\n \n+static struct mxc_extra_irq tzic_extra_irq = {\n+#ifdef CONFIG_FIQ\n+\t.set_irq_fiq = tzic_set_irq_fiq,\n+#endif\n+};\n+\n static __init void tzic_init_gc(unsigned int irq_start)\n {\n \tstruct irq_chip_generic *gc;\n@@ -82,7 +88,7 @@ static __init void tzic_init_gc(unsigned int irq_start)\n \n \tgc = irq_alloc_generic_chip(\"tzic\", 1, irq_start, tzic_base,\n \t\t\t\t handle_level_irq);\n-\tgc->private = tzic_set_irq_fiq;\n+\tgc->private = &tzic_extra_irq;\n \tgc->wake_enabled = IRQ_MSK(32);\n \twakeup_intr[idx] = &gc->wake_active;\n \n", "prefixes": [] }