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GET /api/patches/1154083/?format=api
{ "id": 1154083, "url": "http://patchwork.ozlabs.org/api/patches/1154083/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190827131354.12703-9-anthony.l.nguyen@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190827131354.12703-9-anthony.l.nguyen@intel.com>", "list_archive_url": null, "date": "2019-08-27T13:13:54", "name": "[S28,9/9] ice: Rework around device/function capabilities", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "f256cfa182ae6c00d4723bf56755f35c31c47577", "submitter": { "id": 68875, "url": "http://patchwork.ozlabs.org/api/people/68875/?format=api", "name": "Tony Nguyen", "email": "anthony.l.nguyen@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190827131354.12703-9-anthony.l.nguyen@intel.com/mbox/", "series": [ { "id": 127658, "url": "http://patchwork.ozlabs.org/api/series/127658/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=127658", "date": "2019-08-27T13:13:48", "name": "[S28,1/9] ice: Reliably reset VFs", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/127658/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1154083/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1154083/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.133; helo=hemlock.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 46J2Rc18pSz9sDQ\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 28 Aug 2019 07:43:07 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id D174488665;\n\tTue, 27 Aug 2019 21:43:05 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id KyLkrtDB-BMi; Tue, 27 Aug 2019 21:43:05 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 011D388613;\n\tTue, 27 Aug 2019 21:43:05 +0000 (UTC)", "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\tby ash.osuosl.org (Postfix) with ESMTP id 727941BF4E3\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 27 Aug 2019 21:43:01 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 6FF6686B05\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 27 Aug 2019 21:43:01 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id CbwqasGlAe0V for <intel-wired-lan@lists.osuosl.org>;\n\tTue, 27 Aug 2019 21:43:00 +0000 (UTC)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n\tby fraxinus.osuosl.org (Postfix) with ESMTPS id 2420186AB5\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 27 Aug 2019 21:43:00 +0000 (UTC)", "from orsmga008.jf.intel.com ([10.7.209.65])\n\tby orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t27 Aug 2019 14:42:59 -0700", "from unknown (HELO localhost.jf.intel.com) ([10.166.244.174])\n\tby orsmga008.jf.intel.com with ESMTP; 27 Aug 2019 14:42:59 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,438,1559545200\"; d=\"scan'208\";a=\"174703669\"", "From": "Tony Nguyen <anthony.l.nguyen@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Tue, 27 Aug 2019 06:13:54 -0700", "Message-Id": "<20190827131354.12703-9-anthony.l.nguyen@intel.com>", "X-Mailer": "git-send-email 2.20.1", "In-Reply-To": "<20190827131354.12703-1-anthony.l.nguyen@intel.com>", "References": "<20190827131354.12703-1-anthony.l.nguyen@intel.com>", "MIME-Version": "1.0", "Subject": "[Intel-wired-lan] [PATCH S28 9/9] ice: Rework around\n\tdevice/function capabilities", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>\n\nice_parse_caps is printing capabilities in a different way when\ncompared to the variable names. This makes it difficult to search for\nthe right strings in the debug logs. So this patch updates the\nprint strings to be exactly the same as the fields' name in the\nstructure.\n\nSigned-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>\nSigned-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>\n---\n drivers/net/ethernet/intel/ice/ice_common.c | 40 ++++++++++-----------\n 1 file changed, 20 insertions(+), 20 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/ice/ice_common.c b/drivers/net/ethernet/intel/ice/ice_common.c\nindex e8397e5b6267..8b2c46615834 100644\n--- a/drivers/net/ethernet/intel/ice/ice_common.c\n+++ b/drivers/net/ethernet/intel/ice/ice_common.c\n@@ -1551,29 +1551,29 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,\n \t\tcase ICE_AQC_CAPS_VALID_FUNCTIONS:\n \t\t\tcaps->valid_functions = number;\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: valid functions = %d\\n\", prefix,\n+\t\t\t\t \"%s: valid_functions (bitmap) = %d\\n\", prefix,\n \t\t\t\t caps->valid_functions);\n \t\t\tbreak;\n \t\tcase ICE_AQC_CAPS_SRIOV:\n \t\t\tcaps->sr_iov_1_1 = (number == 1);\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: SR-IOV = %d\\n\", prefix,\n+\t\t\t\t \"%s: sr_iov_1_1 = %d\\n\", prefix,\n \t\t\t\t caps->sr_iov_1_1);\n \t\t\tbreak;\n \t\tcase ICE_AQC_CAPS_VF:\n \t\t\tif (dev_p) {\n \t\t\t\tdev_p->num_vfs_exposed = number;\n \t\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t\t \"%s: VFs exposed = %d\\n\", prefix,\n+\t\t\t\t\t \"%s: num_vfs_exposed = %d\\n\", prefix,\n \t\t\t\t\t dev_p->num_vfs_exposed);\n \t\t\t} else if (func_p) {\n \t\t\t\tfunc_p->num_allocd_vfs = number;\n \t\t\t\tfunc_p->vf_base_id = logical_id;\n \t\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t\t \"%s: VFs allocated = %d\\n\", prefix,\n+\t\t\t\t\t \"%s: num_allocd_vfs = %d\\n\", prefix,\n \t\t\t\t\t func_p->num_allocd_vfs);\n \t\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t\t \"%s: VF base_id = %d\\n\", prefix,\n+\t\t\t\t\t \"%s: vf_base_id = %d\\n\", prefix,\n \t\t\t\t\t func_p->vf_base_id);\n \t\t\t}\n \t\t\tbreak;\n@@ -1581,17 +1581,17 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,\n \t\t\tif (dev_p) {\n \t\t\t\tdev_p->num_vsi_allocd_to_host = number;\n \t\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t\t \"%s: num VSI alloc to host = %d\\n\",\n+\t\t\t\t\t \"%s: num_vsi_allocd_to_host = %d\\n\",\n \t\t\t\t\t prefix,\n \t\t\t\t\t dev_p->num_vsi_allocd_to_host);\n \t\t\t} else if (func_p) {\n \t\t\t\tfunc_p->guar_num_vsi =\n \t\t\t\t\tice_get_num_per_func(hw, ICE_MAX_VSI);\n \t\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t\t \"%s: num guaranteed VSI (fw) = %d\\n\",\n+\t\t\t\t\t \"%s: guar_num_vsi (fw) = %d\\n\",\n \t\t\t\t\t prefix, number);\n \t\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t\t \"%s: num guaranteed VSI = %d\\n\",\n+\t\t\t\t\t \"%s: guar_num_vsi = %d\\n\",\n \t\t\t\t\t prefix, func_p->guar_num_vsi);\n \t\t\t}\n \t\t\tbreak;\n@@ -1600,56 +1600,56 @@ ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,\n \t\t\tcaps->active_tc_bitmap = logical_id;\n \t\t\tcaps->maxtc = phys_id;\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: DCB = %d\\n\", prefix, caps->dcb);\n+\t\t\t\t \"%s: dcb = %d\\n\", prefix, caps->dcb);\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: active TC bitmap = %d\\n\", prefix,\n+\t\t\t\t \"%s: active_tc_bitmap = %d\\n\", prefix,\n \t\t\t\t caps->active_tc_bitmap);\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: TC max = %d\\n\", prefix, caps->maxtc);\n+\t\t\t\t \"%s: maxtc = %d\\n\", prefix, caps->maxtc);\n \t\t\tbreak;\n \t\tcase ICE_AQC_CAPS_RSS:\n \t\t\tcaps->rss_table_size = number;\n \t\t\tcaps->rss_table_entry_width = logical_id;\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: RSS table size = %d\\n\", prefix,\n+\t\t\t\t \"%s: rss_table_size = %d\\n\", prefix,\n \t\t\t\t caps->rss_table_size);\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: RSS table width = %d\\n\", prefix,\n+\t\t\t\t \"%s: rss_table_entry_width = %d\\n\", prefix,\n \t\t\t\t caps->rss_table_entry_width);\n \t\t\tbreak;\n \t\tcase ICE_AQC_CAPS_RXQS:\n \t\t\tcaps->num_rxq = number;\n \t\t\tcaps->rxq_first_id = phys_id;\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: num Rx queues = %d\\n\", prefix,\n+\t\t\t\t \"%s: num_rxq = %d\\n\", prefix,\n \t\t\t\t caps->num_rxq);\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: Rx first queue ID = %d\\n\", prefix,\n+\t\t\t\t \"%s: rxq_first_id = %d\\n\", prefix,\n \t\t\t\t caps->rxq_first_id);\n \t\t\tbreak;\n \t\tcase ICE_AQC_CAPS_TXQS:\n \t\t\tcaps->num_txq = number;\n \t\t\tcaps->txq_first_id = phys_id;\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: num Tx queues = %d\\n\", prefix,\n+\t\t\t\t \"%s: num_txq = %d\\n\", prefix,\n \t\t\t\t caps->num_txq);\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: Tx first queue ID = %d\\n\", prefix,\n+\t\t\t\t \"%s: txq_first_id = %d\\n\", prefix,\n \t\t\t\t caps->txq_first_id);\n \t\t\tbreak;\n \t\tcase ICE_AQC_CAPS_MSIX:\n \t\t\tcaps->num_msix_vectors = number;\n \t\t\tcaps->msix_vector_first_id = phys_id;\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: MSIX vector count = %d\\n\", prefix,\n+\t\t\t\t \"%s: num_msix_vectors = %d\\n\", prefix,\n \t\t\t\t caps->num_msix_vectors);\n \t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: MSIX first vector index = %d\\n\", prefix,\n+\t\t\t\t \"%s: msix_vector_first_id = %d\\n\", prefix,\n \t\t\t\t caps->msix_vector_first_id);\n \t\t\tbreak;\n \t\tcase ICE_AQC_CAPS_MAX_MTU:\n \t\t\tcaps->max_mtu = number;\n-\t\t\tice_debug(hw, ICE_DBG_INIT, \"%s: max MTU = %d\\n\",\n+\t\t\tice_debug(hw, ICE_DBG_INIT, \"%s: max_mtu = %d\\n\",\n \t\t\t\t prefix, caps->max_mtu);\n \t\t\tbreak;\n \t\tdefault:\n", "prefixes": [ "S28", "9/9" ] }