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GET /api/patches/1140228/?format=api
{ "id": 1140228, "url": "http://patchwork.ozlabs.org/api/patches/1140228/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-aspeed/patch/20190730060029.25268-1-Ben_Pai@wistron.com/", "project": { "id": 57, "url": "http://patchwork.ozlabs.org/api/projects/57/?format=api", "name": "Linux ASPEED SoC development", "link_name": "linux-aspeed", "list_id": "linux-aspeed.lists.ozlabs.org", "list_email": "linux-aspeed@lists.ozlabs.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190730060029.25268-1-Ben_Pai@wistron.com>", "list_archive_url": null, "date": "2019-07-30T06:00:29", "name": "ARM: dts: aspeed: Add Mihawk BMC platform", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "99c498ca22fefc121a99022492aa289a1f9c9f95", "submitter": { "id": 77077, "url": "http://patchwork.ozlabs.org/api/people/77077/?format=api", "name": "Ben Pai", "email": "Ben_Pai@wistron.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-aspeed/patch/20190730060029.25268-1-Ben_Pai@wistron.com/mbox/", "series": [ { "id": 122618, "url": "http://patchwork.ozlabs.org/api/series/122618/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-aspeed/list/?series=122618", "date": "2019-07-30T06:00:29", "name": "ARM: dts: aspeed: Add Mihawk BMC platform", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/122618/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1140228/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1140228/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-aspeed@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "linux-aspeed@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\tkey-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 45zZZZ5TWrz9sMr\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 1 Aug 2019 12:52:06 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 45zZZZ4ZTXzDqnV\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 1 Aug 2019 12:52:06 +1000 (AEST)", "from segapp03.wistron.com (segapp02.wistron.com [103.200.3.19])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 45yQyw6B90zDqTF\n\tfor <linux-aspeed@lists.ozlabs.org>;\n\tTue, 30 Jul 2019 16:05:44 +1000 (AEST)", "from EXCHAPP01.whq.wistron (unverified [10.37.38.24]) by \n\tTWNHUMSW4.wistron.com (Clearswift SMTPRS 5.6.0) with ESMTP id \n\t<Td94f978787c0a81672148c@TWNHUMSW4.wistron.com>; Tue, 30 Jul 2019 \n\t14:00:33 +0800", "from EXCHAPP01.whq.wistron (10.37.38.24) by EXCHAPP01.whq.wistron \n\t(10.37.38.24) with Microsoft SMTP Server \n\t(version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id \n\t15.1.1713.5; Tue, 30 Jul 2019 14:00:32 +0800", "from gitserver.wistron.com (10.37.38.233) by EXCHAPP01.whq.wistron\n\t(10.37.38.24) with Microsoft SMTP Server id 15.1.1713.5 via Frontend\n\tTransport; Tue, 30 Jul 2019 14:00:32 +0800" ], "Authentication-Results": [ "ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=wistron.com", "lists.ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=wistron.com\n\t(client-ip=103.200.3.19; helo=segapp03.wistron.com;\n\tenvelope-from=ben_pai@wistron.com; receiver=<UNKNOWN>)", "lists.ozlabs.org;\n\tdmarc=none (p=none dis=none) header.from=wistron.com" ], "X-Greylist": "delayed 302 seconds by postgrey-1.36 at bilbo;\n\tTue, 30 Jul 2019 16:05:44 AEST", "From": "Ben Pai <Ben_Pai@wistron.com>", "To": "<robh+dt@kernel.org>, <mark.rutland@arm.com>, <joel@jms.id.au>, \n\t<andrew@aj.id.au>, <devicetree@vger.kernel.org>, \n\t<linux-arm-kernel@lists.infradead.org>, \n\t<linux-aspeed@lists.ozlabs.org>, <linux-kernel@vger.kernel.org>", "Subject": "[PATCH] ARM: dts: aspeed: Add Mihawk BMC platform", "Date": "Tue, 30 Jul 2019 14:00:29 +0800", "Message-ID": "<20190730060029.25268-1-Ben_Pai@wistron.com>", "X-Mailer": "git-send-email 2.17.1", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"us-ascii\"", "X-TM-SNTS-SMTP": "B8F3A59F9A568685DBD873CF6FDF86BFBFE5BE878EEFCCE1F7C2FDDB36AE387C2000:8", "Content-Transfer-Encoding": "7bit", "X-Mailman-Approved-At": "Thu, 01 Aug 2019 12:52:00 +1000", "X-BeenThere": "linux-aspeed@lists.ozlabs.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Linux ASPEED SoC development <linux-aspeed.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linux-aspeed>,\n\t<mailto:linux-aspeed-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linux-aspeed/>", "List-Post": "<mailto:linux-aspeed@lists.ozlabs.org>", "List-Help": "<mailto:linux-aspeed-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linux-aspeed>,\n\t<mailto:linux-aspeed-request@lists.ozlabs.org?subject=subscribe>", "Cc": "Ben Pai <Ben_Pai@wistron.com>, wangat@tw.ibm.com", "Errors-To": "linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org", "Sender": "\"Linux-aspeed\"\n\t<linux-aspeed-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>" }, "content": "The Mihawk BMC is an ASPEED ast2500 based BMC that is part of an\nOpenPower Power9 server.\n\nThis adds the device tree description for most upstream components. It\nis a squashed commit from the OpenBMC kernel tree.\n\nSigned-off-by: Ben Pai <Ben_Pai@wistron.com>\n---\n arch/arm/boot/dts/Makefile | 1 +\n arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts | 922 ++++++++++++++++++++\n 2 files changed, 923 insertions(+)\n create mode 100755 arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts", "diff": "diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile\nindex eb6de52c1936..262345544359 100644\n--- a/arch/arm/boot/dts/Makefile\n+++ b/arch/arm/boot/dts/Makefile\n@@ -1281,5 +1281,6 @@ dtb-$(CONFIG_ARCH_ASPEED) += \\\n \taspeed-bmc-opp-vesnin.dtb \\\n \taspeed-bmc-opp-witherspoon.dtb \\\n \taspeed-bmc-opp-zaius.dtb \\\n+\taspeed-bmc-opp-mihawk.dtb \\\n \taspeed-bmc-portwell-neptune.dtb \\\n \taspeed-bmc-quanta-q71l.dtb\ndiff --git a/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts\nnew file mode 100755\nindex 000000000000..cfa20e0b2939\n--- /dev/null\n+++ b/arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts\n@@ -0,0 +1,922 @@\n+/dts-v1/;\n+\n+#include \"aspeed-g5.dtsi\"\n+#include <dt-bindings/gpio/aspeed-gpio.h>\n+#include <dt-bindings/leds/leds-pca955x.h>\n+\n+/ {\n+\tmodel = \"Mihawk BMC\";\n+\tcompatible = \"ibm,mihawk-bmc\", \"aspeed,ast2500\";\n+\n+\n+\tchosen {\n+\t\tstdout-path = &uart5;\n+\t\tbootargs = \"console=ttyS4,115200 earlyprintk\";\n+\t};\n+\n+\tmemory@80000000 {\n+\t\treg = <0x80000000 0x20000000>; /* address and size of RAM(512MB) */\n+\t};\n+\n+\treserved-memory {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tranges;\n+\n+\t\tflash_memory: region@98000000 {\n+\t\t\tno-map;\n+\t\t\treg = <0x98000000 0x04000000>; /* 64M */\n+\t\t};\n+\n+\t\tgfx_memory: framebuffer {\n+\t\t\tsize = <0x01000000>;\n+\t\t\talignment = <0x01000000>;\n+\t\t\tcompatible = \"shared-dma-pool\";\n+\t\t\treusable;\n+\t\t};\n+\n+\t\tvideo_engine_memory: jpegbuffer {\n+\t\t\tsize = <0x02000000>;\t/* 32MM */\n+\t\t\talignment = <0x01000000>;\n+\t\t\tcompatible = \"shared-dma-pool\";\n+\t\t\treusable;\n+\t\t};\n+\t};\n+\n+\tgpio-keys {\n+\t\tcompatible = \"gpio-keys\";\n+\n+\t\tair-water {\n+\t\t\tlabel = \"air-water\";\n+\t\t\tgpios = <&gpio ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <ASPEED_GPIO(F, 6)>;\n+\t\t};\n+\n+\t\tcheckstop {\n+\t\t\tlabel = \"checkstop\";\n+\t\t\tgpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <ASPEED_GPIO(J, 2)>;\n+\t\t};\n+\n+\t\tps0-presence {\n+\t\t\tlabel = \"ps0-presence\";\n+\t\t\tgpios = <&gpio ASPEED_GPIO(Z, 2) GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <ASPEED_GPIO(Z, 2)>;\n+\t\t};\n+\n+\t\tps1-presence {\n+\t\t\tlabel = \"ps1-presence\";\n+\t\t\tgpios = <&gpio ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <ASPEED_GPIO(Z, 0)>;\n+\t\t};\n+\t\tid-button {\n+\t\t\tlabel = \"id-button\";\n+\t\t\tgpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <ASPEED_GPIO(F, 1)>;\n+\t\t};\n+\t};\n+\n+\tgpio-keys-polled {\n+\t\tcompatible = \"gpio-keys-polled\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tpoll-interval = <1000>;\n+\n+\t\tfan0-presence {\n+\t\t\tlabel = \"fan0-presence\";\n+\t\t\tgpios = <&pca9552 9 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <9>;\n+\t\t};\n+\n+\t\tfan1-presence {\n+\t\t\tlabel = \"fan1-presence\";\n+\t\t\tgpios = <&pca9552 10 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <10>;\n+\t\t};\n+\n+\t\tfan2-presence {\n+\t\t\tlabel = \"fan2-presence\";\n+\t\t\tgpios = <&pca9552 11 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <11>;\n+\t\t};\n+\n+\t\tfan3-presence {\n+\t\t\tlabel = \"fan3-presence\";\n+\t\t\tgpios = <&pca9552 12 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <12>;\n+\t\t};\n+\n+\t\tfan4-presence {\n+\t\t\tlabel = \"fan4-presence\";\n+\t\t\tgpios = <&pca9552 13 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <13>;\n+\t\t};\n+\n+\t\tfan5-presence {\n+\t\t\tlabel = \"fan5-presence\";\n+\t\t\tgpios = <&pca9552 14 GPIO_ACTIVE_LOW>;\n+\t\t\tlinux,code = <14>;\n+\t\t};\n+\t};\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+\n+\t\tfault {\n+\t\t\tretain-state-shutdown;\n+\t\t\tdefault-state = \"keep\";\n+\t\t\tgpios = <&gpio ASPEED_GPIO(AA, 0) GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tpower {\n+\t\t\tretain-state-shutdown;\n+\t\t\tdefault-state = \"keep\";\n+\t\t\tgpios = <&gpio ASPEED_GPIO(AA, 1) GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\trear-id {\n+\t\t\tretain-state-shutdown;\n+\t\t\tdefault-state = \"keep\";\n+\t\t\tgpios = <&gpio ASPEED_GPIO(AA, 2) GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\trear-g {\n+\t\t\tretain-state-shutdown;\n+\t\t\tdefault-state = \"keep\";\n+\t\t\tgpios = <&gpio ASPEED_GPIO(AA, 4) GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\trear-ok {\n+\t\t\tretain-state-shutdown;\n+\t\t\tdefault-state = \"keep\";\n+\t\t\tgpios = <&gpio ASPEED_GPIO(Y, 0) GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tfan0 {\n+\t\t\tretain-state-shutdown;\n+\t\t\tdefault-state = \"keep\";\n+\t\t\tgpios = <&pca9552 0 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tfan1 {\n+\t\t\tretain-state-shutdown;\n+\t\t\tdefault-state = \"keep\";\n+\t\t\tgpios = <&pca9552 1 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tfan2 {\n+\t\t\tretain-state-shutdown;\n+\t\t\tdefault-state = \"keep\";\n+\t\t\tgpios = <&pca9552 2 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tfan3 {\n+\t\t\tretain-state-shutdown;\n+\t\t\tdefault-state = \"keep\";\n+\t\t\tgpios = <&pca9552 3 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tfan4 {\n+\t\t\tretain-state-shutdown;\n+\t\t\tdefault-state = \"keep\";\n+\t\t\tgpios = <&pca9552 4 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tfan5 {\n+\t\t\tretain-state-shutdown;\n+\t\t\tdefault-state = \"keep\";\n+\t\t\tgpios = <&pca9552 5 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\t};\n+\n+\tfsi: gpio-fsi {\n+\t\tcompatible = \"fsi-master-gpio\", \"fsi-master\";\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <0>;\n+\t\tno-gpio-delays;\n+\n+\t\tclock-gpios = <&gpio ASPEED_GPIO(E, 6) GPIO_ACTIVE_HIGH>;\n+\t\tdata-gpios = <&gpio ASPEED_GPIO(E, 7) GPIO_ACTIVE_HIGH>;\n+\t\tmux-gpios = <&gpio ASPEED_GPIO(E, 5) GPIO_ACTIVE_HIGH>;\n+\t\tenable-gpios = <&gpio ASPEED_GPIO(D, 0) GPIO_ACTIVE_HIGH>;\n+\t\ttrans-gpios = <&gpio ASPEED_GPIO(R, 2) GPIO_ACTIVE_HIGH>;\n+\t};\n+\tiio-hwmon-12v {\n+\t\tcompatible = \"iio-hwmon\";\n+\t\tio-channels = <&adc 0>;\n+\t};\n+\t\n+\tiio-hwmon-5v {\n+\t\tcompatible = \"iio-hwmon\";\n+\t\tio-channels = <&adc 1>;\n+\t};\n+\t\n+\tiio-hwmon-3v {\n+\t\tcompatible = \"iio-hwmon\";\n+\t\tio-channels = <&adc 2>;\n+\t};\n+\t\t\n+\tiio-hwmon-vdd0 {\n+\t\tcompatible = \"iio-hwmon\";\n+\t\tio-channels = <&adc 3>;\n+\t};\n+\t\n+\tiio-hwmon-vdd1 {\n+\t\tcompatible = \"iio-hwmon\";\n+\t\tio-channels = <&adc 4>;\n+\t};\n+\t\n+\tiio-hwmon-vcs0 {\n+\t\tcompatible = \"iio-hwmon\";\n+\t\tio-channels = <&adc 5>;\n+\t};\n+\t\n+\tiio-hwmon-vcs1 {\n+\t\tcompatible = \"iio-hwmon\";\n+\t\tio-channels = <&adc 6>;\n+\t};\n+\n+\tiio-hwmon-vdn0 {\n+\t\tcompatible = \"iio-hwmon\";\n+\t\tio-channels = <&adc 7>;\n+\t};\n+\t\n+\tiio-hwmon-vdn1 {\n+\t\tcompatible = \"iio-hwmon\";\n+\t\tio-channels = <&adc 8>;\n+\t};\n+\t\n+\tiio-hwmon-vio0 {\n+\t\tcompatible = \"iio-hwmon\";\n+\t\tio-channels = <&adc 9>;\n+\t};\n+\t\n+\tiio-hwmon-vio1 {\n+\t\tcompatible = \"iio-hwmon\";\n+\t\tio-channels = <&adc 10>;\n+\t};\n+\t\n+\tiio-hwmon-vddra {\n+\t\tcompatible = \"iio-hwmon\";\n+\t\tio-channels = <&adc 11>;\n+\t};\n+\t\n+\tiio-hwmon-vddrb {\n+\t\tcompatible = \"iio-hwmon\";\n+\t\tio-channels = <&adc 13>;\n+\t};\n+\t\n+\tiio-hwmon-vddrc {\n+\t\tcompatible = \"iio-hwmon\";\n+\t\tio-channels = <&adc 14>;\n+\t};\n+\t\n+\tiio-hwmon-vddrd {\n+\t\tcompatible = \"iio-hwmon\";\n+\t\tio-channels = <&adc 15>;\n+\t};\n+\t\n+\tiio-hwmon-battery {\n+\t\tcompatible = \"iio-hwmon\";\n+\t\tio-channels = <&adc 12>;\n+\t};\n+};\n+\n+&pwm_tacho {\n+\tstatus = \"okay\";\n+\t/*compatible = \"aspeed,ast2500-pwm-tacho\";\n+\t#address-cells = <1>;\n+\t#size-cells = <1>;\n+\treg = <0x1e786000 0x1000>;\n+\tclocks = <&pwm_tacho_fixed_clk>;*/\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default\n+\t\t&pinctrl_pwm2_default &pinctrl_pwm3_default\n+\t\t&pinctrl_pwm4_default &pinctrl_pwm5_default>;\n+\n+\tfan@0 {\n+\t\treg = <0x00>;\n+\t\taspeed,fan-tach-ch = /bits/ 8 <0x00>;\n+\t};\n+\n+\tfan@1 {\n+\t\treg = <0x01>;\n+\t\taspeed,fan-tach-ch = /bits/ 8 <0x01>;\n+\t};\n+\n+\tfan@2 {\n+\t\treg = <0x02>;\n+\t\taspeed,fan-tach-ch = /bits/ 8 <0x02>;\n+\t};\n+\n+\tfan@3 {\n+\t\treg = <0x03>;\n+\t\taspeed,fan-tach-ch = /bits/ 8 <0x03>;\n+\t};\n+\n+\tfan@4 {\n+\t\treg = <0x04>;\n+\t\taspeed,fan-tach-ch = /bits/ 8 <0x04>;\n+\t};\n+\n+\tfan@5 {\n+\t\treg = <0x05>;\n+\t\taspeed,fan-tach-ch = /bits/ 8 <0x05>;\n+\t};\n+\n+\tfan@6 {\n+\t\treg = <0x00>;\n+\t\taspeed,fan-tach-ch = /bits/ 8 <0x06>;\n+\t};\n+\n+\tfan@7 {\n+\t\treg = <0x01>;\n+\t\taspeed,fan-tach-ch = /bits/ 8 <0x07>;\n+\t};\n+\n+\tfan@8 {\n+\t\treg = <0x02>;\n+\t\taspeed,fan-tach-ch = /bits/ 8 <0x08>;\n+\t};\n+\n+\tfan@9 {\n+\t\treg = <0x03>;\n+\t\taspeed,fan-tach-ch = /bits/ 8 <0x09>;\n+\t};\n+\n+\tfan@10 {\n+\t\treg = <0x04>;\n+\t\taspeed,fan-tach-ch = /bits/ 8 <0x0a>;\n+\t};\n+\n+\tfan@11 {\n+\t\treg = <0x05>;\n+\t\taspeed,fan-tach-ch = /bits/ 8 <0x0b>;\n+\t};\n+};\n+\n+&fmc {\n+\tstatus = \"okay\";\n+\tflash@0 {\n+\t\tstatus = \"okay\";\n+\t\tlabel = \"bmc\";\n+\t\tm25p,fast-read;\n+\t\tspi-max-frequency = <50000000>;\n+\t\tpartitions {\n+\t\t\t#address-cells = < 1 >;\n+\t\t\t#size-cells = < 1 >;\n+\t\t\tcompatible = \"fixed-partitions\";\n+\t\t\tu-boot@0 {\n+\t\t\t\treg = < 0 0x60000 >;\n+\t\t\t\tlabel = \"u-boot\";\n+\t\t\t};\n+\t\t\tu-boot-env@60000 {\n+\t\t\t\treg = < 0x60000 0x20000 >;\n+\t\t\t\tlabel = \"u-boot-env\";\n+\t\t\t};\n+\t\t\tobmc-ubi@80000 {\n+\t\t\t\treg = < 0x80000 0x1F80000 >;\n+\t\t\t\tlabel = \"obmc-ubi\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\tflash@1 {\n+\t\tstatus = \"okay\";\n+\t\tlabel = \"alt-bmc\";\n+\t\tm25p,fast-read;\n+\t\tspi-max-frequency = <50000000>;\n+\t\tpartitions {\n+\t\t\t#address-cells = < 1 >;\n+\t\t\t#size-cells = < 1 >;\n+\t\t\tcompatible = \"fixed-partitions\";\n+\t\t\tu-boot@0 {\n+\t\t\t\treg = < 0 0x60000 >;\n+\t\t\t\tlabel = \"alt-u-boot\";\n+\t\t\t};\n+\t\t\tu-boot-env@60000 {\n+\t\t\t\treg = < 0x60000 0x20000 >;\n+\t\t\t\tlabel = \"alt-u-boot-env\";\n+\t\t\t};\n+\t\t\tobmc-ubi@80000 {\n+\t\t\t\treg = < 0x80000 0x1F80000 >;\n+\t\t\t\tlabel = \"alt-obmc-ubi\";\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&spi1 {\n+\tstatus = \"okay\";\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_spi1_default>;\n+\n+\tflash@0 {\n+\t\tstatus = \"okay\";\n+\t\tlabel = \"pnor\";\n+\t\tm25p,fast-read;\n+\t\tspi-max-frequency = <100000000>;\n+\t};\n+};\n+\n+&lpc_ctrl {\n+\tstatus = \"okay\";\n+\tmemory-region = <&flash_memory>;\n+\tflash = <&spi1>;\n+};\n+\n+&uart1 {\n+\t/* Rear RS-232 connector */\n+\tstatus = \"okay\";\n+\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_txd1_default\n+\t\t\t&pinctrl_rxd1_default\n+\t\t\t&pinctrl_nrts1_default\n+\t\t\t&pinctrl_ndtr1_default\n+\t\t\t&pinctrl_ndsr1_default\n+\t\t\t&pinctrl_ncts1_default\n+\t\t\t&pinctrl_ndcd1_default\n+\t\t\t&pinctrl_nri1_default>;\n+};\n+\n+&uart2 {\n+\t/* APSS */\n+\tstatus = \"okay\";\n+\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>;\n+};\n+\n+&uart5 {\n+\tstatus = \"okay\";\n+};\n+\n+&mac0 {\n+\tstatus = \"okay\";\n+\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_rmii1_default>;\n+\tuse-ncsi;\n+};\n+\n+&mac1 {\n+\tstatus = \"okay\";\n+\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_rgmii2_default &pinctrl_mdio2_default>;\n+};\n+\n+&i2c0 {\n+\tstatus = \"disabled\";\n+};\n+\n+&i2c1 {\n+\tstatus = \"disabled\";\n+};\n+\n+&i2c2 {\n+\tstatus = \"okay\";\n+\n+\t/* SAMTEC P0 */\n+\t/* SAMTEC P1 */\n+\t\n+};\n+\n+&i2c3 {\n+\tstatus = \"okay\";\n+\n+\t/* APSS */\n+\t/* CPLD */\n+\n+\t/* PCA9516 (repeater) ->\n+\t * CLK Buffer 9FGS9092\n+\t * CLK Buffer 9DBL0651BKILFT\n+\t * CLK Buffer 9DBL0651BKILFT\n+\t * Power Supply 0\n+\t * Power Supply 1\n+\t * PCA 9552 LED\n+\t */\n+\t \n+\tpower-supply@58 {\n+\t\tcompatible = \"ibm,cffps1\";\n+\t\treg = <0x58>;\n+\t};\n+\n+\tpower-supply@5b {\n+\t\tcompatible = \"ibm,cffps1\";\n+\t\treg = <0x5b>;\n+\t};\n+\n+\tpca9552: pca9552@60 {\n+\t\tcompatible = \"nxp,pca9552\";\n+\t\treg = <0x60>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\tgpio-controller;\n+\t\t#gpio-cells = <2>;\n+\n+\t\tgpio@0 {\n+\t\t\treg = <0>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\t\tgpio@1 {\n+\t\t\treg = <1>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\t\tgpio@2 {\n+\t\t\treg = <2>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\t\tgpio@3 {\n+\t\t\treg = <3>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\t\tgpio@4 {\n+\t\t\treg = <4>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\t\tgpio@5 {\n+\t\t\treg = <5>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\t\tgpio@6 {\n+\t\t\treg = <6>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\t\tgpio@7 {\n+\t\t\treg = <7>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\t\tgpio@8 {\n+\t\t\treg = <8>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\t\tgpio@9 {\n+\t\t\treg = <9>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\t\tgpio@10 {\n+\t\t\treg = <10>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\t\tgpio@11 {\n+\t\t\treg = <11>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\t\tgpio@12 {\n+\t\t\treg = <12>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\t\tgpio@13 {\n+\t\t\treg = <13>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\t\tgpio@14 {\n+\t\t\treg = <14>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\t\tgpio@15 {\n+\t\t\treg = <15>;\n+\t\t\ttype = <PCA955X_TYPE_GPIO>;\n+\t\t};\n+\n+\t};\n+\n+};\n+\n+&i2c4 {\n+\tstatus = \"okay\";\n+\n+\t/* CP0 VDD & VCS : IR35221 */\n+\t/* CP0 VDN : IR35221 */\n+\t/* CP0 VIO : IR38064 */\n+ /* CP0 VDDR : PXM1330 */\n+\n+\tir35221@70 {\n+\t\tcompatible = \"infineon,ir35221\";\n+\t\treg = <0x70>;\n+\t};\n+\n+\tir35221@72 {\n+\t\tcompatible = \"infineon,ir35221\";\n+\t\treg = <0x72>;\n+\t};\n+\n+};\n+\n+&i2c5 {\n+\tstatus = \"okay\";\n+\t\n+\t/* CP0 VDD & VCS : IR35221 */\n+\t/* CP0 VDN : IR35221 */\n+\t/* CP0 VIO : IR38064 */\n+ /* CP0 VDDR : PXM1330 */\n+\n+\tir35221@70 {\n+\t\tcompatible = \"infineon,ir35221\";\n+\t\treg = <0x70>;\n+\t};\n+\n+\tir35221@72 {\n+\t\tcompatible = \"infineon,ir35221\";\n+\t\treg = <0x72>;\n+\t};\n+\t\n+};\n+\n+&i2c6 {\n+\tstatus = \"okay\";\n+\t\n+\t/* pca9548 -> NVMe1 to 8 */\n+\t\n+\tpca9548@70 {\n+\t\tcompatible = \"nxp,pca9548\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x70>;\n+\t};\n+\t\n+};\n+\n+&i2c7 {\n+\tstatus = \"okay\";\n+\t\n+\t/* pca9548 -> NVMe9 to 16 */\n+\t\n+\tpca9548@70 {\n+\t\tcompatible = \"nxp,pca9548\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x70>;\n+\t};\n+\t\n+};\n+\n+&i2c8 {\n+\tstatus = \"okay\";\n+\n+\t/* FSI CLK/DAT */\n+\teeprom@50 {\n+\t\tcompatible = \"atmel,24c64\";\n+\t\treg = <0x50>;\n+\t};\n+};\n+\n+&i2c9 {\n+\tstatus = \"okay\";\n+\t\n+\t/* pca9545 Riser -> \n+\t* \tPCIe x8 Slot3 \n+\t* \tPCIe x16 slot4 \n+\t* \tPCIe x8 slot5 \n+\t* \tI2C BMC RISER PCA9554\n+\t* \tBMC SCL/SDA PCA9554 \n+\t* \tPCA9554\n+\t*/\n+\t\n+\t/* pca9545 -> \n+\t* \tPCIe x16 Slot1 \n+\t* \tPCIe x8 slot2 \n+\t* \tPEX8748 \n+\t*/\n+\n+\tpca9545riser@70 {\n+\t\tcompatible = \"nxp,pca9545\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x70>;\n+\n+\t\t/*interrupt-parent = <&ipic>;*/\n+\t\t/*interrupts = <17 IRQ_TYPE_LEVEL_LOW>;*/\n+\t\ti2c-mux-idle-disconnect;\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <2>;\n+\t};\n+\t\n+\tpca9545@71 {\n+\t\tcompatible = \"nxp,pca9545\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x71>;\n+\n+\t\t/*interrupt-parent = <&ipic>;*/\n+\t\t/*interrupts = <17 IRQ_TYPE_LEVEL_LOW>;*/\n+\t\ti2c-mux-idle-disconnect;\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <2>;\t\n+\t};\n+};\n+\n+&i2c10 {\n+\tstatus = \"okay\";\n+\t\n+\t/* pca9545 Riser -> \n+\t* \tPCIe x8 Slot8 \n+\t* \tPCIe x16 slot9 \n+\t* \tPCIe x8 slot10 \n+\t* \tI2C BMC RISER PCA9554\n+\t* \tBMC SCL/SDA PCA9554 \n+\t* \tPCA9554\n+\t*/\n+\t\n+\t/* pca9545 -> \n+\t* \tPCIe x16 Slot1 \n+\t* \tPCIe x8 slot2 \n+\t* \tPEX8748 \n+\t*/\n+\t\n+\tpca9545riser@70 {\n+\t\tcompatible = \"nxp,pca9545\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x70>;\n+\n+\t\t/*interrupt-parent = <&ipic>;*/\n+\t\t/*interrupts = <17 IRQ_TYPE_LEVEL_LOW>;*/\n+\t\ti2c-mux-idle-disconnect;\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <2>;\n+\t};\n+\t\n+\tpca9545@71 {\n+\t\tcompatible = \"nxp,pca9545\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x71>;\n+\n+\t\t/*interrupt-parent = <&ipic>;*/\n+\t\t/*interrupts = <17 IRQ_TYPE_LEVEL_LOW>;*/\n+\t\ti2c-mux-idle-disconnect;\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <2>;\t\n+\t};\n+};\n+\n+&i2c11 {\n+\tstatus = \"okay\";\n+\t\n+\t/* TPM */\n+\t/* RTC RX8900CE */\n+\t/* FPGA for power sequence */\n+\t/* TMP275A */\n+\t/* TMP275A */\n+\t/* EMC1462 */\n+\n+\ttpm@57 {\n+\t\tcompatible = \"infineon,slb9645tt\";\n+\t\treg = <0x57>;\n+\t};\n+\t\n+\trtc@32 {\n+\t\tcompatible = \"epson,rx8900\";\n+\t\treg = <0x32>;\n+\t};\n+\t\n+\ttmp275@48 {\n+\t\tcompatible = \"ti,tmp275\";\n+\t\treg = <0x48>;\n+\t};\n+\t\n+\ttmp275@49 {\n+\t\tcompatible = \"ti,tmp275\";\n+\t\treg = <0x49>;\n+\t};\n+\n+ /* chip emc1462 use emc1403 driver */\n+ emc1403@4c {\n+ compatible = \"smsc,emc1403\";\n+ reg = <0x4c>;\n+ };\n+\n+};\n+\n+&i2c12 {\n+\tstatus = \"okay\";\n+\n+\t/* pca9545 ->\n+\t*\tSAS BP1\n+\t*\tSAS BP2\n+\t*\tNVMe BP\n+\t*\tM.2 riser\n+\t*/\n+\t\n+\tpca9545@70 {\n+\t\tcompatible = \"nxp,pca9545\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x70>;\n+\n+\t\t/*interrupt-parent = <&ipic>;*/\n+\t\t/*interrupts = <17 IRQ_TYPE_LEVEL_LOW>;*/\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <2>;\n+\t\t\n+\t\ti2c@0 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <0>;\n+\t\t\t\n+\t\t\teeprom@50 {\n+\t\t\t\tcompatible = \"atmel,24c64\";\n+\t\t\t\treg = <0x50>;\n+\t\t\t};\n+\t\t};\n+\t\t\n+\t\ti2c@1 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <1>;\n+\t\t\t\n+\t\t\teeprom@50 {\n+\t\t\t\tcompatible = \"atmel,24c64\";\n+\t\t\t\treg = <0x50>;\n+\t\t\t};\n+\t\t};\n+\t\t\n+\t\ti2c@2 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <2>;\n+\t\t\t\n+\t\t\teeprom@50 {\n+\t\t\t\tcompatible = \"atmel,24c64\";\n+\t\t\t\treg = <0x50>;\n+\t\t\t};\n+\t\t};\n+\t\t\n+\t\ti2c@3 {\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\treg = <3>;\n+\t\t\t\n+\t\t\ttmp275@48 {\n+\t\t\t\tcompatible = \"ti,tmp275\";\n+\t\t\t\treg = <0x48>;\n+\t\t\t};\n+\t\t};\n+\t\t\n+\t};\n+\t\n+};\n+\n+&i2c13 {\n+\tstatus = \"okay\";\n+\t\n+\t/* pca9548 ->\n+\t*\tNVMe BP\n+\t*\tNVMe HDD17 to 24\n+\t*/\n+\t\n+\tpca9548@70 {\n+\t\tcompatible = \"nxp,pca9548\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\treg = <0x70>;\n+\t};\t\n+};\n+\n+&vuart {\n+\tstatus = \"okay\";\n+};\n+\n+&gfx {\n+\tstatus = \"okay\";\n+\tmemory-region = <&gfx_memory>;\n+};\n+\n+&pinctrl {\n+\taspeed,external-nodes = <&gfx &lhc>;\n+};\n+\n+&adc {\n+\tstatus = \"okay\";\n+};\n+\n+&wdt1 {\n+\taspeed,reset-type = \"none\";\n+\taspeed,external-signal;\n+\taspeed,ext-push-pull;\n+\taspeed,ext-active-high;\n+\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_wdtrst1_default>;\n+};\n+\n+&wdt2 {\n+\taspeed,alt-boot;\n+};\n+\n+&ibt {\n+\tstatus = \"okay\";\n+};\n+\n+&vhub {\n+\tstatus = \"okay\";\n+};\n+\n+&video {\n+\tstatus = \"okay\";\n+\tmemory-region = <&video_engine_memory>;\n+};\n+\n+#include \"ibm-power9-dual.dtsi\"\n\\ No newline at end of file\n", "prefixes": [] }