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GET /api/patches/1139006/?format=api
{ "id": 1139006, "url": "http://patchwork.ozlabs.org/api/patches/1139006/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190730142959.8467-4-laurentiu.tudor@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190730142959.8467-4-laurentiu.tudor@nxp.com>", "list_archive_url": null, "date": "2019-07-30T14:29:58", "name": "[U-Boot,4/5] armv8: ls1088a: add icid setup for platform devices", "commit_ref": "5c6dc6c9a9a5f253f3928a97ca020712177884e7", "pull_url": null, "state": "accepted", "archived": false, "hash": "2067cc91b5016ffdf5edf6cc25bafef480fc2fe3", "submitter": { "id": 71003, "url": "http://patchwork.ozlabs.org/api/people/71003/?format=api", "name": "Laurentiu Tudor", "email": "laurentiu.tudor@nxp.com" }, "delegate": { "id": 2467, "url": "http://patchwork.ozlabs.org/api/users/2467/?format=api", "username": "prabhu_kush", "first_name": "Prabhakar", "last_name": "Kushwaha", "email": "prabhakar@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190730142959.8467-4-laurentiu.tudor@nxp.com/mbox/", "series": [ { "id": 122243, "url": "http://patchwork.ozlabs.org/api/series/122243/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=122243", "date": "2019-07-30T14:29:55", "name": "[U-Boot,1/5] armv8: fsl-layerscape: add missing sec jr base address defines", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/122243/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1139006/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1139006/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=nxp.com" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 45yfBh07b8z9sBF\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 31 Jul 2019 00:31:39 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 0A643C21ECF; Tue, 30 Jul 2019 14:30:28 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 929C6C21E6A;\n\tTue, 30 Jul 2019 14:30:07 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 730C0C21DF9; Tue, 30 Jul 2019 14:30:05 +0000 (UTC)", "from inva021.nxp.com (inva021.nxp.com [92.121.34.21])\n\tby lists.denx.de (Postfix) with ESMTPS id 37F47C21DEC\n\tfor <u-boot@lists.denx.de>; Tue, 30 Jul 2019 14:30:05 +0000 (UTC)", "from inva021.nxp.com (localhost [127.0.0.1])\n\tby inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 0B24F20070A;\n\tTue, 30 Jul 2019 16:30:05 +0200 (CEST)", "from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com\n\t[134.27.226.22])\n\tby inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id F2C28200701;\n\tTue, 30 Jul 2019 16:30:04 +0200 (CEST)", "from fsr-ub1864-101.ea.freescale.net\n\t(fsr-ub1864-101.ea.freescale.net [10.171.82.13])\n\tby inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 9C4AE204D6;\n\tTue, 30 Jul 2019 16:30:04 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0", "From": "laurentiu.tudor@nxp.com", "To": "u-boot@lists.denx.de,\n\tprabhakar.kushwaha@nxp.com", "Date": "Tue, 30 Jul 2019 17:29:58 +0300", "Message-Id": "<20190730142959.8467-4-laurentiu.tudor@nxp.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190730142959.8467-1-laurentiu.tudor@nxp.com>", "References": "<20190730142959.8467-1-laurentiu.tudor@nxp.com>", "X-Virus-Scanned": "ClamAV using ClamSMTP", "Subject": "[U-Boot] [PATCH 4/5] armv8: ls1088a: add icid setup for platform\n\tdevices", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Laurentiu Tudor <laurentiu.tudor@nxp.com>\n\nAdd ICID setup for the platform devices contained on this chip: usb,\nsata, sdhc, sec. The ICID macros for SEC needed to be adapted because\nthe format of the registers is different.\n\nSigned-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>\n---\n arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 +\n .../arm/cpu/armv8/fsl-layerscape/ls1088_ids.c | 30 +++++++++++\n arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 ++\n .../asm/arch-fsl-layerscape/fsl_icid.h | 54 +++++++++++++++----\n .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 6 +++\n board/freescale/ls1088a/ls1088a.c | 4 ++\n 6 files changed, 89 insertions(+), 10 deletions(-)\n create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c", "diff": "diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile\nindex a8d3cf91fc..aa88b93175 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile\n@@ -47,6 +47,7 @@ endif\n \n ifneq ($(CONFIG_ARCH_LS1088A),)\n obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o\n+obj-y += icid.o ls1088_ids.o\n endif\n \n ifneq ($(CONFIG_ARCH_LS1028A),)\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c\nnew file mode 100644\nindex 0000000000..956d6e78c8\n--- /dev/null\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c\n@@ -0,0 +1,30 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright 2019 NXP\n+ */\n+\n+#include <common.h>\n+#include <asm/arch-fsl-layerscape/immap_lsch3.h>\n+#include <asm/arch-fsl-layerscape/fsl_icid.h>\n+#include <asm/arch-fsl-layerscape/fsl_portals.h>\n+\n+struct icid_id_table icid_tbl[] = {\n+\tSET_SDHC_ICID(FSL_SDMMC_STREAM_ID),\n+\tSET_USB_ICID(1, \"snps,dwc3\", FSL_USB1_STREAM_ID),\n+\tSET_USB_ICID(2, \"snps,dwc3\", FSL_USB2_STREAM_ID),\n+\tSET_SATA_ICID(1, \"fsl,ls1088a-ahci\", FSL_SATA1_STREAM_ID),\n+\tSET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),\n+\tSET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),\n+\tSET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),\n+\tSET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),\n+\tSET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),\n+\tSET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),\n+\tSET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),\n+\tSET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),\n+\tSET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),\n+\tSET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),\n+\tSET_SEC_DECO_ICID_ENTRY(2, FSL_SEC_STREAM_ID),\n+\tSET_SEC_DECO_ICID_ENTRY(3, FSL_SEC_STREAM_ID),\n+};\n+\n+int icid_tbl_sz = ARRAY_SIZE(icid_tbl);\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\nindex 7414215208..467c34649f 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n@@ -339,6 +339,10 @@ void fsl_lsch3_early_init_f(void)\n \tif (fsl_check_boot_mode_secure() == 1)\n \t\tbypass_smmu();\n #endif\n+\n+#ifdef CONFIG_ARCH_LS1088A\n+\tset_icids();\n+#endif\n }\n \n /* Get VDD in the unit mV from voltage ID */\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h\nindex 435ffb04fa..feb3304364 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h\n@@ -40,6 +40,14 @@ void fdt_fixup_icid(void *blob);\n \t .le = _le \\\n \t}\n \n+#ifdef CONFIG_SYS_FSL_SEC_LE\n+#define SEC_IS_LE true\n+#elif defined(CONFIG_SYS_FSL_SEC_BE)\n+#define SEC_IS_LE false\n+#endif\n+\n+#ifdef CONFIG_FSL_LSCH2\n+\n #ifdef CONFIG_SYS_FSL_CCSR_SCFG_LE\n #define SCFG_IS_LE true\n #elif defined(CONFIG_SYS_FSL_CCSR_SCFG_BE)\n@@ -100,11 +108,7 @@ void fdt_fixup_icid(void *blob);\n #define SET_FMAN_ICID_ENTRY(_port_id, streamid) \\\n \t{ .port_id = (_port_id), .icid = (streamid) }\n \n-#ifdef CONFIG_SYS_FSL_SEC_LE\n-#define SEC_IS_LE true\n-#elif defined(CONFIG_SYS_FSL_SEC_BE)\n-#define SEC_IS_LE false\n-#endif\n+#define SEC_ICID_REG_VAL(streamid) (((streamid) << 16) | (streamid))\n \n #define SET_SEC_QI_ICID(streamid) \\\n \tSET_ICID_ENTRY(\"fsl,sec-v4.0\", streamid, \\\n@@ -112,6 +116,38 @@ void fdt_fixup_icid(void *blob);\n \t\tCONFIG_SYS_FSL_SEC_ADDR, \\\n \t\tCONFIG_SYS_FSL_SEC_ADDR, SEC_IS_LE)\n \n+extern struct fman_icid_id_table fman_icid_tbl[];\n+extern int fman_icid_tbl_sz;\n+\n+#else /* CONFIG_FSL_LSCH2 */\n+\n+#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE\n+#define GUR_IS_LE true\n+#elif defined(CONFIG_SYS_FSL_CCSR_GUR_BE)\n+#define GUR_IS_LE false\n+#endif\n+\n+#define SET_GUR_ICID(compat, streamid, name, compataddr) \\\n+\tSET_ICID_ENTRY(compat, streamid, streamid, \\\n+\t\toffsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \\\n+\t\tcompataddr, GUR_IS_LE)\n+\n+#define SET_USB_ICID(usb_num, compat, streamid) \\\n+\tSET_GUR_ICID(compat, streamid, usb##usb_num##_amqr,\\\n+\t\tCONFIG_SYS_XHCI_USB##usb_num##_ADDR)\n+\n+#define SET_SATA_ICID(sata_num, compat, streamid) \\\n+\tSET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \\\n+\t\tAHCI_BASE_ADDR##sata_num)\n+\n+#define SET_SDHC_ICID(streamid) \\\n+\tSET_GUR_ICID(\"fsl,esdhc\", streamid, sdmm1_amqr,\\\n+\t\tCONFIG_SYS_FSL_ESDHC_ADDR)\n+\n+#define SEC_ICID_REG_VAL(streamid) (streamid)\n+\n+#endif /* CONFIG_FSL_LSCH2 */\n+\n #define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \\\n \tSET_ICID_ENTRY( \\\n \t\t(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \\\n@@ -120,24 +156,22 @@ void fdt_fixup_icid(void *blob);\n \t\t\t? NULL \\\n \t\t\t: \"fsl,sec-v4.0-job-ring\"), \\\n \t\tstreamid, \\\n-\t\t(((streamid) << 16) | (streamid)), \\\n+\t\tSEC_ICID_REG_VAL(streamid), \\\n \t\toffsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \\\n \t\tCONFIG_SYS_FSL_SEC_ADDR, \\\n \t\tFSL_SEC_JR##jr_num##_BASE_ADDR, SEC_IS_LE)\n \n #define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \\\n-\tSET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \\\n+\tSET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \\\n \t\toffsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \\\n \t\tCONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)\n \n #define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \\\n-\tSET_ICID_ENTRY(NULL, streamid, (((streamid) << 16) | (streamid)), \\\n+\tSET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \\\n \t\toffsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \\\n \t\tCONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)\n \n extern struct icid_id_table icid_tbl[];\n-extern struct fman_icid_id_table fman_icid_tbl[];\n extern int icid_tbl_sz;\n-extern int fman_icid_tbl_sz;\n \n #endif\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h\nindex c53cc57e56..383eb259bd 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h\n@@ -98,4 +98,10 @@\n #define FSL_DPAA2_STREAM_ID_START\t23\n #define FSL_DPAA2_STREAM_ID_END\t\t63\n \n+#define FSL_SEC_STREAM_ID\t\t64\n+#define FSL_SEC_JR1_STREAM_ID\t\t65\n+#define FSL_SEC_JR2_STREAM_ID\t\t66\n+#define FSL_SEC_JR3_STREAM_ID\t\t67\n+#define FSL_SEC_JR4_STREAM_ID\t\t68\n+\n #endif\ndiff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c\nindex 6d11a134dc..7fde358325 100644\n--- a/board/freescale/ls1088a/ls1088a.c\n+++ b/board/freescale/ls1088a/ls1088a.c\n@@ -20,6 +20,7 @@\n #include <hwconfig.h>\n #include <asm/arch/fsl_serdes.h>\n #include <asm/arch/soc.h>\n+#include <asm/arch-fsl-layerscape/fsl_icid.h>\n \n #include \"../common/qixis.h\"\n #include \"ls1088a_qixis.h\"\n@@ -768,6 +769,9 @@ int ft_board_setup(void *blob, bd_t *bd)\n #ifdef CONFIG_FSL_MC_ENET\n \tfdt_fixup_board_enet(blob);\n #endif\n+\n+\tfdt_fixup_icid(blob);\n+\n \tif (is_pb_board())\n \t\tfixup_ls1088ardb_pb_banner(blob);\n \n", "prefixes": [ "U-Boot", "4/5" ] }