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GET /api/patches/1139004/?format=api
{ "id": 1139004, "url": "http://patchwork.ozlabs.org/api/patches/1139004/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190730142959.8467-2-laurentiu.tudor@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190730142959.8467-2-laurentiu.tudor@nxp.com>", "list_archive_url": null, "date": "2019-07-30T14:29:56", "name": "[U-Boot,2/5] armv8: fsl-layerscape: add base addresses for several devices", "commit_ref": "08f9bc9f4332e13a4ba4705d84d62e41a45b3fbe", "pull_url": null, "state": "accepted", "archived": false, "hash": "7e13e2c3c61846903786a55b2aa7b83930efd1fd", "submitter": { "id": 71003, "url": "http://patchwork.ozlabs.org/api/people/71003/?format=api", "name": "Laurentiu Tudor", "email": "laurentiu.tudor@nxp.com" }, "delegate": { "id": 2467, "url": "http://patchwork.ozlabs.org/api/users/2467/?format=api", "username": "prabhu_kush", "first_name": "Prabhakar", "last_name": "Kushwaha", "email": "prabhakar@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190730142959.8467-2-laurentiu.tudor@nxp.com/mbox/", "series": [ { "id": 122243, "url": "http://patchwork.ozlabs.org/api/series/122243/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=122243", "date": "2019-07-30T14:29:55", "name": "[U-Boot,1/5] armv8: fsl-layerscape: add missing sec jr base address defines", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/122243/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1139004/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1139004/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=nxp.com" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 45yfBG6tKyz9s00\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 31 Jul 2019 00:31:18 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 821D8C21E7F; Tue, 30 Jul 2019 14:30:18 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id E42CBC21E1B;\n\tTue, 30 Jul 2019 14:30:06 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid B22BFC21DEC; Tue, 30 Jul 2019 14:30:04 +0000 (UTC)", "from inva020.nxp.com (inva020.nxp.com [92.121.34.13])\n\tby lists.denx.de (Postfix) with ESMTPS id 68503C21E12\n\tfor <u-boot@lists.denx.de>; Tue, 30 Jul 2019 14:30:04 +0000 (UTC)", "from inva020.nxp.com (localhost [127.0.0.1])\n\tby inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 3B27F1A0708;\n\tTue, 30 Jul 2019 16:30:04 +0200 (CEST)", "from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com\n\t[134.27.226.22])\n\tby inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 2F68B1A150F;\n\tTue, 30 Jul 2019 16:30:04 +0200 (CEST)", "from fsr-ub1864-101.ea.freescale.net\n\t(fsr-ub1864-101.ea.freescale.net [10.171.82.13])\n\tby inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id D9A4F204D6;\n\tTue, 30 Jul 2019 16:30:03 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0", "From": "laurentiu.tudor@nxp.com", "To": "u-boot@lists.denx.de,\n\tprabhakar.kushwaha@nxp.com", "Date": "Tue, 30 Jul 2019 17:29:56 +0300", "Message-Id": "<20190730142959.8467-2-laurentiu.tudor@nxp.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190730142959.8467-1-laurentiu.tudor@nxp.com>", "References": "<20190730142959.8467-1-laurentiu.tudor@nxp.com>", "X-Virus-Scanned": "ClamAV using ClamSMTP", "Subject": "[U-Boot] [PATCH 2/5] armv8: fsl-layerscape: add base addresses for\n\tseveral devices", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Laurentiu Tudor <laurentiu.tudor@nxp.com>\n\nAdd CCSR base addresses for ESDHC2, EDMA QDMA, DISPLAY and GPU devices.\n\nSigned-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>\n---\n .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 15 +++++++++++++++\n 1 file changed, 15 insertions(+)", "diff": "diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\nindex 7cd5333ff4..84bed8d423 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n@@ -25,6 +25,8 @@\n #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR\t(CONFIG_SYS_IMMR + 0x00370000)\n #define SYS_FSL_QSPI_ADDR\t\t\t(CONFIG_SYS_IMMR + 0x010c0000)\n #define CONFIG_SYS_FSL_ESDHC_ADDR\t\t(CONFIG_SYS_IMMR + 0x01140000)\n+#define FSL_ESDHC1_BASE_ADDR\t\t\tCONFIG_SYS_FSL_ESDHC_ADDR\n+#define FSL_ESDHC2_BASE_ADDR\t\t\t(CONFIG_SYS_IMMR + 0x01150000)\n #ifndef CONFIG_NXP_LSCH3_2\n #define CONFIG_SYS_IFC_ADDR\t\t\t(CONFIG_SYS_IMMR + 0x01240000)\n #endif\n@@ -79,10 +81,23 @@\n #define TZASC_REGION_ATTRIBUTES_0(x)\t((TZASC1_BASE + (x * 0x10000)) + 0x110)\n #define TZASC_REGION_ID_ACCESS_0(x)\t((TZASC1_BASE + (x * 0x10000)) + 0x114)\n \n+/* EDMA */\n+#define EDMA_BASE_ADDR\t\t\t\t(CONFIG_SYS_IMMR + 0x012c0000)\n+\n /* SATA */\n #define AHCI_BASE_ADDR1\t\t\t\t(CONFIG_SYS_IMMR + 0x02200000)\n #define AHCI_BASE_ADDR2\t\t\t\t(CONFIG_SYS_IMMR + 0x02210000)\n \n+/* QDMA */\n+#define QDMA_BASE_ADDR\t\t\t\t(CONFIG_SYS_IMMR + 0x07380000)\n+#define QMAN_CQSIDR_REG\t\t\t\t0x20a80\n+\n+/* DISPLAY */\n+#define DISPLAY_BASE_ADDR\t\t\t(CONFIG_SYS_IMMR + 0x0e080000)\n+\n+/* GPU */\n+#define GPU_BASE_ADDR\t\t\t\t(CONFIG_SYS_IMMR + 0x0e0c0000)\n+\n /* SFP */\n #define CONFIG_SYS_SFP_ADDR\t\t(CONFIG_SYS_IMMR + 0x00e80200)\n \n", "prefixes": [ "U-Boot", "2/5" ] }