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GET /api/patches/1137377/?format=api
{ "id": 1137377, "url": "http://patchwork.ozlabs.org/api/patches/1137377/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190726112403.32842-2-chuanhua.han@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190726112403.32842-2-chuanhua.han@nxp.com>", "list_archive_url": null, "date": "2019-07-26T11:24:01", "name": "[U-Boot,v4,2/4] armv8: ls2088aqds: The ls2088aqds board supports the I2C driver model.", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "224a84d193e757a2f61e92d9724b11b26dd7c24c", "submitter": { "id": 74737, "url": "http://patchwork.ozlabs.org/api/people/74737/?format=api", "name": "Chuanhua Han", "email": "chuanhua.han@nxp.com" }, "delegate": { "id": 2467, "url": "http://patchwork.ozlabs.org/api/users/2467/?format=api", "username": "prabhu_kush", "first_name": "Prabhakar", "last_name": "Kushwaha", "email": "prabhakar@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190726112403.32842-2-chuanhua.han@nxp.com/mbox/", "series": [ { "id": 121633, "url": "http://patchwork.ozlabs.org/api/series/121633/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=121633", "date": "2019-07-26T11:24:00", "name": "[U-Boot,v4,1/4] rtc: ds3232/ds3231: Add support to generate 32KHz output for driver module", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/121633/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1137377/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1137377/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=nxp.com" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 45w6Ry1t6Lz9s4Y\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 26 Jul 2019 21:34:22 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid C82E5C21CB1; Fri, 26 Jul 2019 11:34:18 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id ACB32C21D56;\n\tFri, 26 Jul 2019 11:33:40 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 69ADBC21BE5; Fri, 26 Jul 2019 11:33:38 +0000 (UTC)", "from inva020.nxp.com (inva020.nxp.com [92.121.34.13])\n\tby lists.denx.de (Postfix) with ESMTPS id 61479C21C50\n\tfor <u-boot@lists.denx.de>; Fri, 26 Jul 2019 11:33:34 +0000 (UTC)", "from inva020.nxp.com (localhost [127.0.0.1])\n\tby inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 27F481A09D2;\n\tFri, 26 Jul 2019 13:33:34 +0200 (CEST)", "from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com\n\t[165.114.16.14])\n\tby inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 1762A1A01B5;\n\tFri, 26 Jul 2019 13:33:29 +0200 (CEST)", "from titan.ap.freescale.net (TITAN.ap.freescale.net\n\t[10.192.208.233])\n\tby invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id C95ED402F6;\n\tFri, 26 Jul 2019 19:33:22 +0800 (SGT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0", "From": "Chuanhua Han <chuanhua.han@nxp.com>", "To": "albert.u.boot@aribaud.net, prabhakar.kushwaha@nxp.com,\n\tpriyanka.jain@nxp.com, rajesh.bhagat@nxp.com", "Date": "Fri, 26 Jul 2019 19:24:01 +0800", "Message-Id": "<20190726112403.32842-2-chuanhua.han@nxp.com>", "X-Mailer": "git-send-email 2.9.5", "In-Reply-To": "<20190726112403.32842-1-chuanhua.han@nxp.com>", "References": "<20190726112403.32842-1-chuanhua.han@nxp.com>", "X-Virus-Scanned": "ClamAV using ClamSMTP", "Cc": "u-boot@lists.denx.de, Chuanhua Han <chuanhua.han@nxp.com>,\n\ttrini@konsulko.com", "Subject": "[U-Boot] [PATCH v4 2/4] armv8: ls2088aqds: The ls2088aqds board\n\tsupports the I2C driver model.", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "This patch is updating ls2088aqds board init code to support DM_I2C.\n\nSigned-off-by: Chuanhua Han <chuanhua.han@nxp.com>\n---\ndepends on:\n\t- http://patchwork.ozlabs.org/project/uboot/list/?series=118772\n\t- http://patchwork.ozlabs.org/project/uboot/list/?series=117226\n\nChanges in v4:\n\t- Simplify i2c_write related function calls and reduce\nthe amount of code by using circular iteration\n\t- Place the variable definitions for udevice at \nthe beginning of the function\nChanges in v3:\n\t- Delete something about DS3231_BUS_NUM\n\t- Modify the interface and definition of rtc_enable_32khz_output function\nChanges in v2:\n\t- No change.\n\n board/freescale/ls2080aqds/eth.c | 151 ++++++++++++++++++++++----------\n board/freescale/ls2080aqds/ls2080aqds.c | 16 ++++\n include/configs/ls2080aqds.h | 3 +\n 3 files changed, 123 insertions(+), 47 deletions(-)", "diff": "diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c\nindex f706fd4..baf031a 100644\n--- a/board/freescale/ls2080aqds/eth.c\n+++ b/board/freescale/ls2080aqds/eth.c\n@@ -89,11 +89,16 @@ struct ls2080a_qds_mdio {\n \tstruct mii_dev *realbus;\n };\n \n+struct reg_pair {\n+\tuint addr;\n+\tu8 *val;\n+};\n+\n static void sgmii_configure_repeater(int serdes_port)\n {\n \tstruct mii_dev *bus;\n \tuint8_t a = 0xf;\n-\tint i, j, ret;\n+\tint i, j, k, ret;\n \tint dpmac_id = 0, dpmac, mii_bus = 0;\n \tunsigned short value;\n \tchar dev[2][20] = {\"LS2080A_QDS_MDIO0\", \"LS2080A_QDS_MDIO3\"};\n@@ -104,10 +109,30 @@ static void sgmii_configure_repeater(int serdes_port)\n \tuint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};\n \tuint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};\n \n+\tu8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};\n+\tstruct reg_pair reg_pair[10] = {\n+\t\t\t{6, ®_val[0]}, {4, ®_val[1]},\n+\t\t\t{8, ®_val[2]}, {0xf, NULL},\n+\t\t\t{0x11, NULL}, {0x16, NULL},\n+\t\t\t{0x18, NULL}, {0x23, ®_val[3]},\n+\t\t\t{0x2d, ®_val[4]}, {4, ®_val[5]},\n+\t};\n+\n \tint *riser_phy_addr = &xqsgii_riser_phy_addr[0];\n+#ifdef CONFIG_DM_I2C\n+\tstruct udevice *udev;\n+#endif\n \n \t/* Set I2c to Slot 1 */\n-\ti2c_write(0x77, 0, 0, &a, 1);\n+#ifndef CONFIG_DM_I2C\n+\tret = i2c_write(0x77, 0, 0, &a, 1);\n+#else\n+\tret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);\n+\tif (!ret)\n+\t\tret = dm_i2c_write(udev, 0, &a, 1);\n+#endif\n+\tif (ret)\n+\t\tgoto error;\n \n \tfor (dpmac = 0; dpmac < 8; dpmac++) {\n \t\t/* Check the PHY status */\n@@ -120,7 +145,15 @@ static void sgmii_configure_repeater(int serdes_port)\n \t\t\tmii_bus = 1;\n \t\t\tdpmac_id = dpmac + 9;\n \t\t\ta = 0xb;\n-\t\t\ti2c_write(0x76, 0, 0, &a, 1);\n+#ifndef CONFIG_DM_I2C\n+\t\t\tret = i2c_write(0x76, 0, 0, &a, 1);\n+#else\n+\t\t\tret = i2c_get_chip_for_busnum(0, 0x76, 1, &udev);\n+\t\t\tif (!ret)\n+\t\t\t\tret = dm_i2c_write(udev, 0, &a, 1);\n+#endif\n+\t\t\tif (ret)\n+\t\t\t\tgoto error;\n \t\t\tbreak;\n \t\t}\n \n@@ -153,29 +186,29 @@ static void sgmii_configure_repeater(int serdes_port)\n \n \t\tfor (i = 0; i < 4; i++) {\n \t\t\tfor (j = 0; j < 4; j++) {\n-\t\t\t\ta = 0x18;\n-\t\t\t\ti2c_write(i2c_addr[dpmac], 6, 1, &a, 1);\n-\t\t\t\ta = 0x38;\n-\t\t\t\ti2c_write(i2c_addr[dpmac], 4, 1, &a, 1);\n-\t\t\t\ta = 0x4;\n-\t\t\t\ti2c_write(i2c_addr[dpmac], 8, 1, &a, 1);\n-\n-\t\t\t\ti2c_write(i2c_addr[dpmac], 0xf, 1,\n-\t\t\t\t\t &ch_a_eq[i], 1);\n-\t\t\t\ti2c_write(i2c_addr[dpmac], 0x11, 1,\n-\t\t\t\t\t &ch_a_ctl2[j], 1);\n-\n-\t\t\t\ti2c_write(i2c_addr[dpmac], 0x16, 1,\n-\t\t\t\t\t &ch_b_eq[i], 1);\n-\t\t\t\ti2c_write(i2c_addr[dpmac], 0x18, 1,\n-\t\t\t\t\t &ch_b_ctl2[j], 1);\n-\n-\t\t\t\ta = 0x14;\n-\t\t\t\ti2c_write(i2c_addr[dpmac], 0x23, 1, &a, 1);\n-\t\t\t\ta = 0xb5;\n-\t\t\t\ti2c_write(i2c_addr[dpmac], 0x2d, 1, &a, 1);\n-\t\t\t\ta = 0x20;\n-\t\t\t\ti2c_write(i2c_addr[dpmac], 4, 1, &a, 1);\n+\t\t\t\treg_pair[3].val = &ch_a_eq[i];\n+\t\t\t\treg_pair[4].val = &ch_a_ctl2[j];\n+\t\t\t\treg_pair[5].val = &ch_b_eq[i];\n+\t\t\t\treg_pair[6].val = &ch_b_ctl2[j];\n+\n+\t\t\t\tfor (k = 0; k < 10; k++) {\n+#ifndef CONFIG_DM_I2C\n+\t\t\t\t\tret = i2c_write(i2c_addr[dpmac],\n+\t\t\t\t\t\t\treg_pair[k].addr,\n+\t\t\t\t\t\t\t1, reg_pair[k].val, 1);\n+#else\n+\t\t\t\t\tret = i2c_get_chip_for_busnum(0,\n+\t\t\t\t\t\t\t i2c_addr[dpmac],\n+\t\t\t\t\t\t\t 1, &udev);\n+\t\t\t\t\tif (!ret)\n+\t\t\t\t\t\tret = dm_i2c_write(udev,\n+\t\t\t\t\t\t\t reg_pair[k].addr,\n+\t\t\t\t\t\t\t reg_pair[k].val, 1);\n+#endif\n+\t\t\t\t\tif (ret)\n+\t\t\t\t\t\tgoto error;\n+\t\t\t\t}\n+\n \t\t\t\tmdelay(100);\n \t\t\t\tret = miiphy_read(dev[mii_bus],\n \t\t\t\t\t\t riser_phy_addr[dpmac],\n@@ -216,7 +249,7 @@ error:\n static void qsgmii_configure_repeater(int dpmac)\n {\n \tuint8_t a = 0xf;\n-\tint i, j;\n+\tint i, j, k;\n \tint i2c_phy_addr = 0;\n \tint phy_addr = 0;\n \tint i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};\n@@ -226,12 +259,32 @@ static void qsgmii_configure_repeater(int dpmac)\n \tuint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};\n \tuint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};\n \n+\tu8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};\n+\tstruct reg_pair reg_pair[10] = {\n+\t\t{6, ®_val[0]}, {4, ®_val[1]},\n+\t\t{8, ®_val[2]}, {0xf, NULL},\n+\t\t{0x11, NULL}, {0x16, NULL},\n+\t\t{0x18, NULL}, {0x23, ®_val[3]},\n+\t\t{0x2d, ®_val[4]}, {4, ®_val[5]},\n+\t};\n+\n \tconst char *dev = \"LS2080A_QDS_MDIO0\";\n \tint ret = 0;\n \tunsigned short value;\n+#ifdef CONFIG_DM_I2C\n+\tstruct udevice *udev;\n+#endif\n \n \t/* Set I2c to Slot 1 */\n-\ti2c_write(0x77, 0, 0, &a, 1);\n+#ifndef CONFIG_DM_I2C\n+\tret = i2c_write(0x77, 0, 0, &a, 1);\n+#else\n+\tret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);\n+\tif (!ret)\n+\t\tret = dm_i2c_write(udev, 0, &a, 1);\n+#endif\n+\tif (ret)\n+\t\tgoto error;\n \n \tswitch (dpmac) {\n \tcase 1:\n@@ -282,25 +335,29 @@ static void qsgmii_configure_repeater(int dpmac)\n \n \tfor (i = 0; i < 4; i++) {\n \t\tfor (j = 0; j < 4; j++) {\n-\t\t\ta = 0x18;\n-\t\t\ti2c_write(i2c_phy_addr, 6, 1, &a, 1);\n-\t\t\ta = 0x38;\n-\t\t\ti2c_write(i2c_phy_addr, 4, 1, &a, 1);\n-\t\t\ta = 0x4;\n-\t\t\ti2c_write(i2c_phy_addr, 8, 1, &a, 1);\n-\n-\t\t\ti2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);\n-\t\t\ti2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);\n-\n-\t\t\ti2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);\n-\t\t\ti2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);\n-\n-\t\t\ta = 0x14;\n-\t\t\ti2c_write(i2c_phy_addr, 0x23, 1, &a, 1);\n-\t\t\ta = 0xb5;\n-\t\t\ti2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);\n-\t\t\ta = 0x20;\n-\t\t\ti2c_write(i2c_phy_addr, 4, 1, &a, 1);\n+\t\t\treg_pair[3].val = &ch_a_eq[i];\n+\t\t\treg_pair[4].val = &ch_a_ctl2[j];\n+\t\t\treg_pair[5].val = &ch_b_eq[i];\n+\t\t\treg_pair[6].val = &ch_b_ctl2[j];\n+\n+\t\t\tfor (k = 0; k < 10; k++) {\n+#ifndef CONFIG_DM_I2C\n+\t\t\t\tret = i2c_write(i2c_phy_addr,\n+\t\t\t\t\t\treg_pair[k].addr,\n+\t\t\t\t\t\t1, reg_pair[k].val, 1);\n+#else\n+\t\t\t\tret = i2c_get_chip_for_busnum(0,\n+\t\t\t\t\t\ti2c_phy_addr,\n+\t\t\t\t\t\t1, &udev);\n+\t\t\t\tif (!ret)\n+\t\t\t\t\tret = dm_i2c_write(udev,\n+\t\t\t\t\t\t\t reg_pair[k].addr,\n+\t\t\t\t\t\t\t reg_pair[k].val, 1);\n+#endif\n+\t\t\t\tif (ret)\n+\t\t\t\t\tgoto error;\n+\t\t\t}\n+\n \t\t\tmdelay(100);\n \t\t\tret = miiphy_read(dev, phy_addr, 0x11, &value);\n \t\t\tif (ret > 0)\ndiff --git a/board/freescale/ls2080aqds/ls2080aqds.c b/board/freescale/ls2080aqds/ls2080aqds.c\nindex a0a3301..b3d120b 100644\n--- a/board/freescale/ls2080aqds/ls2080aqds.c\n+++ b/board/freescale/ls2080aqds/ls2080aqds.c\n@@ -160,8 +160,16 @@ unsigned long get_board_ddr_clk(void)\n int select_i2c_ch_pca9547(u8 ch)\n {\n \tint ret;\n+#ifdef CONFIG_DM_I2C\n+\tstruct udevice *dev;\n \n+\tret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);\n+\tif (!ret)\n+\t\tret = dm_i2c_write(dev, 0, &ch, 1);\n+\n+#else\n \tret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);\n+#endif\n \tif (ret) {\n \t\tputs(\"PCA: failed to select proper channel\\n\");\n \t\treturn ret;\n@@ -224,7 +232,15 @@ int board_init(void)\n \tgd->env_addr = (ulong)&default_environment[0];\n #endif\n \tselect_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);\n+\n+#ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT\n+#ifdef CONFIG_DM_I2C\n+\trtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR);\n+#else\n \trtc_enable_32khz_output();\n+#endif\n+#endif\n+\n #ifdef CONFIG_FSL_CAAM\n \tsec_init();\n #endif\ndiff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h\nindex 18f30b5..05ff770 100644\n--- a/include/configs/ls2080aqds.h\n+++ b/include/configs/ls2080aqds.h\n@@ -16,7 +16,9 @@ unsigned long get_board_ddr_clk(void);\n \n #ifdef CONFIG_FSL_QSPI\n #define CONFIG_QIXIS_I2C_ACCESS\n+#ifndef CONFIG_DM_I2C\n #define CONFIG_SYS_I2C_EARLY_INIT\n+#endif\n #define CONFIG_SYS_I2C_IFDR_DIV\t\t0x7e\n #endif\n \n@@ -324,6 +326,7 @@ unsigned long get_board_ddr_clk(void);\n */\n #define RTC\n #define CONFIG_RTC_DS3231 1\n+#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT\n #define CONFIG_SYS_I2C_RTC_ADDR 0x68\n \n /* EEPROM */\n", "prefixes": [ "U-Boot", "v4", "2/4" ] }