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GET /api/patches/1137249/?format=api
{ "id": 1137249, "url": "http://patchwork.ozlabs.org/api/patches/1137249/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20190726061705.14764-2-krzk@kernel.org/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190726061705.14764-2-krzk@kernel.org>", "list_archive_url": null, "date": "2019-07-26T06:17:05", "name": "[v2,2/2] ARM: dts: imx6ul-kontron-n6310: Add Kontron i.MX6UL N6310 SoM and boards", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "6c6814996bc6eea7c7deb358018bf00197b617ba", "submitter": { "id": 68952, "url": "http://patchwork.ozlabs.org/api/people/68952/?format=api", "name": "Krzysztof Kozlowski", "email": "krzk@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/patch/20190726061705.14764-2-krzk@kernel.org/mbox/", "series": [ { "id": 121584, "url": "http://patchwork.ozlabs.org/api/series/121584/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=121584", "date": "2019-07-26T06:17:04", "name": "[v2,1/2] dt-bindings: vendor-prefixes: Add Admatec AG", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/121584/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1137249/comments/", "check": "fail", "checks": "http://patchwork.ozlabs.org/api/patches/1137249/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=kernel.org", "ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=kernel.org header.i=@kernel.org\n\theader.b=\"WgQj8mgE\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45vzQQ28tyz9sBF\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tFri, 26 Jul 2019 16:17:34 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1725867AbfGZGRd (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tFri, 26 Jul 2019 02:17:33 -0400", "from mail.kernel.org ([198.145.29.99]:59034 \"EHLO mail.kernel.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1726317AbfGZGRd (ORCPT <rfc822;devicetree@vger.kernel.org>);\n\tFri, 26 Jul 2019 02:17:33 -0400", "from localhost.localdomain (unknown [194.230.155.239])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128\n\tbits)) (No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id CEAEB21734;\n\tFri, 26 Jul 2019 06:17:27 +0000 (UTC)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=default; t=1564121850;\n\tbh=C3TajwOkwLXqDIi4QhjVSGK2y3X4sDvPm7m9eoKSf90=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=WgQj8mgEDbzo/I/+r4rOeSm6se1PO+nKRXozyNvYBb7oJ4D1907d2Fsvi3KVTuxMQ\n\tAhEAPPlP0Nt+LdCwhBO7bQmj+2IB0vMe6/reCXrF+hjIwlSrJ2p43Z6y/sA4yNnZFx\n\t0V9mFo8By0Ko7nAb0kk7G3hZYE/bf4jpIt/dEnzo=", "From": "Krzysztof Kozlowski <krzk@kernel.org>", "To": "Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,\n\tShawn Guo <shawnguo@kernel.org>, Sascha Hauer <s.hauer@pengutronix.de>,\n\tPengutronix Kernel Team <kernel@pengutronix.de>,\n\tFabio Estevam <festevam@gmail.com>, NXP Linux Team <linux-imx@nxp.com>,\n\tdevicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tSchrempf Frieder <frieder.schrempf@kontron.de>", "Cc": "Krzysztof Kozlowski <krzk@kernel.org>", "Subject": "[PATCH v2 2/2] ARM: dts: imx6ul-kontron-n6310: Add Kontron i.MX6UL\n\tN6310 SoM and boards", "Date": "Fri, 26 Jul 2019 08:17:05 +0200", "Message-Id": "<20190726061705.14764-2-krzk@kernel.org>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190726061705.14764-1-krzk@kernel.org>", "References": "<20190726061705.14764-1-krzk@kernel.org>", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "Add support for i.MX6UL modules from Kontron Electronics GmbH (before\nacquisition: Exceet Electronics) and evalkit boards based on it:\n\n1. N6310 SOM: i.MX6 UL System-on-Module, a 25x25 mm solderable module\n (LGA pads and pin castellations) with 256 MB RAM, 1 MB NOR-Flash,\n 256 MB NAND and other interfaces,\n2. N6310 S: evalkit, w/wo eMMC, without display,\n3. N6310 S 43: evalkit with 4.3\" display,\n4. N6310 S 50: evalkit with 5.0\" display.\n\nThis includes device nodes for unsupported displays (Admatec\nT043C004800272T2A and T070P133T0S301).\n\nThe work is based on Exceet/Kontron source code (GPLv2) with numerous\nchanges:\n1. Reorganize files,\n2. Rename Exceet -> Kontron,\n3. Rename models/compatibles to match newest Kontron product naming,\n4. Fix coding style errors,\n5. Fix DTC warnings,\n6. Extend compatibles so eval boards inherit the SoM compatible,\n7. Use defines instead of GPIO flag values,\n8. Use proper vendor compatible for Macronix SPI NOR,\n9. Sort nodes alphabetically.\n\nSigned-off-by: Krzysztof Kozlowski <krzk@kernel.org>\n\n---\n\nChanges since v1, after Frieder's review:\n1. Remove unneeded license notes,\n2. Add Kontron copyright (2018),\n3. Rename the files/models/compatibles to new naming - N6310,\n4. Remove unneeded CPU operating points override,\n5. Switch regulator nodes into simple children nodes without addresses\n (so not simple bus),\n6. Use proper vendor compatible for Macronix SPI NOR.\n---\n .../devicetree/bindings/arm/fsl.yaml | 4 +\n arch/arm/boot/dts/Makefile | 3 +\n .../boot/dts/imx6ul-kontron-n6310-s-43.dts | 120 +++++\n .../boot/dts/imx6ul-kontron-n6310-s-50.dts | 120 +++++\n arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts | 424 ++++++++++++++++++\n .../boot/dts/imx6ul-kontron-n6310-som.dtsi | 137 ++++++\n 6 files changed, 808 insertions(+)\n create mode 100644 arch/arm/boot/dts/imx6ul-kontron-n6310-s-43.dts\n create mode 100644 arch/arm/boot/dts/imx6ul-kontron-n6310-s-50.dts\n create mode 100644 arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts\n create mode 100644 arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi", "diff": "diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml\nindex 7294ac36f4c0..afb61a55e26f 100644\n--- a/Documentation/devicetree/bindings/arm/fsl.yaml\n+++ b/Documentation/devicetree/bindings/arm/fsl.yaml\n@@ -161,6 +161,10 @@ properties:\n items:\n - enum:\n - fsl,imx6ul-14x14-evk # i.MX6 UltraLite 14x14 EVK Board\n+ - kontron,n6310-som # Kontron N6310 SOM\n+ - kontron,n6310-s # Kontron N6310 S Board\n+ - kontron,n6310-s-43 # Kontron N6310 S 43 Board\n+ - kontron,n6310-s-50 # Kontron N6310 S 50 Board\n - const: fsl,imx6ul\n \n - description: i.MX6ULL based Boards\ndiff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile\nindex 9159fa2cea90..28b6cb3454a3 100644\n--- a/arch/arm/boot/dts/Makefile\n+++ b/arch/arm/boot/dts/Makefile\n@@ -569,6 +569,9 @@ dtb-$(CONFIG_SOC_IMX6UL) += \\\n \timx6ul-geam.dtb \\\n \timx6ul-isiot-emmc.dtb \\\n \timx6ul-isiot-nand.dtb \\\n+\timx6ul-kontron-n6310-s.dtb \\\n+\timx6ul-kontron-n6310-s-43.dtb \\\n+\timx6ul-kontron-n6310-s-50.dtb \\\n \timx6ul-liteboard.dtb \\\n \timx6ul-opos6uldev.dtb \\\n \timx6ul-pico-hobbit.dtb \\\ndiff --git a/arch/arm/boot/dts/imx6ul-kontron-n6310-s-43.dts b/arch/arm/boot/dts/imx6ul-kontron-n6310-s-43.dts\nnew file mode 100644\nindex 000000000000..63a0d8408fea\n--- /dev/null\n+++ b/arch/arm/boot/dts/imx6ul-kontron-n6310-s-43.dts\n@@ -0,0 +1,120 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (C) 2017 exceet electronics GmbH\n+ * Copyright (C) 2018 Kontron Electronics GmbH\n+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>\n+ */\n+\n+#include \"imx6ul-kontron-n6310-s.dts\"\n+\n+/ {\n+\tmodel = \"Kontron N6310 S 43\";\n+\tcompatible = \"kontron,n6310-s-43\", \"kontron,n6310-s\",\n+\t\t \"kontron,n6310-som\", \"fsl,imx6ul\";\n+\n+\tbacklight: backlight {\n+\t\tcompatible = \"pwm-backlight\";\n+\t\tpwms = <&pwm7 0 5000000>;\n+\t\tbrightness-levels = <0 4 8 16 32 64 128 255>;\n+\t\tdefault-brightness-level = <6>;\n+\t\tstatus = \"okay\";\n+\t};\n+\n+\tpanel {\n+\t\tcompatible = \"admatec,t043c004800272t2a\";\n+\t\tbacklight = <&backlight>;\n+\n+\t\tport {\n+\t\t\tpanel_in: endpoint {\n+\t\t\t\tremote-endpoint = <&display_out>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&i2c4 {\n+\tgt911@5d {\n+\t\tcompatible = \"goodix,gt928\";\n+\t\treg = <0x5d>;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_cap_touch>;\n+\t\tinterrupt-parent = <&gpio5>;\n+\t\tinterrupts = <6 8>;\n+\t\treset-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;\n+\t\tirq-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;\n+\t};\n+};\n+\n+&iomuxc {\n+\tpinctrl_lcdif_dat: lcdifdatgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_LCD_DATA00__LCDIF_DATA00\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA01__LCDIF_DATA01\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA02__LCDIF_DATA02\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA03__LCDIF_DATA03\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA04__LCDIF_DATA04\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA05__LCDIF_DATA05\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA06__LCDIF_DATA06\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA07__LCDIF_DATA07\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA08__LCDIF_DATA08\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA09__LCDIF_DATA09\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA10__LCDIF_DATA10\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA11__LCDIF_DATA11\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA12__LCDIF_DATA12\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA13__LCDIF_DATA13\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA14__LCDIF_DATA14\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA15__LCDIF_DATA15\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA16__LCDIF_DATA16\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA17__LCDIF_DATA17\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA18__LCDIF_DATA18\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA19__LCDIF_DATA19\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA20__LCDIF_DATA20\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA21__LCDIF_DATA21\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA22__LCDIF_DATA22\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA23__LCDIF_DATA23\t0x79\n+\t\t>;\n+\t};\n+\n+\tpinctrl_lcdif_ctrl: lcdifctrlgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_LCD_CLK__LCDIF_CLK\t\t0x79\n+\t\t\tMX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE\t0x79\n+\t\t\tMX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC\t0x79\n+\t\t\tMX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC\t0x79\n+\t\t\tMX6UL_PAD_LCD_RESET__LCDIF_RESET\t0x79\n+\t\t>;\n+\t};\n+\n+\tpinctrl_cap_touch: captouchgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06\t0x1b0b0 /* Touch Interrupt */\n+\t\t\tMX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07\t0x1b0b0 /* Touch Reset */\n+\t\t\tMX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08\t0x1b0b0 /* Touch Wake */\n+\t\t>;\n+\t};\n+\n+\tpinctrl_pwm7: pwm7grp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_CSI_VSYNC__PWM7_OUT\t\t0x110b0\n+\t\t>;\n+\t};\n+};\n+\n+&lcdif {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_lcdif_dat\n+\t\t &pinctrl_lcdif_ctrl>;\n+\tstatus = \"okay\";\n+\n+\tport {\n+\t\tdisplay_out: endpoint {\n+\t\t\tremote-endpoint = <&panel_in>;\n+\t\t};\n+\t};\n+};\n+\n+&pwm7 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_pwm7>;\n+\tstatus = \"okay\";\n+};\ndiff --git a/arch/arm/boot/dts/imx6ul-kontron-n6310-s-50.dts b/arch/arm/boot/dts/imx6ul-kontron-n6310-s-50.dts\nnew file mode 100644\nindex 000000000000..c3b133b3351e\n--- /dev/null\n+++ b/arch/arm/boot/dts/imx6ul-kontron-n6310-s-50.dts\n@@ -0,0 +1,120 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (C) 2017 exceet electronics GmbH\n+ * Copyright (C) 2018 Kontron Electronics GmbH\n+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>\n+ */\n+\n+#include \"imx6ul-kontron-n6310-s.dts\"\n+\n+/ {\n+\tmodel = \"Kontron N6310 S 50\";\n+\tcompatible = \"kontron,n6310-s-50\", \"kontron,n6310-s\",\n+\t\t \"kontron,n6310-som\", \"fsl,imx6ul\";\n+\n+\tbacklight: backlight {\n+\t\tcompatible = \"pwm-backlight\";\n+\t\tpwms = <&pwm7 0 5000000>;\n+\t\tbrightness-levels = <0 4 8 16 32 64 128 255>;\n+\t\tdefault-brightness-level = <6>;\n+\t\tstatus = \"okay\";\n+\t};\n+\n+\tpanel {\n+\t\tcompatible = \"admatec,t070p133t0s301\";\n+\t\tbacklight = <&backlight>;\n+\n+\t\tport {\n+\t\t\tpanel_in: endpoint {\n+\t\t\t\tremote-endpoint = <&display_out>;\n+\t\t\t};\n+\t\t};\n+\t};\n+};\n+\n+&i2c4 {\n+\tgt911@5d {\n+\t\tcompatible = \"goodix,gt928\";\n+\t\treg = <0x5d>;\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_cap_touch>;\n+\t\tinterrupt-parent = <&gpio5>;\n+\t\tinterrupts = <6 8>;\n+\t\treset-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;\n+\t\tirq-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;\n+\t};\n+};\n+\n+&iomuxc {\n+\tpinctrl_lcdif_dat: lcdifdatgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_LCD_DATA00__LCDIF_DATA00\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA01__LCDIF_DATA01\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA02__LCDIF_DATA02\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA03__LCDIF_DATA03\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA04__LCDIF_DATA04\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA05__LCDIF_DATA05\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA06__LCDIF_DATA06\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA07__LCDIF_DATA07\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA08__LCDIF_DATA08\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA09__LCDIF_DATA09\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA10__LCDIF_DATA10\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA11__LCDIF_DATA11\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA12__LCDIF_DATA12\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA13__LCDIF_DATA13\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA14__LCDIF_DATA14\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA15__LCDIF_DATA15\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA16__LCDIF_DATA16\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA17__LCDIF_DATA17\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA18__LCDIF_DATA18\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA19__LCDIF_DATA19\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA20__LCDIF_DATA20\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA21__LCDIF_DATA21\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA22__LCDIF_DATA22\t0x79\n+\t\t\tMX6UL_PAD_LCD_DATA23__LCDIF_DATA23\t0x79\n+\t\t>;\n+\t};\n+\n+\tpinctrl_lcdif_ctrl: lcdifctrlgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_LCD_CLK__LCDIF_CLK\t\t0x79\n+\t\t\tMX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE\t0x79\n+\t\t\tMX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC\t0x79\n+\t\t\tMX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC\t0x79\n+\t\t\tMX6UL_PAD_LCD_RESET__LCDIF_RESET\t0x79\n+\t\t>;\n+\t};\n+\n+\tpinctrl_cap_touch: captouchgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06\t0x1b0b0 /* Touch Interrupt */\n+\t\t\tMX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07\t0x1b0b0 /* Touch Reset */\n+\t\t\tMX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08\t0x1b0b0 /* Touch Wake */\n+\t\t>;\n+\t};\n+\n+\tpinctrl_pwm7: pwm7grp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_CSI_VSYNC__PWM7_OUT\t\t0x110b0\n+\t\t>;\n+\t};\n+};\n+\n+&lcdif {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_lcdif_dat\n+\t\t &pinctrl_lcdif_ctrl>;\n+\tstatus = \"okay\";\n+\n+\tport {\n+\t\tdisplay_out: endpoint {\n+\t\t\tremote-endpoint = <&panel_in>;\n+\t\t};\n+\t};\n+};\n+\n+&pwm7 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_pwm7>;\n+\tstatus = \"okay\";\n+};\ndiff --git a/arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts b/arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts\nnew file mode 100644\nindex 000000000000..5621a3dbf2dc\n--- /dev/null\n+++ b/arch/arm/boot/dts/imx6ul-kontron-n6310-s.dts\n@@ -0,0 +1,424 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (C) 2017 exceet electronics GmbH\n+ * Copyright (C) 2018 Kontron Electronics GmbH\n+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>\n+ */\n+\n+/dts-v1/;\n+\n+#include \"imx6ul-kontron-n6310-som.dtsi\"\n+\n+/ {\n+\tmodel = \"Kontron N6310 S\";\n+\tcompatible = \"kontron,n6310-s\", \"kontron,n6310-som\", \"fsl,imx6ul\";\n+\n+\tpwm-beeper {\n+\t\tcompatible = \"pwm-beeper\";\n+\t\tpwms = <&pwm8 0 5000>;\n+\t};\n+\n+\tgpio-leds {\n+\t\tcompatible = \"gpio-leds\";\n+\t\tpinctrl-names = \"default\";\n+\t\tpinctrl-0 = <&pinctrl_gpio_leds>;\n+\n+\t\tled1 {\n+\t\t\tlabel = \"debug-led1\";\n+\t\t\tgpios = <&gpio1 30 GPIO_ACTIVE_LOW>;\n+\t\t\tdefault-state = \"off\";\n+\t\t\tlinux,default-trigger = \"heartbeat\";\n+\t\t};\n+\n+\t\tled2 {\n+\t\t\tlabel = \"debug-led2\";\n+\t\t\tgpios = <&gpio5 3 GPIO_ACTIVE_LOW>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\n+\t\tled3 {\n+\t\t\tlabel = \"debug-led3\";\n+\t\t\tgpios = <&gpio5 2 GPIO_ACTIVE_LOW>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\t};\n+\n+\tregulators {\n+\t\treg_3v3: regulator1 {\n+\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\tregulator-name = \"3v3\";\n+\t\t\tregulator-min-microvolt = <3300000>;\n+\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t};\n+\n+\t\treg_vref_adc: regulator2 {\n+\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\tregulator-name = \"vref-adc\";\n+\t\t\tregulator-min-microvolt = <3300000>;\n+\t\t\tregulator-max-microvolt = <3300000>;\n+\t\t};\n+\n+\t\treg_usb_otg1_vbus: regulator3 {\n+\t\t\tcompatible = \"regulator-fixed\";\n+\t\t\tregulator-name = \"usb_otg1_vbus\";\n+\t\t\tregulator-min-microvolt = <5000000>;\n+\t\t\tregulator-max-microvolt = <5000000>;\n+\t\t\tgpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;\n+\t\t\tenable-active-high;\n+\t\t};\n+\t};\n+\n+};\n+\n+&adc1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_adc1>;\n+\tnum-channels = <3>;\n+\tvref-supply = <®_vref_adc>;\n+\tstatus = \"okay\";\n+};\n+\n+&can2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_flexcan2>;\n+\tstatus = \"okay\";\n+};\n+\n+&ecspi1 {\n+\tfsl,spi-num-chipselects = <1>;\n+\tcs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_ecspi1>;\n+\tstatus = \"okay\";\n+\n+\tfram@0 {\n+\t\tcompatible = \"atmel,at25\";\n+\t\treg = <0>;\n+\t\tspi-max-frequency = <20000000>;\n+\t\tspi-cpha;\n+\t\tspi-cpol;\n+\t\tpagesize = <1>;\n+\t\tsize = <8192>;\n+\t\taddress-width = <16>;\n+\t};\n+};\n+\n+&fec1 {\n+\tpinctrl-0 = <&pinctrl_enet1>;\n+\t/delete-node/ mdio;\n+};\n+\n+&fec2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;\n+\tphy-mode = \"rmii\";\n+\tphy-handle = <ðphy2>;\n+\tstatus = \"okay\";\n+\n+\tmdio {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tethphy1: ethernet-phy@1 {\n+\t\t\treg = <1>;\n+\t\t\tmicrel,led-mode = <0>;\n+\t\t\tclocks = <&clks IMX6UL_CLK_ENET_REF>;\n+\t\t\tclock-names = \"rmii-ref\";\n+\t\t};\n+\n+\t\tethphy2: ethernet-phy@2 {\n+\t\t\treg = <2>;\n+\t\t\tmicrel,led-mode = <0>;\n+\t\t\tclocks = <&clks IMX6UL_CLK_ENET2_REF>;\n+\t\t\tclock-names = \"rmii-ref\";\n+\t\t};\n+\t};\n+};\n+\n+&i2c1 {\n+\tclock-frequency = <100000>;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_i2c1>;\n+\tstatus = \"okay\";\n+};\n+\n+&i2c4 {\n+\tclock-frequency = <100000>;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_i2c4>;\n+\tstatus = \"okay\";\n+\n+\trtc@32 {\n+\t\tcompatible = \"epson,rx8900\";\n+\t\treg = <0x32>;\n+\t};\n+};\n+\n+&iomuxc {\n+\tpinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;\n+\n+\tpinctrl_wdog: wdoggrp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY\t0x30b0\n+\t\t>;\n+\t};\n+\n+\tpinctrl_gpio: gpio {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05\t0x1b0b0 /* DOUT1 */\n+\t\t\tMX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04\t0x1b0b0 /* DIN1 */\n+\t\t\tMX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01\t0x1b0b0 /* DOUT2 */\n+\t\t\tMX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00\t0x1b0b0 /* DIN2 */\n+\t\t>;\n+\t};\n+\n+\tpinctrl_usbotg1: usbotg1 {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_GPIO1_IO04__GPIO1_IO04\t0x1b0b0\n+\t\t>;\n+\t};\n+\n+\tpinctrl_gpio_leds: gpio_leds {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_UART5_TX_DATA__GPIO1_IO30\t0x1b0b0\t/* LED H14 */\n+\t\t\tMX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03\t0x1b0b0\t/* LED H15 */\n+\t\t\tMX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02\t0x1b0b0\t/* LED H16 */\n+\t\t>;\n+\t};\n+\n+\t/* FRAM */\n+\tpinctrl_ecspi1: ecspi1grp-1 {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_CSI_DATA07__ECSPI1_MISO\t0x100b1\n+\t\t\tMX6UL_PAD_CSI_DATA06__ECSPI1_MOSI\t0x100b1\n+\t\t\tMX6UL_PAD_CSI_DATA04__ECSPI1_SCLK\t0x100b1\n+\t\t\tMX6UL_PAD_CSI_DATA05__GPIO4_IO26\t0x100b1\t/* ECSPI1-CS1 */\n+\t\t>;\n+\t};\n+\n+\tpinctrl_enet2: enet2grp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN\t0x1b0b0\n+\t\t\tMX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER\t0x1b0b0\n+\t\t\tMX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00\t0x1b0b0\n+\t\t\tMX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01\t0x1b0b0\n+\t\t\tMX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN\t0x1b0b0\n+\t\t\tMX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00\t0x1b0b0\n+\t\t\tMX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01\t0x1b0b0\n+\t\t\tMX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2\t0x4001b009\n+\t\t>;\n+\t};\n+\n+\tpinctrl_enet2_mdio: enet2mdiogrp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0\n+\t\t\tMX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0\n+\t\t>;\n+\t};\n+\n+\tpinctrl_flexcan2: flexcan2grp{\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX\t0x1b020\n+\t\t\tMX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX\t0x1b020\n+\t\t>;\n+\t};\n+\n+\tpinctrl_pwm8: pwm8grp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_CSI_HSYNC__PWM8_OUT\t\t0x110b0\n+\t\t>;\n+\t};\n+\n+\tpinctrl_uart1: uart1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX\t0x1b0b1\n+\t\t\tMX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX\t0x1b0b1\n+\t\t>;\n+\t};\n+\n+\tpinctrl_uart2: uart2grp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_NAND_DATA04__UART2_DCE_TX\t0x1b0b1\n+\t\t\tMX6UL_PAD_NAND_DATA05__UART2_DCE_RX\t0x1b0b1\n+\t\t\tMX6UL_PAD_NAND_DATA06__UART2_DCE_CTS\t0x1b0b1\n+\t\t\t/*\n+\t\t\t * mux unused RTS to make sure it doesn't cause\n+\t\t\t * any interrupts when it is undefined\n+\t\t\t */\n+\t\t\tMX6UL_PAD_NAND_DATA07__UART2_DCE_RTS\t0x1b0b1\n+\t\t>;\n+\t};\n+\n+\tpinctrl_uart3: uart3grp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX\t0x1b0b1\n+\t\t\tMX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX\t0x1b0b1\n+\t\t\tMX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS\t0x1b0b1\n+\t\t\tMX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS\t0x1b0b1\n+\t\t>;\n+\t};\n+\n+\tpinctrl_uart4: uart4grp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX\t0x1b0b1\n+\t\t\tMX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX\t0x1b0b1\n+\t\t>;\n+\t};\n+\n+\tpinctrl_usdhc1: usdhc1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_SD1_CMD__USDHC1_CMD\t\t0x17059\n+\t\t\tMX6UL_PAD_SD1_CLK__USDHC1_CLK\t\t0x10059\n+\t\t\tMX6UL_PAD_SD1_DATA0__USDHC1_DATA0\t0x17059\n+\t\t\tMX6UL_PAD_SD1_DATA1__USDHC1_DATA1\t0x17059\n+\t\t\tMX6UL_PAD_SD1_DATA2__USDHC1_DATA2\t0x17059\n+\t\t\tMX6UL_PAD_SD1_DATA3__USDHC1_DATA3\t0x17059\n+\t\t\tMX6UL_PAD_UART1_RTS_B__GPIO1_IO19\t0x100b1\t/* SD1_CD */\n+\t\t>;\n+\t};\n+\n+\tpinctrl_usdhc2: usdhc2grp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_NAND_RE_B__USDHC2_CLK\t\t0x10059\n+\t\t\tMX6UL_PAD_NAND_WE_B__USDHC2_CMD\t\t0x17059\n+\t\t\tMX6UL_PAD_NAND_DATA00__USDHC2_DATA0\t0x17059\n+\t\t\tMX6UL_PAD_NAND_DATA01__USDHC2_DATA1\t0x17059\n+\t\t\tMX6UL_PAD_NAND_DATA02__USDHC2_DATA2\t0x17059\n+\t\t\tMX6UL_PAD_NAND_DATA03__USDHC2_DATA3\t0x17059\n+\t\t>;\n+\t};\n+\n+\tpinctrl_usdhc2_100mhz: usdhc2grp100mhz {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_NAND_RE_B__USDHC2_CLK\t\t0x100b9\n+\t\t\tMX6UL_PAD_NAND_WE_B__USDHC2_CMD\t\t0x170b9\n+\t\t\tMX6UL_PAD_NAND_DATA00__USDHC2_DATA0\t0x170b9\n+\t\t\tMX6UL_PAD_NAND_DATA01__USDHC2_DATA1\t0x170b9\n+\t\t\tMX6UL_PAD_NAND_DATA02__USDHC2_DATA2\t0x170b9\n+\t\t\tMX6UL_PAD_NAND_DATA03__USDHC2_DATA3\t0x170b9\n+\t\t>;\n+\t};\n+\n+\tpinctrl_usdhc2_200mhz: usdhc2grp200mhz {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_NAND_RE_B__USDHC2_CLK\t\t0x100f9\n+\t\t\tMX6UL_PAD_NAND_WE_B__USDHC2_CMD\t\t0x170f9\n+\t\t\tMX6UL_PAD_NAND_DATA00__USDHC2_DATA0\t0x170f9\n+\t\t\tMX6UL_PAD_NAND_DATA01__USDHC2_DATA1\t0x170f9\n+\t\t\tMX6UL_PAD_NAND_DATA02__USDHC2_DATA2\t0x170f9\n+\t\t\tMX6UL_PAD_NAND_DATA03__USDHC2_DATA3\t0x170f9\n+\t\t>;\n+\t};\n+\n+\tpinctrl_i2c1: i2c1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_CSI_PIXCLK__I2C1_SCL\t\t0x4001b8b0\n+\t\t\tMX6UL_PAD_CSI_MCLK__I2C1_SDA\t\t0x4001b8b0\n+\t\t>;\n+\t};\n+\n+\tpinctrl_i2c4: i2c4grp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_UART2_TX_DATA__I2C4_SCL\t0x4001f8b0\n+\t\t\tMX6UL_PAD_UART2_RX_DATA__I2C4_SDA\t0x4001f8b0\n+\t\t>;\n+\t};\n+\n+\tpinctrl_adc1: adc1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_GPIO1_IO02__GPIO1_IO02\t0xb0\n+\t\t\tMX6UL_PAD_GPIO1_IO03__GPIO1_IO03\t0xb0\n+\t\t\tMX6UL_PAD_GPIO1_IO08__GPIO1_IO08\t0xb0\n+\t\t>;\n+\t};\n+};\n+\n+&pwm8 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_pwm8>;\n+\tstatus = \"okay\";\n+};\n+\n+&snvs_poweroff {\n+\tstatus = \"okay\";\n+};\n+\n+&uart1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_uart1>;\n+\tstatus = \"okay\";\n+};\n+\n+&uart2 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_uart2>;\n+\tlinux,rs485-enabled-at-boot-time;\n+\trs485-rx-during-tx;\n+\trs485-rts-active-low;\n+\tuart-has-rtscts;\n+\tstatus = \"okay\";\n+};\n+\n+&uart3 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_uart3>;\n+\tfsl,uart-has-rtscts;\n+\tstatus = \"okay\";\n+};\n+\n+&uart4 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_uart4>;\n+\tstatus = \"okay\";\n+};\n+\n+&usbotg1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_usbotg1>;\n+\tdr_mode = \"otg\";\n+\tstatus = \"okay\";\n+\tsrp-disable;\n+\thnp-disable;\n+\tadp-disable;\n+\tvbus-supply = <®_usb_otg1_vbus>;\n+};\n+\n+&usbotg2 {\n+\tdr_mode = \"host\";\n+\tdisable-over-current;\n+\tstatus = \"okay\";\n+};\n+\n+&usdhc1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_usdhc1>;\n+\tcd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;\n+\tkeep-power-in-suspend;\n+\tenable-sdio-wakeup;\n+\tvmmc-supply = <®_3v3>;\n+\tvoltage-ranges = <3300 3300>;\n+\tno-1-8-v;\n+\tstatus = \"okay\";\n+};\n+\n+&usdhc2 {\n+\tpinctrl-names = \"default\", \"state_100mhz\", \"state_200mhz\";\n+\tpinctrl-0 = <&pinctrl_usdhc2>;\n+\tpinctrl-1 = <&pinctrl_usdhc2_100mhz>;\n+\tpinctrl-2 = <&pinctrl_usdhc2_200mhz>;\n+\ttuning-step = <2>;\n+\tnon-removable;\n+\tkeep-power-in-suspend;\n+\tenable-sdio-wakeup;\n+\tvmmc-supply = <®_3v3>;\n+\tvoltage-ranges = <3300 3300>;\n+\tno-1-8-v;\n+\tstatus = \"okay\";\n+};\n+\n+&wdog1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_wdog>;\n+\tstatus = \"okay\";\n+\tfsl,ext-reset-output;\n+};\ndiff --git a/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi b/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi\nnew file mode 100644\nindex 000000000000..084a8ccd574e\n--- /dev/null\n+++ b/arch/arm/boot/dts/imx6ul-kontron-n6310-som.dtsi\n@@ -0,0 +1,137 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (C) 2017 exceet electronics GmbH\n+ * Copyright (C) 2018 Kontron Electronics GmbH\n+ * Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>\n+ */\n+\n+#include \"imx6ul.dtsi\"\n+#include <dt-bindings/gpio/gpio.h>\n+\n+/ {\n+\tmodel = \"Kontron N6310 SOM\";\n+\tcompatible = \"kontron,n6310-som\", \"fsl,imx6ul\";\n+\n+\tmemory@80000000 {\n+\t\treg = <0x80000000 0x10000000>;\n+\t};\n+};\n+\n+&cpu0 {\n+\tclock-frequency = <528000000>;\n+};\n+\n+&ecspi2 {\n+\tcs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_ecspi2>;\n+\tstatus = \"okay\";\n+\n+\tflash: mx25v80@0 {\n+\t\tcompatible = \"mxicy,mx25v8035f\", \"jedec,spi-nor\";\n+\t\tspi-max-frequency = <50000000>;\n+\t\treg = <0>;\n+\t};\n+};\n+\n+&fec1 {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;\n+\tphy-mode = \"rmii\";\n+\tphy-handle = <ðphy1>;\n+\tstatus = \"okay\";\n+\n+\tmdio {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tethphy1: ethernet-phy@1 {\n+\t\t\treg = <1>;\n+\t\t\tmicrel,led-mode = <0>;\n+\t\t\tclocks = <&clks IMX6UL_CLK_ENET_REF>;\n+\t\t\tclock-names = \"rmii-ref\";\n+\t\t};\n+\t};\n+};\n+\n+&fec2 {\n+\tphy-mode = \"rmii\";\n+\tstatus = \"disabled\";\n+};\n+\n+&iomuxc {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_reset_out>;\n+\n+\tpinctrl_reset_out: rstoutgrp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0\n+\t\t>;\n+\t};\n+\n+\tpinctrl_ecspi2: ecspi2grp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1\n+\t\t\tMX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1\n+\t\t\tMX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1\n+\t\t\tMX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1\n+\t\t>;\n+\t};\n+\n+\tpinctrl_enet1: enet1grp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0\n+\t\t\tMX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0\n+\t\t\tMX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0\n+\t\t\tMX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0\n+\t\t\tMX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0\n+\t\t\tMX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0\n+\t\t\tMX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0\n+\t\t\tMX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009\n+\t\t>;\n+\t};\n+\n+\tpinctrl_enet1_mdio: enet1mdiogrp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0\n+\t\t\tMX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0\n+\t\t>;\n+\t};\n+\n+\tpinctrl_qspi: qspigrp {\n+\t\tfsl,pins = <\n+\t\t\tMX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1\n+\t\t\tMX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1\n+\t\t\tMX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1\n+\t\t\tMX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1\n+\t\t\tMX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1\n+\t\t\tMX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1\n+\t\t>;\n+\t};\n+};\n+\n+&qspi {\n+\tpinctrl-names = \"default\";\n+\tpinctrl-0 = <&pinctrl_qspi>;\n+\tstatus = \"okay\";\n+\n+\tflash0: w25m02gv@0 {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tcompatible = \"spi-nand\";\n+\t\tspi-max-frequency = <108000000>;\n+\t\tspi-tx-bus-width = <4>;\n+\t\tspi-rx-bus-width = <4>;\n+\t\treg = <0>;\n+\n+\t\tpartition@0 {\n+\t\t\tlabel = \"ubi1\";\n+\t\t\treg = <0x00000000 0x08000000>;\n+\t\t};\n+\n+\t\tpartition@8000000 {\n+\t\t\tlabel = \"ubi2\";\n+\t\t\treg = <0x08000000 0x08000000>;\n+\t\t};\n+\t};\n+};\n", "prefixes": [ "v2", "2/2" ] }