Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/1137055/?format=api
{ "id": 1137055, "url": "http://patchwork.ozlabs.org/api/patches/1137055/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190725095401.24590-4-anthony.l.nguyen@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190725095401.24590-4-anthony.l.nguyen@intel.com>", "list_archive_url": null, "date": "2019-07-25T09:53:53", "name": "[S25,04/12] ice: Fix ethtool port and PFC stats for 4x25G cards", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "59c9b5684b17b7084d521fde38e4f77448a4d143", "submitter": { "id": 68875, "url": "http://patchwork.ozlabs.org/api/people/68875/?format=api", "name": "Tony Nguyen", "email": "anthony.l.nguyen@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190725095401.24590-4-anthony.l.nguyen@intel.com/mbox/", "series": [ { "id": 121514, "url": "http://patchwork.ozlabs.org/api/series/121514/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=121514", "date": "2019-07-25T09:53:50", "name": "[S25,01/12] ice: update ethtool stats on-demand", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/121514/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1137055/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1137055/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.138; helo=whitealder.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 45vgYH1wpBz9sBt\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 26 Jul 2019 04:22:26 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id C87618748A;\n\tThu, 25 Jul 2019 18:22:24 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id uXD1fprYPbaz; Thu, 25 Jul 2019 18:22:21 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 3631A8743E;\n\tThu, 25 Jul 2019 18:22:21 +0000 (UTC)", "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\tby ash.osuosl.org (Postfix) with ESMTP id 4FC131BF2C8\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 25 Jul 2019 18:22:19 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 4D42A86582\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 25 Jul 2019 18:22:19 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id pF9aymy8qHhC for <intel-wired-lan@lists.osuosl.org>;\n\tThu, 25 Jul 2019 18:22:18 +0000 (UTC)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby fraxinus.osuosl.org (Postfix) with ESMTPS id 57ECC86591\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 25 Jul 2019 18:22:18 +0000 (UTC)", "from fmsmga004.fm.intel.com ([10.253.24.48])\n\tby fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t25 Jul 2019 11:22:17 -0700", "from unknown (HELO localhost.jf.intel.com) ([10.166.244.174])\n\tby fmsmga004.fm.intel.com with ESMTP; 25 Jul 2019 11:22:17 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,307,1559545200\"; d=\"scan'208\";a=\"193897601\"", "From": "Tony Nguyen <anthony.l.nguyen@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Thu, 25 Jul 2019 02:53:53 -0700", "Message-Id": "<20190725095401.24590-4-anthony.l.nguyen@intel.com>", "X-Mailer": "git-send-email 2.20.1", "In-Reply-To": "<20190725095401.24590-1-anthony.l.nguyen@intel.com>", "References": "<20190725095401.24590-1-anthony.l.nguyen@intel.com>", "MIME-Version": "1.0", "Subject": "[Intel-wired-lan] [PATCH S25 04/12] ice: Fix ethtool port and PFC\n\tstats for 4x25G cards", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Usha Ketineni <usha.k.ketineni@intel.com>\n\nThis patch fixes the issue where port and PFC statistics counters are\nincrementing at the wrong port with 4x25G cards.\nRead the GLPRT port registers using lport parameter instead of pf_id to\nupdate the statistics otherwise the pf_ids are flipped for ports 2 and 3\nwhen read from the HW register PF_FUNC_RID and this is expected as per\nhardware specification.\n\nSigned-off-by: Usha Ketineni <usha.k.ketineni@intel.com>\n---\n drivers/net/ethernet/intel/ice/ice_dcb_lib.c | 13 ++--\n drivers/net/ethernet/intel/ice/ice_main.c | 76 ++++++++++----------\n 2 files changed, 45 insertions(+), 44 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/ice/ice_dcb_lib.c b/drivers/net/ethernet/intel/ice/ice_dcb_lib.c\nindex 21405958aa63..34c9d1e01529 100644\n--- a/drivers/net/ethernet/intel/ice/ice_dcb_lib.c\n+++ b/drivers/net/ethernet/intel/ice/ice_dcb_lib.c\n@@ -505,30 +505,31 @@ void ice_update_dcb_stats(struct ice_pf *pf)\n {\n \tstruct ice_hw_port_stats *prev_ps, *cur_ps;\n \tstruct ice_hw *hw = &pf->hw;\n-\tu8 pf_id = hw->pf_id;\n+\tu8 port;\n \tint i;\n \n+\tport = hw->port_info->lport;\n \tprev_ps = &pf->stats_prev;\n \tcur_ps = &pf->stats;\n \n \tfor (i = 0; i < 8; i++) {\n-\t\tice_stat_update32(hw, GLPRT_PXOFFRXC(pf_id, i),\n+\t\tice_stat_update32(hw, GLPRT_PXOFFRXC(port, i),\n \t\t\t\t pf->stat_prev_loaded,\n \t\t\t\t &prev_ps->priority_xoff_rx[i],\n \t\t\t\t &cur_ps->priority_xoff_rx[i]);\n-\t\tice_stat_update32(hw, GLPRT_PXONRXC(pf_id, i),\n+\t\tice_stat_update32(hw, GLPRT_PXONRXC(port, i),\n \t\t\t\t pf->stat_prev_loaded,\n \t\t\t\t &prev_ps->priority_xon_rx[i],\n \t\t\t\t &cur_ps->priority_xon_rx[i]);\n-\t\tice_stat_update32(hw, GLPRT_PXONTXC(pf_id, i),\n+\t\tice_stat_update32(hw, GLPRT_PXONTXC(port, i),\n \t\t\t\t pf->stat_prev_loaded,\n \t\t\t\t &prev_ps->priority_xon_tx[i],\n \t\t\t\t &cur_ps->priority_xon_tx[i]);\n-\t\tice_stat_update32(hw, GLPRT_PXOFFTXC(pf_id, i),\n+\t\tice_stat_update32(hw, GLPRT_PXOFFTXC(port, i),\n \t\t\t\t pf->stat_prev_loaded,\n \t\t\t\t &prev_ps->priority_xoff_tx[i],\n \t\t\t\t &cur_ps->priority_xoff_tx[i]);\n-\t\tice_stat_update32(hw, GLPRT_RXON2OFFCNT(pf_id, i),\n+\t\tice_stat_update32(hw, GLPRT_RXON2OFFCNT(port, i),\n \t\t\t\t pf->stat_prev_loaded,\n \t\t\t\t &prev_ps->priority_xon_2_xoff[i],\n \t\t\t\t &cur_ps->priority_xon_2_xoff[i]);\ndiff --git a/drivers/net/ethernet/intel/ice/ice_main.c b/drivers/net/ethernet/intel/ice/ice_main.c\nindex 072771543582..920122443c0f 100644\n--- a/drivers/net/ethernet/intel/ice/ice_main.c\n+++ b/drivers/net/ethernet/intel/ice/ice_main.c\n@@ -3298,25 +3298,25 @@ void ice_update_pf_stats(struct ice_pf *pf)\n {\n \tstruct ice_hw_port_stats *prev_ps, *cur_ps;\n \tstruct ice_hw *hw = &pf->hw;\n-\tu8 pf_id;\n+\tu8 port;\n \n+\tport = hw->port_info->lport;\n \tprev_ps = &pf->stats_prev;\n \tcur_ps = &pf->stats;\n-\tpf_id = hw->pf_id;\n \n-\tice_stat_update40(hw, GLPRT_GORCL(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update40(hw, GLPRT_GORCL(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->eth.rx_bytes,\n \t\t\t &cur_ps->eth.rx_bytes);\n \n-\tice_stat_update40(hw, GLPRT_UPRCL(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update40(hw, GLPRT_UPRCL(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->eth.rx_unicast,\n \t\t\t &cur_ps->eth.rx_unicast);\n \n-\tice_stat_update40(hw, GLPRT_MPRCL(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update40(hw, GLPRT_MPRCL(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->eth.rx_multicast,\n \t\t\t &cur_ps->eth.rx_multicast);\n \n-\tice_stat_update40(hw, GLPRT_BPRCL(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update40(hw, GLPRT_BPRCL(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->eth.rx_broadcast,\n \t\t\t &cur_ps->eth.rx_broadcast);\n \n@@ -3324,109 +3324,109 @@ void ice_update_pf_stats(struct ice_pf *pf)\n \t\t\t &prev_ps->eth.rx_discards,\n \t\t\t &cur_ps->eth.rx_discards);\n \n-\tice_stat_update40(hw, GLPRT_GOTCL(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update40(hw, GLPRT_GOTCL(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->eth.tx_bytes,\n \t\t\t &cur_ps->eth.tx_bytes);\n \n-\tice_stat_update40(hw, GLPRT_UPTCL(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update40(hw, GLPRT_UPTCL(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->eth.tx_unicast,\n \t\t\t &cur_ps->eth.tx_unicast);\n \n-\tice_stat_update40(hw, GLPRT_MPTCL(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update40(hw, GLPRT_MPTCL(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->eth.tx_multicast,\n \t\t\t &cur_ps->eth.tx_multicast);\n \n-\tice_stat_update40(hw, GLPRT_BPTCL(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update40(hw, GLPRT_BPTCL(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->eth.tx_broadcast,\n \t\t\t &cur_ps->eth.tx_broadcast);\n \n-\tice_stat_update32(hw, GLPRT_TDOLD(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update32(hw, GLPRT_TDOLD(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->tx_dropped_link_down,\n \t\t\t &cur_ps->tx_dropped_link_down);\n \n-\tice_stat_update40(hw, GLPRT_PRC64L(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update40(hw, GLPRT_PRC64L(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->rx_size_64, &cur_ps->rx_size_64);\n \n-\tice_stat_update40(hw, GLPRT_PRC127L(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update40(hw, GLPRT_PRC127L(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->rx_size_127, &cur_ps->rx_size_127);\n \n-\tice_stat_update40(hw, GLPRT_PRC255L(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update40(hw, GLPRT_PRC255L(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->rx_size_255, &cur_ps->rx_size_255);\n \n-\tice_stat_update40(hw, GLPRT_PRC511L(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update40(hw, GLPRT_PRC511L(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->rx_size_511, &cur_ps->rx_size_511);\n \n-\tice_stat_update40(hw, GLPRT_PRC1023L(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update40(hw, GLPRT_PRC1023L(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->rx_size_1023, &cur_ps->rx_size_1023);\n \n-\tice_stat_update40(hw, GLPRT_PRC1522L(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update40(hw, GLPRT_PRC1522L(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->rx_size_1522, &cur_ps->rx_size_1522);\n \n-\tice_stat_update40(hw, GLPRT_PRC9522L(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update40(hw, GLPRT_PRC9522L(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->rx_size_big, &cur_ps->rx_size_big);\n \n-\tice_stat_update40(hw, GLPRT_PTC64L(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update40(hw, GLPRT_PTC64L(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->tx_size_64, &cur_ps->tx_size_64);\n \n-\tice_stat_update40(hw, GLPRT_PTC127L(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update40(hw, GLPRT_PTC127L(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->tx_size_127, &cur_ps->tx_size_127);\n \n-\tice_stat_update40(hw, GLPRT_PTC255L(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update40(hw, GLPRT_PTC255L(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->tx_size_255, &cur_ps->tx_size_255);\n \n-\tice_stat_update40(hw, GLPRT_PTC511L(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update40(hw, GLPRT_PTC511L(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->tx_size_511, &cur_ps->tx_size_511);\n \n-\tice_stat_update40(hw, GLPRT_PTC1023L(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update40(hw, GLPRT_PTC1023L(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->tx_size_1023, &cur_ps->tx_size_1023);\n \n-\tice_stat_update40(hw, GLPRT_PTC1522L(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update40(hw, GLPRT_PTC1522L(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->tx_size_1522, &cur_ps->tx_size_1522);\n \n-\tice_stat_update40(hw, GLPRT_PTC9522L(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update40(hw, GLPRT_PTC9522L(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->tx_size_big, &cur_ps->tx_size_big);\n \n-\tice_stat_update32(hw, GLPRT_LXONRXC(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update32(hw, GLPRT_LXONRXC(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->link_xon_rx, &cur_ps->link_xon_rx);\n \n-\tice_stat_update32(hw, GLPRT_LXOFFRXC(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update32(hw, GLPRT_LXOFFRXC(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->link_xoff_rx, &cur_ps->link_xoff_rx);\n \n-\tice_stat_update32(hw, GLPRT_LXONTXC(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update32(hw, GLPRT_LXONTXC(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->link_xon_tx, &cur_ps->link_xon_tx);\n \n-\tice_stat_update32(hw, GLPRT_LXOFFTXC(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update32(hw, GLPRT_LXOFFTXC(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->link_xoff_tx, &cur_ps->link_xoff_tx);\n \n \tice_update_dcb_stats(pf);\n \n-\tice_stat_update32(hw, GLPRT_CRCERRS(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update32(hw, GLPRT_CRCERRS(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->crc_errors, &cur_ps->crc_errors);\n \n-\tice_stat_update32(hw, GLPRT_ILLERRC(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update32(hw, GLPRT_ILLERRC(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->illegal_bytes, &cur_ps->illegal_bytes);\n \n-\tice_stat_update32(hw, GLPRT_MLFC(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update32(hw, GLPRT_MLFC(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->mac_local_faults,\n \t\t\t &cur_ps->mac_local_faults);\n \n-\tice_stat_update32(hw, GLPRT_MRFC(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update32(hw, GLPRT_MRFC(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->mac_remote_faults,\n \t\t\t &cur_ps->mac_remote_faults);\n \n-\tice_stat_update32(hw, GLPRT_RLEC(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update32(hw, GLPRT_RLEC(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->rx_len_errors, &cur_ps->rx_len_errors);\n \n-\tice_stat_update32(hw, GLPRT_RUC(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update32(hw, GLPRT_RUC(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->rx_undersize, &cur_ps->rx_undersize);\n \n-\tice_stat_update32(hw, GLPRT_RFC(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update32(hw, GLPRT_RFC(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->rx_fragments, &cur_ps->rx_fragments);\n \n-\tice_stat_update32(hw, GLPRT_ROC(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update32(hw, GLPRT_ROC(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->rx_oversize, &cur_ps->rx_oversize);\n \n-\tice_stat_update32(hw, GLPRT_RJC(pf_id), pf->stat_prev_loaded,\n+\tice_stat_update32(hw, GLPRT_RJC(port), pf->stat_prev_loaded,\n \t\t\t &prev_ps->rx_jabber, &cur_ps->rx_jabber);\n \n \tpf->stat_prev_loaded = true;\n", "prefixes": [ "S25", "04/12" ] }