Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/1137035/?format=api
{ "id": 1137035, "url": "http://patchwork.ozlabs.org/api/patches/1137035/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190725085541.55104-6-anthony.l.nguyen@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190725085541.55104-6-anthony.l.nguyen@intel.com>", "list_archive_url": null, "date": "2019-07-25T08:55:32", "name": "[S23,v4,06/15] ice: Set WB_ON_ITR when we don't re-enable interrupts", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "ec7255a5771f592d0346ed88ae5a525bfd3138c4", "submitter": { "id": 68875, "url": "http://patchwork.ozlabs.org/api/people/68875/?format=api", "name": "Tony Nguyen", "email": "anthony.l.nguyen@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190725085541.55104-6-anthony.l.nguyen@intel.com/mbox/", "series": [ { "id": 121506, "url": "http://patchwork.ozlabs.org/api/series/121506/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=121506", "date": "2019-07-25T08:55:36", "name": "[S23,v4,01/15] ice: Implement ethtool ops for channels", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/121506/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1137035/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1137035/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.138; helo=whitealder.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 45vfG46bD0z9sNF\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 26 Jul 2019 03:24:12 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id 80C82861A7;\n\tThu, 25 Jul 2019 17:24:11 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id WxYqWZWu-sz5; Thu, 25 Jul 2019 17:24:08 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id DCD9086F9E;\n\tThu, 25 Jul 2019 17:24:06 +0000 (UTC)", "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\tby ash.osuosl.org (Postfix) with ESMTP id 3F8D31BF312\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 25 Jul 2019 17:24:02 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 3D44E2044E\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 25 Jul 2019 17:24:02 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id ZUh+3sLt0iwP for <intel-wired-lan@lists.osuosl.org>;\n\tThu, 25 Jul 2019 17:24:00 +0000 (UTC)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n\tby silver.osuosl.org (Postfix) with ESMTPS id 15D7022658\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tThu, 25 Jul 2019 17:23:59 +0000 (UTC)", "from orsmga007.jf.intel.com ([10.7.209.58])\n\tby orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t25 Jul 2019 10:23:56 -0700", "from unknown (HELO localhost.jf.intel.com) ([10.166.244.174])\n\tby orsmga007.jf.intel.com with ESMTP; 25 Jul 2019 10:23:56 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,307,1559545200\"; d=\"scan'208\";a=\"160973707\"", "From": "Tony Nguyen <anthony.l.nguyen@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Thu, 25 Jul 2019 01:55:32 -0700", "Message-Id": "<20190725085541.55104-6-anthony.l.nguyen@intel.com>", "X-Mailer": "git-send-email 2.20.1", "In-Reply-To": "<20190725085541.55104-1-anthony.l.nguyen@intel.com>", "References": "<20190725085541.55104-1-anthony.l.nguyen@intel.com>", "MIME-Version": "1.0", "Subject": "[Intel-wired-lan] [PATCH S23 v4 06/15] ice: Set WB_ON_ITR when we\n\tdon't re-enable interrupts", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Brett Creeley <brett.creeley@intel.com>\n\nCurrently when busy polling is enabled we aren't setting/enabling\nWB_ON_ITR in the driver. This doesn't break the driver, but it does\ncause issues. If we don't enable WB_ON_ITR mode we will still get\nwrite-backs from hardware during polling when a cache line has been\nfilled, but if a cache line is not filled we will not get the\nwrite-back because WB_ON_ITR is not set. Fix this by enabling\nWB_ON_ITR in the driver when interrupts are disabled.\n\nSigned-off-by: Brett Creeley <brett.creeley@intel.com>\nSigned-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>\n---\nv3: Moved defines to group with similar registers\n---\n .../net/ethernet/intel/ice/ice_hw_autogen.h | 3 ++\n drivers/net/ethernet/intel/ice/ice_txrx.c | 54 +++++++++++++++++++\n drivers/net/ethernet/intel/ice/ice_txrx.h | 13 +++++\n 3 files changed, 70 insertions(+)", "diff": "diff --git a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\nindex 87652d722a30..6f78ff5534af 100644\n--- a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\n+++ b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\n@@ -127,8 +127,11 @@\n #define GLINT_DYN_CTL_CLEARPBA_M\t\tBIT(1)\n #define GLINT_DYN_CTL_SWINT_TRIG_M\t\tBIT(2)\n #define GLINT_DYN_CTL_ITR_INDX_S\t\t3\n+#define GLINT_DYN_CTL_ITR_INDX_M\t\tICE_M(0x3, 3)\n #define GLINT_DYN_CTL_INTERVAL_S\t\t5\n+#define GLINT_DYN_CTL_INTERVAL_M\t\tICE_M(0xFFF, 5)\n #define GLINT_DYN_CTL_SW_ITR_INDX_M\t\tICE_M(0x3, 25)\n+#define GLINT_DYN_CTL_WB_ON_ITR_M\t\tBIT(30)\n #define GLINT_DYN_CTL_INTENA_MSK_M\t\tBIT(31)\n #define GLINT_ITR(_i, _INT)\t\t\t(0x00154000 + ((_i) * 8192 + (_INT) * 4))\n #define GLINT_RATE(_INT)\t\t\t(0x0015A000 + ((_INT) * 4))\ndiff --git a/drivers/net/ethernet/intel/ice/ice_txrx.c b/drivers/net/ethernet/intel/ice/ice_txrx.c\nindex 5d2689956ade..9a54406922f0 100644\n--- a/drivers/net/ethernet/intel/ice/ice_txrx.c\n+++ b/drivers/net/ethernet/intel/ice/ice_txrx.c\n@@ -1356,6 +1356,23 @@ ice_update_ena_itr(struct ice_vsi *vsi, struct ice_q_vector *q_vector)\n \tstruct ice_ring_container *rx = &q_vector->rx;\n \tu32 itr_val;\n \n+\t/* when exiting WB_ON_ITR lets set a low ITR value and trigger\n+\t * interrupts to expire right away in case we have more work ready to go\n+\t * already\n+\t */\n+\tif (q_vector->itr_countdown == ICE_IN_WB_ON_ITR_MODE) {\n+\t\titr_val = ice_buildreg_itr(rx->itr_idx, ICE_WB_ON_ITR_USECS);\n+\t\twr32(&vsi->back->hw, GLINT_DYN_CTL(q_vector->reg_idx), itr_val);\n+\t\t/* set target back to last user set value */\n+\t\trx->target_itr = rx->itr_setting;\n+\t\t/* set current to what we just wrote and dynamic if needed */\n+\t\trx->current_itr = ICE_WB_ON_ITR_USECS |\n+\t\t\t(rx->itr_setting & ICE_ITR_DYNAMIC);\n+\t\t/* allow normal interrupt flow to start */\n+\t\tq_vector->itr_countdown = 0;\n+\t\treturn;\n+\t}\n+\n \t/* This will do nothing if dynamic updates are not enabled */\n \tice_update_itr(q_vector, tx);\n \tice_update_itr(q_vector, rx);\n@@ -1400,6 +1417,41 @@ ice_update_ena_itr(struct ice_vsi *vsi, struct ice_q_vector *q_vector)\n \t\t itr_val);\n }\n \n+/**\n+ * ice_set_wb_on_itr - set WB_ON_ITR for this q_vector\n+ * @vsi: pointer to the VSI structure\n+ * @q_vector: q_vector to set WB_ON_ITR on\n+ *\n+ * We need to tell hardware to write-back completed descriptors even when\n+ * interrupts are disabled. Descriptors will be written back on cache line\n+ * boundaries without WB_ON_ITR enabled, but if we don't enable WB_ON_ITR\n+ * descriptors may not be written back if they don't fill a cache line until the\n+ * next interrupt.\n+ *\n+ * This sets the write-back frequency to 2 microseconds as that is the minimum\n+ * value that's not 0 due to ITR granularity. Also, set the INTENA_MSK bit to\n+ * make sure hardware knows we aren't meddling with the INTENA_M bit.\n+ */\n+static void\n+ice_set_wb_on_itr(struct ice_vsi *vsi, struct ice_q_vector *q_vector)\n+{\n+\t/* already in WB_ON_ITR mode no need to change it */\n+\tif (q_vector->itr_countdown == ICE_IN_WB_ON_ITR_MODE)\n+\t\treturn;\n+\n+\tif (q_vector->num_ring_rx)\n+\t\twr32(&vsi->back->hw, GLINT_DYN_CTL(q_vector->reg_idx),\n+\t\t ICE_GLINT_DYN_CTL_WB_ON_ITR(ICE_WB_ON_ITR_USECS,\n+\t\t\t\t\t\t ICE_RX_ITR));\n+\n+\tif (q_vector->num_ring_tx)\n+\t\twr32(&vsi->back->hw, GLINT_DYN_CTL(q_vector->reg_idx),\n+\t\t ICE_GLINT_DYN_CTL_WB_ON_ITR(ICE_WB_ON_ITR_USECS,\n+\t\t\t\t\t\t ICE_TX_ITR));\n+\n+\tq_vector->itr_countdown = ICE_IN_WB_ON_ITR_MODE;\n+}\n+\n /**\n * ice_napi_poll - NAPI polling Rx/Tx cleanup routine\n * @napi: napi struct with our devices info in it\n@@ -1460,6 +1512,8 @@ int ice_napi_poll(struct napi_struct *napi, int budget)\n \t */\n \tif (likely(napi_complete_done(napi, work_done)))\n \t\tice_update_ena_itr(vsi, q_vector);\n+\telse\n+\t\tice_set_wb_on_itr(vsi, q_vector);\n \n \treturn min_t(int, work_done, budget - 1);\n }\ndiff --git a/drivers/net/ethernet/intel/ice/ice_txrx.h b/drivers/net/ethernet/intel/ice/ice_txrx.h\nindex ec76aba347b9..94a9280193e2 100644\n--- a/drivers/net/ethernet/intel/ice/ice_txrx.h\n+++ b/drivers/net/ethernet/intel/ice/ice_txrx.h\n@@ -144,6 +144,19 @@ enum ice_rx_dtype {\n #define ICE_DFLT_INTRL\t0\n #define ICE_MAX_INTRL\t236\n \n+#define ICE_WB_ON_ITR_USECS\t2\n+#define ICE_IN_WB_ON_ITR_MODE\t255\n+/* Sets WB_ON_ITR and assumes INTENA bit is already cleared, which allows\n+ * setting the MSK_M bit to tell hardware to ignore the INTENA_M bit. Also,\n+ * set the write-back latency to the usecs passed in.\n+ */\n+#define ICE_GLINT_DYN_CTL_WB_ON_ITR(usecs, itr_idx)\t\\\n+\t((((usecs) << (GLINT_DYN_CTL_INTERVAL_S - ICE_ITR_GRAN_S)) & \\\n+\t GLINT_DYN_CTL_INTERVAL_M) | \\\n+\t (((itr_idx) << GLINT_DYN_CTL_ITR_INDX_S) & \\\n+\t GLINT_DYN_CTL_ITR_INDX_M) | GLINT_DYN_CTL_INTENA_MSK_M | \\\n+\t GLINT_DYN_CTL_WB_ON_ITR_M)\n+\n /* Legacy or Advanced Mode Queue */\n #define ICE_TX_ADVANCED\t0\n #define ICE_TX_LEGACY\t1\n", "prefixes": [ "S23", "v4", "06/15" ] }