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GET /api/patches/1135860/?format=api
{ "id": 1135860, "url": "http://patchwork.ozlabs.org/api/patches/1135860/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190723100144.57435-1-alice.michael@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190723100144.57435-1-alice.michael@intel.com>", "list_archive_url": null, "date": "2019-07-23T10:01:33", "name": "[next,S8,01/12] i40e: fix shifts of signed values", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "84175ae3a30f29c8f4b8b5097ae2b212ea16202f", "submitter": { "id": 71123, "url": "http://patchwork.ozlabs.org/api/people/71123/?format=api", "name": "Michael, Alice", "email": "alice.michael@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190723100144.57435-1-alice.michael@intel.com/mbox/", "series": [ { "id": 121043, "url": "http://patchwork.ozlabs.org/api/series/121043/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=121043", "date": "2019-07-23T10:01:38", "name": "[next,S8,01/12] i40e: fix shifts of signed values", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/121043/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1135860/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1135860/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.136; helo=silver.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 45tRfb3FTFz9sBt\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 24 Jul 2019 04:22:47 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 83099203EE;\n\tTue, 23 Jul 2019 18:22:45 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id nsvax+Nq1ZLj; Tue, 23 Jul 2019 18:22:41 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby silver.osuosl.org (Postfix) with ESMTP id 88F20203A6;\n\tTue, 23 Jul 2019 18:22:41 +0000 (UTC)", "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\tby ash.osuosl.org (Postfix) with ESMTP id 0BE2A1BF2A5\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 23 Jul 2019 18:22:40 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 091B485AE9\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 23 Jul 2019 18:22:40 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id 8wMCnDJub50X for <intel-wired-lan@lists.osuosl.org>;\n\tTue, 23 Jul 2019 18:22:39 +0000 (UTC)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n\tby fraxinus.osuosl.org (Postfix) with ESMTPS id 37701857D8\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tTue, 23 Jul 2019 18:22:39 +0000 (UTC)", "from orsmga003.jf.intel.com ([10.7.209.27])\n\tby orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t23 Jul 2019 11:22:37 -0700", "from alicemic-1.jf.intel.com ([10.166.17.62])\n\tby orsmga003.jf.intel.com with ESMTP; 23 Jul 2019 11:22:35 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,299,1559545200\"; d=\"scan'208\";a=\"172037669\"", "From": "Alice Michael <alice.michael@intel.com>", "To": "alice.michael@intel.com,\n\tintel-wired-lan@lists.osuosl.org", "Date": "Tue, 23 Jul 2019 06:01:33 -0400", "Message-Id": "<20190723100144.57435-1-alice.michael@intel.com>", "X-Mailer": "git-send-email 2.21.0", "MIME-Version": "1.0", "Subject": "[Intel-wired-lan] [next PATCH S8 01/12] i40e: fix shifts of signed\n\tvalues", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Cc": "Beilei Xing <beilei.xing@intel.com>,\n\tFerruh Yigit <ferruh.yigit@intel.com>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Beilei Xing <beilei.xing@intel.com>\n\nThis patch fixes following error reported by cppcheck:\n(error) Shifting signed 32-bit value by 31 bits is undefined behaviour\n\nSigned-off-by: Ferruh Yigit <ferruh.yigit@intel.com>\n---\n .../net/ethernet/intel/i40e/i40e_register.h | 24 +++++++++----------\n 1 file changed, 12 insertions(+), 12 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/i40e/i40e_register.h b/drivers/net/ethernet/intel/i40e/i40e_register.h\nindex 52e3680c57f8..330ac19a5dae 100644\n--- a/drivers/net/ethernet/intel/i40e/i40e_register.h\n+++ b/drivers/net/ethernet/intel/i40e/i40e_register.h\n@@ -58,7 +58,7 @@\n #define I40E_PF_ARQLEN_ARQCRIT_SHIFT 30\n #define I40E_PF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQCRIT_SHIFT)\n #define I40E_PF_ARQLEN_ARQENABLE_SHIFT 31\n-#define I40E_PF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1, I40E_PF_ARQLEN_ARQENABLE_SHIFT)\n+#define I40E_PF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ARQLEN_ARQENABLE_SHIFT)\n #define I40E_PF_ARQT 0x00080480 /* Reset: EMPR */\n #define I40E_PF_ARQT_ARQT_SHIFT 0\n #define I40E_PF_ARQT_ARQT_MASK I40E_MASK(0x3FF, I40E_PF_ARQT_ARQT_SHIFT)\n@@ -81,7 +81,7 @@\n #define I40E_PF_ATQLEN_ATQCRIT_SHIFT 30\n #define I40E_PF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQCRIT_SHIFT)\n #define I40E_PF_ATQLEN_ATQENABLE_SHIFT 31\n-#define I40E_PF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_PF_ATQLEN_ATQENABLE_SHIFT)\n+#define I40E_PF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1u, I40E_PF_ATQLEN_ATQENABLE_SHIFT)\n #define I40E_PF_ATQT 0x00080400 /* Reset: EMPR */\n #define I40E_PF_ATQT_ATQT_SHIFT 0\n #define I40E_PF_ATQT_ATQT_MASK I40E_MASK(0x3FF, I40E_PF_ATQT_ATQT_SHIFT)\n@@ -108,7 +108,7 @@\n #define I40E_VF_ARQLEN_ARQCRIT_SHIFT 30\n #define I40E_VF_ARQLEN_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQCRIT_SHIFT)\n #define I40E_VF_ARQLEN_ARQENABLE_SHIFT 31\n-#define I40E_VF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN_ARQENABLE_SHIFT)\n+#define I40E_VF_ARQLEN_ARQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ARQLEN_ARQENABLE_SHIFT)\n #define I40E_VF_ARQT(_VF) (0x00082C00 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */\n #define I40E_VF_ARQT_MAX_INDEX 127\n #define I40E_VF_ARQT_ARQT_SHIFT 0\n@@ -136,7 +136,7 @@\n #define I40E_VF_ATQLEN_ATQCRIT_SHIFT 30\n #define I40E_VF_ATQLEN_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQCRIT_SHIFT)\n #define I40E_VF_ATQLEN_ATQENABLE_SHIFT 31\n-#define I40E_VF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN_ATQENABLE_SHIFT)\n+#define I40E_VF_ATQLEN_ATQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ATQLEN_ATQENABLE_SHIFT)\n #define I40E_VF_ATQT(_VF) (0x00082800 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: EMPR */\n #define I40E_VF_ATQT_MAX_INDEX 127\n #define I40E_VF_ATQT_ATQT_SHIFT 0\n@@ -259,7 +259,7 @@\n #define I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT 30\n #define I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT)\n #define I40E_PRTDCB_RETSTCC_ETSTC_SHIFT 31\n-#define I40E_PRTDCB_RETSTCC_ETSTC_MASK I40E_MASK(0x1, I40E_PRTDCB_RETSTCC_ETSTC_SHIFT)\n+#define I40E_PRTDCB_RETSTCC_ETSTC_MASK I40E_MASK(0x1u, I40E_PRTDCB_RETSTCC_ETSTC_SHIFT)\n #define I40E_PRTDCB_RPPMC 0x001223A0 /* Reset: CORER */\n #define I40E_PRTDCB_RPPMC_LANRPPM_SHIFT 0\n #define I40E_PRTDCB_RPPMC_LANRPPM_MASK I40E_MASK(0xFF, I40E_PRTDCB_RPPMC_LANRPPM_SHIFT)\n@@ -503,7 +503,7 @@\n #define I40E_GLGEN_MSCA_MDICMD_SHIFT 30\n #define I40E_GLGEN_MSCA_MDICMD_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDICMD_SHIFT)\n #define I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT 31\n-#define I40E_GLGEN_MSCA_MDIINPROGEN_MASK I40E_MASK(0x1, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT)\n+#define I40E_GLGEN_MSCA_MDIINPROGEN_MASK I40E_MASK(0x1u, I40E_GLGEN_MSCA_MDIINPROGEN_SHIFT)\n #define I40E_GLGEN_MSRWD(_i) (0x0008819C + ((_i) * 4)) /* _i=0...3 */ /* Reset: POR */\n #define I40E_GLGEN_MSRWD_MAX_INDEX 3\n #define I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT 0\n@@ -1242,14 +1242,14 @@\n #define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT 30\n #define I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_SET_QDIS_SHIFT)\n #define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT 31\n-#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK I40E_MASK(0x1, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT)\n+#define I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK I40E_MASK(0x1u, I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_SHIFT)\n #define I40E_PFLAN_QALLOC 0x001C0400 /* Reset: CORER */\n #define I40E_PFLAN_QALLOC_FIRSTQ_SHIFT 0\n #define I40E_PFLAN_QALLOC_FIRSTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_FIRSTQ_SHIFT)\n #define I40E_PFLAN_QALLOC_LASTQ_SHIFT 16\n #define I40E_PFLAN_QALLOC_LASTQ_MASK I40E_MASK(0x7FF, I40E_PFLAN_QALLOC_LASTQ_SHIFT)\n #define I40E_PFLAN_QALLOC_VALID_SHIFT 31\n-#define I40E_PFLAN_QALLOC_VALID_MASK I40E_MASK(0x1, I40E_PFLAN_QALLOC_VALID_SHIFT)\n+#define I40E_PFLAN_QALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PFLAN_QALLOC_VALID_SHIFT)\n #define I40E_QRX_ENA(_Q) (0x00120000 + ((_Q) * 4)) /* _i=0...1535 */ /* Reset: PFR */\n #define I40E_QRX_ENA_MAX_INDEX 1535\n #define I40E_QRX_ENA_QENA_REQ_SHIFT 0\n@@ -1658,7 +1658,7 @@\n #define I40E_GLNVM_SRCTL_START_SHIFT 30\n #define I40E_GLNVM_SRCTL_START_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_START_SHIFT)\n #define I40E_GLNVM_SRCTL_DONE_SHIFT 31\n-#define I40E_GLNVM_SRCTL_DONE_MASK I40E_MASK(0x1, I40E_GLNVM_SRCTL_DONE_SHIFT)\n+#define I40E_GLNVM_SRCTL_DONE_MASK I40E_MASK(0x1u, I40E_GLNVM_SRCTL_DONE_SHIFT)\n #define I40E_GLNVM_SRDATA 0x000B6114 /* Reset: POR */\n #define I40E_GLNVM_SRDATA_WRDATA_SHIFT 0\n #define I40E_GLNVM_SRDATA_WRDATA_MASK I40E_MASK(0xFFFF, I40E_GLNVM_SRDATA_WRDATA_SHIFT)\n@@ -3025,7 +3025,7 @@\n #define I40E_PF_VT_PFALLOC_LASTVF_SHIFT 8\n #define I40E_PF_VT_PFALLOC_LASTVF_MASK I40E_MASK(0xFF, I40E_PF_VT_PFALLOC_LASTVF_SHIFT)\n #define I40E_PF_VT_PFALLOC_VALID_SHIFT 31\n-#define I40E_PF_VT_PFALLOC_VALID_MASK I40E_MASK(0x1, I40E_PF_VT_PFALLOC_VALID_SHIFT)\n+#define I40E_PF_VT_PFALLOC_VALID_MASK I40E_MASK(0x1u, I40E_PF_VT_PFALLOC_VALID_SHIFT)\n #define I40E_VP_MDET_RX(_VF) (0x0012A000 + ((_VF) * 4)) /* _i=0...127 */ /* Reset: CORER */\n #define I40E_VP_MDET_RX_MAX_INDEX 127\n #define I40E_VP_MDET_RX_VALID_SHIFT 0\n@@ -3161,7 +3161,7 @@\n #define I40E_VF_ARQLEN1_ARQCRIT_SHIFT 30\n #define I40E_VF_ARQLEN1_ARQCRIT_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQCRIT_SHIFT)\n #define I40E_VF_ARQLEN1_ARQENABLE_SHIFT 31\n-#define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1, I40E_VF_ARQLEN1_ARQENABLE_SHIFT)\n+#define I40E_VF_ARQLEN1_ARQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ARQLEN1_ARQENABLE_SHIFT)\n #define I40E_VF_ARQT1 0x00007000 /* Reset: EMPR */\n #define I40E_VF_ARQT1_ARQT_SHIFT 0\n #define I40E_VF_ARQT1_ARQT_MASK I40E_MASK(0x3FF, I40E_VF_ARQT1_ARQT_SHIFT)\n@@ -3184,7 +3184,7 @@\n #define I40E_VF_ATQLEN1_ATQCRIT_SHIFT 30\n #define I40E_VF_ATQLEN1_ATQCRIT_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQCRIT_SHIFT)\n #define I40E_VF_ATQLEN1_ATQENABLE_SHIFT 31\n-#define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1, I40E_VF_ATQLEN1_ATQENABLE_SHIFT)\n+#define I40E_VF_ATQLEN1_ATQENABLE_MASK I40E_MASK(0x1u, I40E_VF_ATQLEN1_ATQENABLE_SHIFT)\n #define I40E_VF_ATQT1 0x00008400 /* Reset: EMPR */\n #define I40E_VF_ATQT1_ATQT_SHIFT 0\n #define I40E_VF_ATQT1_ATQT_MASK I40E_MASK(0x3FF, I40E_VF_ATQT1_ATQT_SHIFT)\n", "prefixes": [ "next", "S8", "01/12" ] }