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GET /api/patches/113576/?format=api
{ "id": 113576, "url": "http://patchwork.ozlabs.org/api/patches/113576/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1315322705-8388-3-git-send-email-aneesh@ti.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1315322705-8388-3-git-send-email-aneesh@ti.com>", "list_archive_url": null, "date": "2011-09-06T15:25:05", "name": "[U-Boot,v2,3/3] omap4: IO settings", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "5d480e3c09de24932c40a55921f18eb46c027121", "submitter": { "id": 6298, "url": "http://patchwork.ozlabs.org/api/people/6298/?format=api", "name": "Aneesh V", "email": "aneesh@ti.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1315322705-8388-3-git-send-email-aneesh@ti.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/113576/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/113576/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id A2633B6F68\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 7 Sep 2011 01:27:21 +1000 (EST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id BC980280C1;\n\tTue, 6 Sep 2011 17:27:14 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id TAFJ8QgmivBE; Tue, 6 Sep 2011 17:27:14 +0200 (CEST)", "from theia.denx.de (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 308A3280AC;\n\tTue, 6 Sep 2011 17:27:08 +0200 (CEST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id D07F6280AC\n\tfor <u-boot@lists.denx.de>; Tue, 6 Sep 2011 17:27:00 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id P+UoDER1urJ5 for <u-boot@lists.denx.de>;\n\tTue, 6 Sep 2011 17:26:56 +0200 (CEST)", "from comal.ext.ti.com (comal.ext.ti.com [198.47.26.152])\n\tby theia.denx.de (Postfix) with ESMTPS id 16EE7280A2\n\tfor <u-boot@lists.denx.de>; Tue, 6 Sep 2011 17:26:54 +0200 (CEST)", "from dbdp20.itg.ti.com ([172.24.170.38])\n\tby comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id p86FQnBK007177\n\t(version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO)\n\tfor <u-boot@lists.denx.de>; Tue, 6 Sep 2011 10:26:51 -0500", "from dbde70.ent.ti.com (localhost [127.0.0.1])\n\tby dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p86FQl8N004290\n\tfor <u-boot@lists.denx.de>; Tue, 6 Sep 2011 20:56:48 +0530 (IST)", "from dbdp31.itg.ti.com (172.24.170.98) by DBDE70.ent.ti.com\n\t(172.24.170.148) with Microsoft SMTP Server id 8.3.106.1;\n\tTue, 6 Sep 2011 20:56:48 +0530", "from localhost (a0393566pc.apr.dhcp.ti.com [172.24.137.55])\tby\n\tdbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p86FQlrb011995;\n\tTue, 6 Sep 2011 20:56:47 +0530 (IST)" ], "X-Virus-Scanned": [ "Debian amavisd-new at theia.denx.de", "Debian amavisd-new at theia.denx.de" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "From": "Aneesh V <aneesh@ti.com>", "To": "<u-boot@lists.denx.de>", "Date": "Tue, 6 Sep 2011 20:55:05 +0530", "Message-ID": "<1315322705-8388-3-git-send-email-aneesh@ti.com>", "X-Mailer": "git-send-email 1.7.0.4", "In-Reply-To": "<1312893821-29250-1-git-send-email-aneesh@ti.com>", "References": "<1312893821-29250-1-git-send-email-aneesh@ti.com>", "MIME-Version": "1.0", "Cc": "santosh.shilimkar@ti.com", "Subject": "[U-Boot] [PATCH v2 3/3] omap4: IO settings", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.9", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "u-boot-bounces@lists.denx.de", "Errors-To": "u-boot-bounces@lists.denx.de" }, "content": "Tuning some IO settings for better performance and power.\nAnd consolidate all such IO settings at one place.\n\nSigned-off-by: Aneesh V <aneesh@ti.com>\n---\nV2:\n* Add one more IO setting(in CONTROL_LPDDR2IOi_3) that was\n missing in the V1\n* Move all LPDDR2IO regs related defines to omap4.h from\n emif.h\n* Rebased on latest HEAD of u-boot-ti master\n---\n arch/arm/cpu/armv7/omap4/board.c | 61 +++++++++++++++++++++++++++++++\n arch/arm/cpu/armv7/omap4/emif.c | 25 -------------\n arch/arm/include/asm/arch-omap4/emif.h | 18 ---------\n arch/arm/include/asm/arch-omap4/omap4.h | 46 ++++++++++++++++++++++-\n 4 files changed, 105 insertions(+), 45 deletions(-)", "diff": "diff --git a/arch/arm/cpu/armv7/omap4/board.c b/arch/arm/cpu/armv7/omap4/board.c\nindex 69a0ce5..13ad654 100644\n--- a/arch/arm/cpu/armv7/omap4/board.c\n+++ b/arch/arm/cpu/armv7/omap4/board.c\n@@ -70,6 +70,66 @@ u32 omap_boot_mode(void)\n {\n \treturn omap4_boot_mode;\n }\n+\n+/*\n+ * Some tuning of IOs for optimal power and performance\n+ */\n+static void do_io_settings(void)\n+{\n+\tu32 lpddr2io;\n+\tstruct control_lpddr2io_regs *lpddr2io_regs =\n+\t\t(struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;\n+\tstruct omap4_sys_ctrl_regs *const ctrl =\n+\t\t(struct omap4_sys_ctrl_regs *)SYSCTRL_GENERAL_CORE_BASE;\n+\n+\tu32 omap4_rev = omap_revision();\n+\n+\tif (omap4_rev == OMAP4430_ES1_0)\n+\t\tlpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;\n+\telse if (omap4_rev == OMAP4430_ES2_0)\n+\t\tlpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;\n+\telse\n+\t\tlpddr2io = CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN;\n+\n+\twritel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);\n+\twritel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);\n+\t/* No pull for GR10 as per hw team's recommendation */\n+\twritel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,\n+\t\t&lpddr2io_regs->control_lpddr2io1_2);\n+\tclrbits_le32(&lpddr2io_regs->control_lpddr2io1_3,\n+\t\tLPDDR2_INT_VREF_EN_CA_MASK | LPDDR2_INT_VREF_EN_DQ_MASK);\n+\twritel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);\n+\twritel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);\n+\t/* No pull for GR10 as per hw team's recommendation */\n+\twritel(lpddr2io & ~LPDDR2IO_GR10_WD_MASK,\n+\t\t&lpddr2io_regs->control_lpddr2io2_2);\n+\tclrbits_le32(&lpddr2io_regs->control_lpddr2io2_3,\n+\t\tLPDDR2_INT_VREF_EN_CA_MASK | LPDDR2_INT_VREF_EN_DQ_MASK);\n+\n+\t/*\n+\t * Some of these settings (TRIM values) come from eFuse and are\n+\t * in turn programmed in the eFuse at manufacturing time after\n+\t * calibration of the device. Do the software over-ride only if\n+\t * the device is not correctly trimmed\n+\t */\n+\tif (!(readl(&ctrl->control_std_fuse_opp_bgap) & 0xFFFF)) {\n+\n+\t\twritel(LDOSRAM_VOLT_CTRL_OVERRIDE,\n+\t\t\t&ctrl->control_ldosram_iva_voltage_ctrl);\n+\n+\t\twritel(LDOSRAM_VOLT_CTRL_OVERRIDE,\n+\t\t\t&ctrl->control_ldosram_mpu_voltage_ctrl);\n+\n+\t\twritel(LDOSRAM_VOLT_CTRL_OVERRIDE,\n+\t\t\t&ctrl->control_ldosram_core_voltage_ctrl);\n+\t}\n+\n+\tif (!readl(&ctrl->control_efuse_1))\n+\t\twritel(CONTROL_EFUSE_1_OVERRIDE, &ctrl->control_efuse_1);\n+\n+\tif (!readl(&ctrl->control_efuse_2))\n+\t\twritel(CONTROL_EFUSE_2_OVERRIDE, &ctrl->control_efuse_2);\n+}\n #endif\n \n void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)\n@@ -197,6 +257,7 @@ void s_init(void)\n \tset_mux_conf_regs();\n #ifdef CONFIG_SPL_BUILD\n \tpreloader_console_init();\n+\tdo_io_settings();\n #endif\n \tprcm_init();\n #ifdef CONFIG_SPL_BUILD\ndiff --git a/arch/arm/cpu/armv7/omap4/emif.c b/arch/arm/cpu/armv7/omap4/emif.c\nindex 8c46464..988b205 100644\n--- a/arch/arm/cpu/armv7/omap4/emif.c\n+++ b/arch/arm/cpu/armv7/omap4/emif.c\n@@ -1063,30 +1063,6 @@ static void do_sdram_init(u32 base)\n \tdebug(\"<<do_sdram_init() %x\\n\", base);\n }\n \n-void sdram_init_pads(void)\n-{\n-\tu32 lpddr2io;\n-\tstruct control_lpddr2io_regs *lpddr2io_regs =\n-\t\t(struct control_lpddr2io_regs *)LPDDR2_IO_REGS_BASE;\n-\tu32 omap4_rev = omap_revision();\n-\n-\tif (omap4_rev == OMAP4430_ES1_0)\n-\t\tlpddr2io = CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN;\n-\telse if (omap4_rev == OMAP4430_ES2_0)\n-\t\tlpddr2io = CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER;\n-\telse\n-\t\treturn;\t\t/* Post ES2.1 reset values will work */\n-\n-\twritel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_0);\n-\twritel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_1);\n-\twritel(lpddr2io, &lpddr2io_regs->control_lpddr2io1_2);\n-\twritel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_0);\n-\twritel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_1);\n-\twritel(lpddr2io, &lpddr2io_regs->control_lpddr2io2_2);\n-\n-\twritel(CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1, CONTROL_EFUSE_2);\n-}\n-\n static void emif_post_init_config(u32 base)\n {\n \tstruct emif_reg_struct *emif = (struct emif_reg_struct *)base;\n@@ -1243,7 +1219,6 @@ void sdram_init(void)\n \tdebug(\"in_sdram = %d\\n\", in_sdram);\n \n \tif (!in_sdram) {\n-\t\tsdram_init_pads();\n \t\tbypass_dpll(&prcm->cm_clkmode_dpll_core);\n \t}\n \ndiff --git a/arch/arm/include/asm/arch-omap4/emif.h b/arch/arm/include/asm/arch-omap4/emif.h\nindex 6845c65..3a549ba 100644\n--- a/arch/arm/include/asm/arch-omap4/emif.h\n+++ b/arch/arm/include/asm/arch-omap4/emif.h\n@@ -593,17 +593,6 @@ struct dmm_lisa_map_regs {\n \tu32 dmm_lisa_map_3;\n };\n \n-struct control_lpddr2io_regs {\n-\tu32 control_lpddr2io1_0;\n-\tu32 control_lpddr2io1_1;\n-\tu32 control_lpddr2io1_2;\n-\tu32 control_lpddr2io1_3;\n-\tu32 control_lpddr2io2_0;\n-\tu32 control_lpddr2io2_1;\n-\tu32 control_lpddr2io2_2;\n-\tu32 control_lpddr2io2_3;\n-};\n-\n #define CS0\t0\n #define CS1\t1\n /* The maximum frequency at which the LPDDR2 interface can operate in Hz*/\n@@ -823,13 +812,6 @@ struct control_lpddr2io_regs {\n /* MR16 value: refresh full array(no partial array self refresh) */\n #define MR16_REF_FULL_ARRAY\t0\n \n-/* LPDDR2 IO regs */\n-#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN\t0x1C1C1C1C\n-#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER\t0x9E9E9E9E\n-\n-/* CONTROL_EFUSE_2 */\n-#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1\t\t0x00ffc000\n-\n /*\n * Maximum number of entries we keep in our array of timing tables\n * We need not keep all the speed bins supported by the device\ndiff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h\nindex 7ff46d7..6245017 100644\n--- a/arch/arm/include/asm/arch-omap4/omap4.h\n+++ b/arch/arm/include/asm/arch-omap4/omap4.h\n@@ -54,8 +54,6 @@\n /* LPDDR2 IO regs */\n #define LPDDR2_IO_REGS_BASE\t0x4A100638\n \n-#define CONTROL_EFUSE_2\t\t0x4A100704\n-\n /* CONTROL_ID_CODE */\n #define CONTROL_ID_CODE\t\t0x4A002204\n \n@@ -84,6 +82,9 @@\n /* GPMC */\n #define OMAP44XX_GPMC_BASE\t0x50000000\n \n+/* SYSTEM CONTROL MODULE */\n+#define SYSCTRL_GENERAL_CORE_BASE\t0x4A002000\n+\n /*\n * Hardware Register Details\n */\n@@ -108,6 +109,23 @@\n #define PRM_RSTCTRL\t\tPRM_DEVICE_BASE\n #define PRM_RSTCTRL_RESET\t0x01\n \n+/* Control Module */\n+#define LDOSRAM_ACTMODE_VSET_IN_MASK\t(0x1F << 5)\n+#define LDOSRAM_VOLT_CTRL_OVERRIDE\t0x0401040f\n+#define CONTROL_EFUSE_1_OVERRIDE\t0x1C4D0110\n+#define CONTROL_EFUSE_2_OVERRIDE\t0x00084000\n+\n+/* LPDDR2 IO regs */\n+#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN\t0x1C1C1C1C\n+#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER\t0x9E9E9E9E\n+#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN\t0x7C7C7C7C\n+#define LPDDR2IO_GR10_WD_MASK\t\t\t\t(3 << 17)\n+#define LPDDR2_INT_VREF_EN_CA_MASK\t0x8\n+#define LPDDR2_INT_VREF_EN_DQ_MASK\t0x4\n+\n+/* CONTROL_EFUSE_2 */\n+#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1\t\t0x00ffc000\n+\n #ifndef __ASSEMBLY__\n \n struct s32ktimer {\n@@ -115,6 +133,30 @@ struct s32ktimer {\n \tunsigned int s32k_cr;\t/* 0x10 */\n };\n \n+struct omap4_sys_ctrl_regs {\n+\tunsigned int pad1[129];\n+\tunsigned int control_id_code;\t\t\t/* 0x4A002204 */\n+\tunsigned int pad11[22];\n+\tunsigned int control_std_fuse_opp_bgap;\t\t/* 0x4a002260 */\n+\tunsigned int pad2[47];\n+\tunsigned int control_ldosram_iva_voltage_ctrl;\t/* 0x4A002320 */\n+\tunsigned int control_ldosram_mpu_voltage_ctrl;\t/* 0x4A002324 */\n+\tunsigned int control_ldosram_core_voltage_ctrl;\t/* 0x4A002328 */\n+\tunsigned int pad3[260341];\n+\tunsigned int control_efuse_1;\t\t\t/* 0x4A100700 */\n+\tunsigned int control_efuse_2;\t\t\t/* 0x4A100704 */\n+};\n+\n+struct control_lpddr2io_regs {\n+\tunsigned int control_lpddr2io1_0;\n+\tunsigned int control_lpddr2io1_1;\n+\tunsigned int control_lpddr2io1_2;\n+\tunsigned int control_lpddr2io1_3;\n+\tunsigned int control_lpddr2io2_0;\n+\tunsigned int control_lpddr2io2_1;\n+\tunsigned int control_lpddr2io2_2;\n+\tunsigned int control_lpddr2io2_3;\n+};\n #endif /* __ASSEMBLY__ */\n \n /*\n", "prefixes": [ "U-Boot", "v2", "3/3" ] }