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GET /api/patches/1132738/?format=api
{ "id": 1132738, "url": "http://patchwork.ozlabs.org/api/patches/1132738/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190716115745.12585-34-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190716115745.12585-34-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2019-07-16T11:57:21", "name": "[U-Boot,v3,33/57] ram: rk3399: Add IO settings", "commit_ref": "74109de3c2ff8beb9d0a311f1a0b26a715050c06", "pull_url": null, "state": "accepted", "archived": false, "hash": "e89e3ad1887b20bb662585df8c806f7f2842b8bb", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 93623, "url": "http://patchwork.ozlabs.org/api/users/93623/?format=api", "username": "kevery", "first_name": "Kever", "last_name": "Yang", "email": "ykai007@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190716115745.12585-34-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 119754, "url": "http://patchwork.ozlabs.org/api/series/119754/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=119754", "date": "2019-07-16T11:56:48", "name": "ram: rk3399: Add LPDDR4 support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/119754/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1132738/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1132738/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"j3b0/r3f\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 45p06j6ZtDz9s8m\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 16 Jul 2019 22:28:11 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid CF576C21EC3; Tue, 16 Jul 2019 12:08:04 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 61ADCC21DA1;\n\tTue, 16 Jul 2019 12:05:04 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid AFB60C21E1B; Tue, 16 Jul 2019 11:59:59 +0000 (UTC)", "from mail-pf1-f193.google.com (mail-pf1-f193.google.com\n\t[209.85.210.193])\n\tby lists.denx.de (Postfix) with ESMTPS id 7975EC21DAF\n\tfor <u-boot@lists.denx.de>; Tue, 16 Jul 2019 11:59:55 +0000 (UTC)", "by mail-pf1-f193.google.com with SMTP id i189so9007412pfg.10\n\tfor <u-boot@lists.denx.de>; Tue, 16 Jul 2019 04:59:55 -0700 (PDT)", "from localhost.localdomain ([49.206.201.107])\n\tby smtp.gmail.com with ESMTPSA id\n\tz24sm36269566pfr.51.2019.07.16.04.59.50\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tTue, 16 Jul 2019 04:59:53 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amarulasolutions.com; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=uemF/St7hQ0ruGO/Xb9kgNrdXpJ27IOAI3pTbvufdX4=;\n\tb=j3b0/r3fJIqwIJpEWJUZ3UR94SQv55eG8ceRyb6laZt6ya+EGTzE3ErNtGc/Maq9q0\n\tF3r2xulfi3IbVOZUJ+xtq1fn/fXXgqq3KMiQq2h1UuxNRh/uRntq/G/Y7Gks0CIPcQ/6\n\tDSZAGEnb6zJOMN5SkWpkGIWUGMcF07YvzSRUU=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=uemF/St7hQ0ruGO/Xb9kgNrdXpJ27IOAI3pTbvufdX4=;\n\tb=IZOX+xLms+V3q7KYvlzFxLGjsuTPKJVFjVrvWnClBNv4g5s4PveDJDGLVpAEVGrHYv\n\tW0wgDg/oEXh0VgooSvTh53R4tulD43lAwzHcwkV9wROPCyOg7pe0IAwpqj7vm+/e5r1R\n\t9WuxJ5THTCDwHGTpBW/9kfMVd/F49zsBDareIWXP8W8tVhU1U59M+jvT1a2yYxabYrV4\n\tZhnp955lHEzDjpDpnBwL7pj3uUSR3vSGAY6JP3hRiJ6YKEJRDtPfDN4YryGtwAtgLAuy\n\trYhdzDLvw9ul/emp2TpGEzPGs8IaqDjqZOvMGhm9onORPzwFNtrfIsWkkkjxsSUqJ3RG\n\tO7Sg==", "X-Gm-Message-State": "APjAAAW1fcvDSIF8NmuOgeHrlq34nHMjp8LnHM0qdgf2er4FbGlLpKV9\n\twfXb1GvCKm8oW19Wsm4Mj1qfZg==", "X-Google-Smtp-Source": "APXvYqyCHq9yhC5vjr4AGGJ/Avot/QTQqg8n4BT5/ppB7094ncIoaL4sD0/LwdgLPln/bPd2QmCUPA==", "X-Received": "by 2002:a17:90a:8d09:: with SMTP id\n\tc9mr36400136pjo.131.1563278394106; \n\tTue, 16 Jul 2019 04:59:54 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Simon Glass <sjg@chromium.org>,\n\tPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>,\n\tKever Yang <kever.yang@rock-chips.com>,\n\tYouMin Chen <cym@rock-chips.com>, u-boot@lists.denx.de", "Date": "Tue, 16 Jul 2019 17:27:21 +0530", "Message-Id": "<20190716115745.12585-34-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20190716115745.12585-1-jagan@amarulasolutions.com>", "References": "<20190716115745.12585-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com,\n\tlinux-amarula@amarulasolutions.com,\n\tManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>", "Subject": "[U-Boot] [PATCH v3 33/57] ram: rk3399: Add IO settings", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Add IO settings for dram ctl and phy.\n\nIO settings are useful for configuring ctl, phy odt, vref,\nmr5, mode select and other needed input output operations\nfor lpddr4 or any other dramtype sdram.\n\nRight now, this patch added IO setting for all supported\nsdram frequencies.\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\nSigned-off-by: YouMin Chen <cym@rock-chips.com>\n---\n drivers/ram/rockchip/sdram_rk3399.c | 104 ++++++++++++++++++++++++++++\n 1 file changed, 104 insertions(+)", "diff": "diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c\nindex 359ab0b826..95d9f3a88b 100644\n--- a/drivers/ram/rockchip/sdram_rk3399.c\n+++ b/drivers/ram/rockchip/sdram_rk3399.c\n@@ -80,6 +80,110 @@ struct rockchip_dmc_plat {\n \tstruct regmap *map;\n };\n \n+struct io_setting {\n+\tu32 mhz;\n+\tu32 mr5;\n+\t/* dram side */\n+\tu32 dq_odt;\n+\tu32 ca_odt;\n+\tu32 pdds;\n+\tu32 dq_vref;\n+\tu32 ca_vref;\n+\t/* phy side */\n+\tu32 rd_odt;\n+\tu32 wr_dq_drv;\n+\tu32 wr_ca_drv;\n+\tu32 wr_ckcs_drv;\n+\tu32 rd_odt_en;\n+\tu32 rd_vref;\n+} lpddr4_io_setting[] = {\n+\t{\n+\t\t50 * MHz,\n+\t\t0,\n+\t\t/* dram side */\n+\t\t0,\t/* dq_odt; */\n+\t\t0,\t/* ca_odt; */\n+\t\t6,\t/* pdds; */\n+\t\t0x72,\t/* dq_vref; */\n+\t\t0x72,\t/* ca_vref; */\n+\t\t/* phy side */\n+\t\tPHY_DRV_ODT_HI_Z,\t/* rd_odt; */\n+\t\tPHY_DRV_ODT_40,\t/* wr_dq_drv; */\n+\t\tPHY_DRV_ODT_40,\t/* wr_ca_drv; */\n+\t\tPHY_DRV_ODT_40,\t/* wr_ckcs_drv; */\n+\t\t0,\t/* rd_odt_en;*/\n+\t\t41,\t/* rd_vref; (unit %, range 3.3% - 48.7%) */\n+\t},\n+\t{\n+\t\t600 * MHz,\n+\t\t0,\n+\t\t/* dram side */\n+\t\t1,\t/* dq_odt; */\n+\t\t0,\t/* ca_odt; */\n+\t\t6,\t/* pdds; */\n+\t\t0x72,\t/* dq_vref; */\n+\t\t0x72,\t/* ca_vref; */\n+\t\t/* phy side */\n+\t\tPHY_DRV_ODT_HI_Z,\t/* rd_odt; */\n+\t\tPHY_DRV_ODT_48,\t/* wr_dq_drv; */\n+\t\tPHY_DRV_ODT_40,\t/* wr_ca_drv; */\n+\t\tPHY_DRV_ODT_40,\t/* wr_ckcs_drv; */\n+\t\t0,\t/* rd_odt_en; */\n+\t\t32,\t/* rd_vref; (unit %, range 3.3% - 48.7%) */\n+\t},\n+\t{\n+\t\t800 * MHz,\n+\t\t0,\n+\t\t/* dram side */\n+\t\t1,\t/* dq_odt; */\n+\t\t0,\t/* ca_odt; */\n+\t\t1,\t/* pdds; */\n+\t\t0x72,\t/* dq_vref; */\n+\t\t0x72,\t/* ca_vref; */\n+\t\t/* phy side */\n+\t\tPHY_DRV_ODT_40,\t/* rd_odt; */\n+\t\tPHY_DRV_ODT_48,\t/* wr_dq_drv; */\n+\t\tPHY_DRV_ODT_40,\t/* wr_ca_drv; */\n+\t\tPHY_DRV_ODT_40,\t/* wr_ckcs_drv; */\n+\t\t1,\t/* rd_odt_en; */\n+\t\t17,\t/* rd_vref; (unit %, range 3.3% - 48.7%) */\n+\t},\n+\t{\n+\t\t933 * MHz,\n+\t\t0,\n+\t\t/* dram side */\n+\t\t3,\t/* dq_odt; */\n+\t\t0,\t/* ca_odt; */\n+\t\t6,\t/* pdds; */\n+\t\t0x59,\t/* dq_vref; 32% */\n+\t\t0x72,\t/* ca_vref; */\n+\t\t/* phy side */\n+\t\tPHY_DRV_ODT_HI_Z,\t/* rd_odt; */\n+\t\tPHY_DRV_ODT_48,\t/* wr_dq_drv; */\n+\t\tPHY_DRV_ODT_40,\t/* wr_ca_drv; */\n+\t\tPHY_DRV_ODT_40,\t/* wr_ckcs_drv; */\n+\t\t0,\t/* rd_odt_en; */\n+\t\t32,\t/* rd_vref; (unit %, range 3.3% - 48.7%) */\n+\t},\n+\t{\n+\t\t1066 * MHz,\n+\t\t0,\n+\t\t/* dram side */\n+\t\t6,\t/* dq_odt; */\n+\t\t0,\t/* ca_odt; */\n+\t\t1,\t/* pdds; */\n+\t\t0x10,\t/* dq_vref; */\n+\t\t0x72,\t/* ca_vref; */\n+\t\t/* phy side */\n+\t\tPHY_DRV_ODT_40,\t/* rd_odt; */\n+\t\tPHY_DRV_ODT_60,\t/* wr_dq_drv; */\n+\t\tPHY_DRV_ODT_40,\t/* wr_ca_drv; */\n+\t\tPHY_DRV_ODT_40,\t/* wr_ckcs_drv; */\n+\t\t1,\t/* rd_odt_en; */\n+\t\t17,\t/* rd_vref; (unit %, range 3.3% - 48.7%) */\n+\t},\n+};\n+\n static void *get_ddrc0_con(struct dram_info *dram, u8 channel)\n {\n \treturn (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;\n", "prefixes": [ "U-Boot", "v3", "33/57" ] }