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GET /api/patches/1132732/?format=api
{ "id": 1132732, "url": "http://patchwork.ozlabs.org/api/patches/1132732/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190716115745.12585-33-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190716115745.12585-33-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2019-07-16T11:57:20", "name": "[U-Boot,v3,32/57] ram: rk3399: Don't disable dfi dram clk for lpddr4, rank 1", "commit_ref": "740409804e96bcc3411af66f5daa5914ff888638", "pull_url": null, "state": "accepted", "archived": false, "hash": "717455325efd3e7548b78bde81d2ff0b9576e012", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 93623, "url": "http://patchwork.ozlabs.org/api/users/93623/?format=api", "username": "kevery", "first_name": "Kever", "last_name": "Yang", "email": "ykai007@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190716115745.12585-33-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 119754, "url": "http://patchwork.ozlabs.org/api/series/119754/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=119754", "date": "2019-07-16T11:56:48", "name": "ram: rk3399: Add LPDDR4 support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/119754/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1132732/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1132732/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"j4Ku2On3\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 45p04w1zCNz9s8m\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 16 Jul 2019 22:26:39 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid B1B12C21E7F; Tue, 16 Jul 2019 12:04:33 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 626B9C21E52;\n\tTue, 16 Jul 2019 12:01:50 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid EBDF5C21E73; Tue, 16 Jul 2019 11:59:55 +0000 (UTC)", "from mail-pl1-f193.google.com (mail-pl1-f193.google.com\n\t[209.85.214.193])\n\tby lists.denx.de (Postfix) with ESMTPS id 93CC7C21DA6\n\tfor <u-boot@lists.denx.de>; Tue, 16 Jul 2019 11:59:51 +0000 (UTC)", "by mail-pl1-f193.google.com with SMTP id c2so9980529plz.13\n\tfor <u-boot@lists.denx.de>; Tue, 16 Jul 2019 04:59:51 -0700 (PDT)", "from localhost.localdomain ([49.206.201.107])\n\tby smtp.gmail.com with ESMTPSA id\n\tz24sm36269566pfr.51.2019.07.16.04.59.46\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tTue, 16 Jul 2019 04:59:49 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amarulasolutions.com; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=pRdXh1cKmOxDhyJeNVB4/lTa5Z+Y787ANmhkfv74kgk=;\n\tb=j4Ku2On3v4ATjaWeyCELDe8vaSZ0MB5LnP/OXq1YTZ7ALWO533ITcYIb9c1dp7eJA2\n\tw8TZZrCNE5foyALk8sNGKzKBafM7KfVKBNb/6LP78faveCPS6a+st2u/z0wxrCkig5L6\n\t1v1OfcZS9NSrIbWyk+yo1/gBaOBzR/jUvGXus=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=pRdXh1cKmOxDhyJeNVB4/lTa5Z+Y787ANmhkfv74kgk=;\n\tb=SGFPCm/FPZ8jF2aJiNK17yBti+QI3QH9sSddrZEluczix9r8lq1LLPZcyzPHzlqC28\n\tfUVX1YR/nhmKUPMzYXBwaH0B6eCs6PUvxeDImVsX9ZdPvixRutjVcYQjPM/ut0xLhbKw\n\tk7fOSnu23Yp1zQw7YqmO78ztYkKIbNLVKjA5o/2fTyZ5mPAUH3rOr0IZCrtIQrBA4KLl\n\tEBRJ/2gwmKZrYy93cpBn96SGYprWKHMb9AKzgkqOvm/LpFO4nniZiLLfKcRHoXpQ8CSz\n\tYXXK7pepkSsmlEGdmSnMPAs5uY7hZPMeYwKoiZ27R3CR2Jq6bPwt87fLSfLtApWbY4MK\n\tX2RQ==", "X-Gm-Message-State": "APjAAAUM0cu1LwonCpJwTHT5SH6RYvZHDD+mobxCn3+kvXfQyI9kJ5im\n\tyVEYiA2nmWIYubYM8mU3VmkTAQ==", "X-Google-Smtp-Source": "APXvYqwUcNB1whkCW1RL3Nkg1A+G3N5KFtkzy8Mp2jSshl6rtYK+2Fm+jUAf2Z9Z5/ez6BcFTOjrWA==", "X-Received": "by 2002:a17:902:7791:: with SMTP id\n\to17mr35240785pll.27.1563278390221; \n\tTue, 16 Jul 2019 04:59:50 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Simon Glass <sjg@chromium.org>,\n\tPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>,\n\tKever Yang <kever.yang@rock-chips.com>,\n\tYouMin Chen <cym@rock-chips.com>, u-boot@lists.denx.de", "Date": "Tue, 16 Jul 2019 17:27:20 +0530", "Message-Id": "<20190716115745.12585-33-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20190716115745.12585-1-jagan@amarulasolutions.com>", "References": "<20190716115745.12585-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com,\n\tlinux-amarula@amarulasolutions.com,\n\tManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>", "Subject": "[U-Boot] [PATCH v3 32/57] ram: rk3399: Don't disable dfi dram clk\n\tfor lpddr4, rank 1", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "The hardware for LPDDR4 with\n- CLK0P/N connect to lower 16-bits\n- CLK1P/N connect to higher 16-bits\n\nand usually dfi dram clk is configured via CLK1P/N, so\ndisabling dfi dram clk will disable the CLK1P/N as well.\n\nSo, add patch to not to disable dfi dram clk for lpddr4,\nwith rank 1.\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\nSigned-off-by: YouMin Chen <cym@rock-chips.com>\n---\n drivers/ram/rockchip/sdram_rk3399.c | 14 ++++++++++++--\n 1 file changed, 12 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c\nindex 1050cbdb07..359ab0b826 100644\n--- a/drivers/ram/rockchip/sdram_rk3399.c\n+++ b/drivers/ram/rockchip/sdram_rk3399.c\n@@ -1225,8 +1225,18 @@ static void dram_all_config(struct dram_info *dram,\n \t\twritel(noc_timing->ddrmode.d32,\n \t\t &ddr_msch_regs->ddrmode);\n \n-\t\t/* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */\n-\t\tif (params->ch[channel].cap_info.rank == 1)\n+\t\t/**\n+\t\t * rank 1 memory clock disable (dfi_dram_clk_disable = 1)\n+\t\t *\n+\t\t * The hardware for LPDDR4 with\n+\t\t * - CLK0P/N connect to lower 16-bits\n+\t\t * - CLK1P/N connect to higher 16-bits\n+\t\t *\n+\t\t * dfi dram clk is configured via CLK1P/N, so disabling\n+\t\t * dfi dram clk will disable the CLK1P/N as well for lpddr4.\n+\t\t */\n+\t\tif (params->ch[channel].cap_info.rank == 1 &&\n+\t\t params->base.dramtype != LPDDR4)\n \t\t\tsetbits_le32(&dram->chan[channel].pctl->denali_ctl[276],\n \t\t\t\t 1 << 17);\n \t}\n", "prefixes": [ "U-Boot", "v3", "32/57" ] }