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GET /api/patches/1132725/?format=api
{ "id": 1132725, "url": "http://patchwork.ozlabs.org/api/patches/1132725/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190716115745.12585-20-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190716115745.12585-20-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2019-07-16T11:57:07", "name": "[U-Boot,v3,19/57] ram: rk3399: Configure phy IO in ds odt", "commit_ref": "ba607fafd12e44735b6f3bc352b686101efc9155", "pull_url": null, "state": "accepted", "archived": false, "hash": "412aaa5c4bed7637fa49bdcfda57d4409af9e3ab", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 93623, "url": "http://patchwork.ozlabs.org/api/users/93623/?format=api", "username": "kevery", "first_name": "Kever", "last_name": "Yang", "email": "ykai007@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190716115745.12585-20-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 119754, "url": "http://patchwork.ozlabs.org/api/series/119754/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=119754", "date": "2019-07-16T11:56:48", "name": "ram: rk3399: Add LPDDR4 support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/119754/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1132725/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1132725/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"jCoUEpHv\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 45p01q4TbDz9s8m\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 16 Jul 2019 22:23:59 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 4D8E9C21C6A; Tue, 16 Jul 2019 12:02:51 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 011CCC21E1D;\n\tTue, 16 Jul 2019 12:00:50 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 143E4C21E35; Tue, 16 Jul 2019 11:59:09 +0000 (UTC)", "from mail-pf1-f196.google.com (mail-pf1-f196.google.com\n\t[209.85.210.196])\n\tby lists.denx.de (Postfix) with ESMTPS id 8542BC21E2B\n\tfor <u-boot@lists.denx.de>; Tue, 16 Jul 2019 11:59:05 +0000 (UTC)", "by mail-pf1-f196.google.com with SMTP id i189so9006332pfg.10\n\tfor <u-boot@lists.denx.de>; Tue, 16 Jul 2019 04:59:05 -0700 (PDT)", "from localhost.localdomain ([49.206.201.107])\n\tby smtp.gmail.com with ESMTPSA id\n\tz24sm36269566pfr.51.2019.07.16.04.59.00\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tTue, 16 Jul 2019 04:59:03 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amarulasolutions.com; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=iUvWjq1BPXXrVhqOCtmAWyZXv7hBktL59XaTbIUcq2E=;\n\tb=jCoUEpHvyUhyeuQ1U2+ghk5jkVXn6uuoM7ANq768bzrk0WmmKWT5R8uDLVqoYZ8djb\n\tKC9suSP0lU8yXk44FsKfz4bv0AITXGCMlKkqQ1XMLNro6jr522FcipbfkfY0/vv5DJFg\n\tVv1Skfe5EId/L56DTeYN5jN9Rf2y18FIDIGx0=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=iUvWjq1BPXXrVhqOCtmAWyZXv7hBktL59XaTbIUcq2E=;\n\tb=I7LWX97nfuV7SKe5VomOD4xz68B0dWCCm0Hl+Prg4CYP2CgbGdNHLAnUt6IDA/TJTJ\n\tFTyHt8jPOhWpCXYx1ipGzSZNd3CJPDV6mI65CEaJcQIzIjLKsU2kqCtN31DAADe/8IQk\n\tw2uiS+jm8WCkZqEaziUWslV/F1Xddpukae71Utk4ckvROJxZYuTbpw/CCtYmDUAxnPJG\n\taAFQ6HrinxVmbnuye+XuLhpZjKg6nFBFO0ZHvb835KcgrLwRAVcdZKM0RwjKKwZQFzjc\n\thZk3SrKmSzQGau6rEPKzVqnvFh2/OlXENXUWasj7zJ6kmRVtk4eQGg4RZhlUtAs4Glv7\n\tVQdQ==", "X-Gm-Message-State": "APjAAAW3o0HqoJjwRC5qGGVjSzr0Sd68f+aPUSlCLZ2q/5z2HKOCpFH2\n\tcxgl1k1ERVgjttHDJE48BjLxSw==", "X-Google-Smtp-Source": "APXvYqzZlFQu9pt5lTgpKzSyJ0BzroW2t95NOltGImVnHuaXoavw+kbtFE8QU+Y7K2PR6CpuqzyDVw==", "X-Received": "by 2002:a17:90a:8c0c:: with SMTP id\n\ta12mr35678317pjo.67.1563278344023; \n\tTue, 16 Jul 2019 04:59:04 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Simon Glass <sjg@chromium.org>,\n\tPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>,\n\tKever Yang <kever.yang@rock-chips.com>,\n\tYouMin Chen <cym@rock-chips.com>, u-boot@lists.denx.de", "Date": "Tue, 16 Jul 2019 17:27:07 +0530", "Message-Id": "<20190716115745.12585-20-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20190716115745.12585-1-jagan@amarulasolutions.com>", "References": "<20190716115745.12585-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com,\n\tlinux-amarula@amarulasolutions.com,\n\tManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>", "Subject": "[U-Boot] [PATCH v3 19/57] ram: rk3399: Configure phy IO in ds odt", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Some dramtypes like lpddr4 initialization would required to\nconfigure phy IO even after pctl_cfg and after set_ds_odt.\n\nFor those cases the set_ds_odt would be an initial call to\nsetup the phy.\n\nTo satisfy all the cases, trigger phy IO from set_ds_odt.\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\n---\n drivers/ram/rockchip/sdram_rk3399.c | 327 ++++++++++++++--------------\n 1 file changed, 162 insertions(+), 165 deletions(-)", "diff": "diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c\nindex e4723c7d59..a49677285d 100644\n--- a/drivers/ram/rockchip/sdram_rk3399.c\n+++ b/drivers/ram/rockchip/sdram_rk3399.c\n@@ -188,6 +188,166 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,\n \t\twritel(0x2EC7FFFF, &denali_pi[34]);\n }\n \n+static int phy_io_config(const struct chan_info *chan,\n+\t\t\t const struct rk3399_sdram_params *params)\n+{\n+\tu32 *denali_phy = chan->publ->denali_phy;\n+\tu32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;\n+\tu32 mode_sel;\n+\tu32 reg_value;\n+\tu32 drv_value, odt_value;\n+\tu32 speed;\n+\n+\t/* vref setting */\n+\tif (params->base.dramtype == LPDDR4) {\n+\t\t/* LPDDR4 */\n+\t\tvref_mode_dq = 0x6;\n+\t\tvref_value_dq = 0x1f;\n+\t\tvref_mode_ac = 0x6;\n+\t\tvref_value_ac = 0x1f;\n+\t} else if (params->base.dramtype == LPDDR3) {\n+\t\tif (params->base.odt == 1) {\n+\t\t\tvref_mode_dq = 0x5; /* LPDDR3 ODT */\n+\t\t\tdrv_value = (readl(&denali_phy[6]) >> 12) & 0xf;\n+\t\t\todt_value = (readl(&denali_phy[6]) >> 4) & 0xf;\n+\t\t\tif (drv_value == PHY_DRV_ODT_48) {\n+\t\t\t\tswitch (odt_value) {\n+\t\t\t\tcase PHY_DRV_ODT_240:\n+\t\t\t\t\tvref_value_dq = 0x16;\n+\t\t\t\t\tbreak;\n+\t\t\t\tcase PHY_DRV_ODT_120:\n+\t\t\t\t\tvref_value_dq = 0x26;\n+\t\t\t\t\tbreak;\n+\t\t\t\tcase PHY_DRV_ODT_60:\n+\t\t\t\t\tvref_value_dq = 0x36;\n+\t\t\t\t\tbreak;\n+\t\t\t\tdefault:\n+\t\t\t\t\tdebug(\"Invalid ODT value.\\n\");\n+\t\t\t\t\treturn -EINVAL;\n+\t\t\t\t}\n+\t\t\t} else if (drv_value == PHY_DRV_ODT_40) {\n+\t\t\t\tswitch (odt_value) {\n+\t\t\t\tcase PHY_DRV_ODT_240:\n+\t\t\t\t\tvref_value_dq = 0x19;\n+\t\t\t\t\tbreak;\n+\t\t\t\tcase PHY_DRV_ODT_120:\n+\t\t\t\t\tvref_value_dq = 0x23;\n+\t\t\t\t\tbreak;\n+\t\t\t\tcase PHY_DRV_ODT_60:\n+\t\t\t\t\tvref_value_dq = 0x31;\n+\t\t\t\t\tbreak;\n+\t\t\t\tdefault:\n+\t\t\t\t\tdebug(\"Invalid ODT value.\\n\");\n+\t\t\t\t\treturn -EINVAL;\n+\t\t\t\t}\n+\t\t\t} else if (drv_value == PHY_DRV_ODT_34_3) {\n+\t\t\t\tswitch (odt_value) {\n+\t\t\t\tcase PHY_DRV_ODT_240:\n+\t\t\t\t\tvref_value_dq = 0x17;\n+\t\t\t\t\tbreak;\n+\t\t\t\tcase PHY_DRV_ODT_120:\n+\t\t\t\t\tvref_value_dq = 0x20;\n+\t\t\t\t\tbreak;\n+\t\t\t\tcase PHY_DRV_ODT_60:\n+\t\t\t\t\tvref_value_dq = 0x2e;\n+\t\t\t\t\tbreak;\n+\t\t\t\tdefault:\n+\t\t\t\t\tdebug(\"Invalid ODT value.\\n\");\n+\t\t\t\t\treturn -EINVAL;\n+\t\t\t\t}\n+\t\t\t} else {\n+\t\t\t\tdebug(\"Invalid DRV value.\\n\");\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\t\t} else {\n+\t\t\tvref_mode_dq = 0x2; /* LPDDR3 */\n+\t\t\tvref_value_dq = 0x1f;\n+\t\t}\n+\t\tvref_mode_ac = 0x2;\n+\t\tvref_value_ac = 0x1f;\n+\t} else if (params->base.dramtype == DDR3) {\n+\t\t/* DDR3L */\n+\t\tvref_mode_dq = 0x1;\n+\t\tvref_value_dq = 0x1f;\n+\t\tvref_mode_ac = 0x1;\n+\t\tvref_value_ac = 0x1f;\n+\t} else {\n+\t\tdebug(\"Unknown DRAM type.\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\treg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;\n+\n+\t/* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */\n+\tclrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);\n+\t/* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */\n+\tclrsetbits_le32(&denali_phy[914], 0xfff, reg_value);\n+\t/* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */\n+\tclrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);\n+\t/* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */\n+\tclrsetbits_le32(&denali_phy[915], 0xfff, reg_value);\n+\n+\treg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;\n+\n+\t/* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */\n+\tclrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);\n+\n+\tif (params->base.dramtype == LPDDR4)\n+\t\tmode_sel = 0x6;\n+\telse if (params->base.dramtype == LPDDR3)\n+\t\tmode_sel = 0x0;\n+\telse if (params->base.dramtype == DDR3)\n+\t\tmode_sel = 0x1;\n+\telse\n+\t\treturn -EINVAL;\n+\n+\t/* PHY_924 PHY_PAD_FDBK_DRIVE */\n+\tclrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);\n+\t/* PHY_926 PHY_PAD_DATA_DRIVE */\n+\tclrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);\n+\t/* PHY_927 PHY_PAD_DQS_DRIVE */\n+\tclrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);\n+\t/* PHY_928 PHY_PAD_ADDR_DRIVE */\n+\tclrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);\n+\t/* PHY_929 PHY_PAD_CLK_DRIVE */\n+\tclrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);\n+\t/* PHY_935 PHY_PAD_CKE_DRIVE */\n+\tclrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);\n+\t/* PHY_937 PHY_PAD_RST_DRIVE */\n+\tclrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);\n+\t/* PHY_939 PHY_PAD_CS_DRIVE */\n+\tclrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);\n+\n+\t/* speed setting */\n+\tif (params->base.ddr_freq < 400)\n+\t\tspeed = 0x0;\n+\telse if (params->base.ddr_freq < 800)\n+\t\tspeed = 0x1;\n+\telse if (params->base.ddr_freq < 1200)\n+\t\tspeed = 0x2;\n+\telse\n+\t\tspeed = 0x3;\n+\n+\t/* PHY_924 PHY_PAD_FDBK_DRIVE */\n+\tclrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);\n+\t/* PHY_926 PHY_PAD_DATA_DRIVE */\n+\tclrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);\n+\t/* PHY_927 PHY_PAD_DQS_DRIVE */\n+\tclrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);\n+\t/* PHY_928 PHY_PAD_ADDR_DRIVE */\n+\tclrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);\n+\t/* PHY_929 PHY_PAD_CLK_DRIVE */\n+\tclrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);\n+\t/* PHY_935 PHY_PAD_CKE_DRIVE */\n+\tclrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);\n+\t/* PHY_937 PHY_PAD_RST_DRIVE */\n+\tclrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);\n+\t/* PHY_939 PHY_PAD_CS_DRIVE */\n+\tclrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);\n+\n+\treturn 0;\n+}\n+\n static void set_ds_odt(const struct chan_info *chan,\n \t\t const struct rk3399_sdram_params *params)\n {\n@@ -332,6 +492,8 @@ static void set_ds_odt(const struct chan_info *chan,\n \n \t/* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */\n \tclrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);\n+\n+\tphy_io_config(chan, params);\n }\n \n static void pctl_start(struct dram_info *dram, u8 channel)\n@@ -376,166 +538,6 @@ static void pctl_start(struct dram_info *dram, u8 channel)\n \t\t\tdram->pwrup_srefresh_exit[channel]);\n }\n \n-static int phy_io_config(const struct chan_info *chan,\n-\t\t\t const struct rk3399_sdram_params *params)\n-{\n-\tu32 *denali_phy = chan->publ->denali_phy;\n-\tu32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;\n-\tu32 mode_sel;\n-\tu32 reg_value;\n-\tu32 drv_value, odt_value;\n-\tu32 speed;\n-\n-\t/* vref setting */\n-\tif (params->base.dramtype == LPDDR4) {\n-\t\t/* LPDDR4 */\n-\t\tvref_mode_dq = 0x6;\n-\t\tvref_value_dq = 0x1f;\n-\t\tvref_mode_ac = 0x6;\n-\t\tvref_value_ac = 0x1f;\n-\t} else if (params->base.dramtype == LPDDR3) {\n-\t\tif (params->base.odt == 1) {\n-\t\t\tvref_mode_dq = 0x5; /* LPDDR3 ODT */\n-\t\t\tdrv_value = (readl(&denali_phy[6]) >> 12) & 0xf;\n-\t\t\todt_value = (readl(&denali_phy[6]) >> 4) & 0xf;\n-\t\t\tif (drv_value == PHY_DRV_ODT_48) {\n-\t\t\t\tswitch (odt_value) {\n-\t\t\t\tcase PHY_DRV_ODT_240:\n-\t\t\t\t\tvref_value_dq = 0x16;\n-\t\t\t\t\tbreak;\n-\t\t\t\tcase PHY_DRV_ODT_120:\n-\t\t\t\t\tvref_value_dq = 0x26;\n-\t\t\t\t\tbreak;\n-\t\t\t\tcase PHY_DRV_ODT_60:\n-\t\t\t\t\tvref_value_dq = 0x36;\n-\t\t\t\t\tbreak;\n-\t\t\t\tdefault:\n-\t\t\t\t\tdebug(\"Invalid ODT value.\\n\");\n-\t\t\t\t\treturn -EINVAL;\n-\t\t\t\t}\n-\t\t\t} else if (drv_value == PHY_DRV_ODT_40) {\n-\t\t\t\tswitch (odt_value) {\n-\t\t\t\tcase PHY_DRV_ODT_240:\n-\t\t\t\t\tvref_value_dq = 0x19;\n-\t\t\t\t\tbreak;\n-\t\t\t\tcase PHY_DRV_ODT_120:\n-\t\t\t\t\tvref_value_dq = 0x23;\n-\t\t\t\t\tbreak;\n-\t\t\t\tcase PHY_DRV_ODT_60:\n-\t\t\t\t\tvref_value_dq = 0x31;\n-\t\t\t\t\tbreak;\n-\t\t\t\tdefault:\n-\t\t\t\t\tdebug(\"Invalid ODT value.\\n\");\n-\t\t\t\t\treturn -EINVAL;\n-\t\t\t\t}\n-\t\t\t} else if (drv_value == PHY_DRV_ODT_34_3) {\n-\t\t\t\tswitch (odt_value) {\n-\t\t\t\tcase PHY_DRV_ODT_240:\n-\t\t\t\t\tvref_value_dq = 0x17;\n-\t\t\t\t\tbreak;\n-\t\t\t\tcase PHY_DRV_ODT_120:\n-\t\t\t\t\tvref_value_dq = 0x20;\n-\t\t\t\t\tbreak;\n-\t\t\t\tcase PHY_DRV_ODT_60:\n-\t\t\t\t\tvref_value_dq = 0x2e;\n-\t\t\t\t\tbreak;\n-\t\t\t\tdefault:\n-\t\t\t\t\tdebug(\"Invalid ODT value.\\n\");\n-\t\t\t\t\treturn -EINVAL;\n-\t\t\t\t}\n-\t\t\t} else {\n-\t\t\t\tdebug(\"Invalid DRV value.\\n\");\n-\t\t\t\treturn -EINVAL;\n-\t\t\t}\n-\t\t} else {\n-\t\t\tvref_mode_dq = 0x2; /* LPDDR3 */\n-\t\t\tvref_value_dq = 0x1f;\n-\t\t}\n-\t\tvref_mode_ac = 0x2;\n-\t\tvref_value_ac = 0x1f;\n-\t} else if (params->base.dramtype == DDR3) {\n-\t\t/* DDR3L */\n-\t\tvref_mode_dq = 0x1;\n-\t\tvref_value_dq = 0x1f;\n-\t\tvref_mode_ac = 0x1;\n-\t\tvref_value_ac = 0x1f;\n-\t} else {\n-\t\tdebug(\"Unknown DRAM type.\\n\");\n-\t\treturn -EINVAL;\n-\t}\n-\n-\treg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;\n-\n-\t/* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */\n-\tclrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);\n-\t/* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */\n-\tclrsetbits_le32(&denali_phy[914], 0xfff, reg_value);\n-\t/* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */\n-\tclrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);\n-\t/* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */\n-\tclrsetbits_le32(&denali_phy[915], 0xfff, reg_value);\n-\n-\treg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;\n-\n-\t/* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */\n-\tclrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);\n-\n-\tif (params->base.dramtype == LPDDR4)\n-\t\tmode_sel = 0x6;\n-\telse if (params->base.dramtype == LPDDR3)\n-\t\tmode_sel = 0x0;\n-\telse if (params->base.dramtype == DDR3)\n-\t\tmode_sel = 0x1;\n-\telse\n-\t\treturn -EINVAL;\n-\n-\t/* PHY_924 PHY_PAD_FDBK_DRIVE */\n-\tclrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);\n-\t/* PHY_926 PHY_PAD_DATA_DRIVE */\n-\tclrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);\n-\t/* PHY_927 PHY_PAD_DQS_DRIVE */\n-\tclrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);\n-\t/* PHY_928 PHY_PAD_ADDR_DRIVE */\n-\tclrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);\n-\t/* PHY_929 PHY_PAD_CLK_DRIVE */\n-\tclrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);\n-\t/* PHY_935 PHY_PAD_CKE_DRIVE */\n-\tclrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);\n-\t/* PHY_937 PHY_PAD_RST_DRIVE */\n-\tclrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);\n-\t/* PHY_939 PHY_PAD_CS_DRIVE */\n-\tclrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);\n-\n-\t/* speed setting */\n-\tif (params->base.ddr_freq < 400)\n-\t\tspeed = 0x0;\n-\telse if (params->base.ddr_freq < 800)\n-\t\tspeed = 0x1;\n-\telse if (params->base.ddr_freq < 1200)\n-\t\tspeed = 0x2;\n-\telse\n-\t\tspeed = 0x3;\n-\n-\t/* PHY_924 PHY_PAD_FDBK_DRIVE */\n-\tclrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);\n-\t/* PHY_926 PHY_PAD_DATA_DRIVE */\n-\tclrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);\n-\t/* PHY_927 PHY_PAD_DQS_DRIVE */\n-\tclrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);\n-\t/* PHY_928 PHY_PAD_ADDR_DRIVE */\n-\tclrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);\n-\t/* PHY_929 PHY_PAD_CLK_DRIVE */\n-\tclrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);\n-\t/* PHY_935 PHY_PAD_CKE_DRIVE */\n-\tclrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);\n-\t/* PHY_937 PHY_PAD_RST_DRIVE */\n-\tclrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);\n-\t/* PHY_939 PHY_PAD_CS_DRIVE */\n-\tclrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);\n-\n-\treturn 0;\n-}\n-\n static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,\n \t\t u32 channel, const struct rk3399_sdram_params *params)\n {\n@@ -545,7 +547,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,\n \tconst u32 *params_ctl = params->pctl_regs.denali_ctl;\n \tconst u32 *params_phy = params->phy_regs.denali_phy;\n \tu32 tmp, tmp1, tmp2;\n-\tint ret;\n \n \t/*\n \t * work around controller bug:\n@@ -623,10 +624,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,\n \ttmp = (readl(&denali_phy[467]) >> 16) & 0xff;\n \tclrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16);\n \n-\tret = phy_io_config(chan, params);\n-\tif (ret)\n-\t\treturn ret;\n-\n \treturn 0;\n }\n \n", "prefixes": [ "U-Boot", "v3", "19/57" ] }