Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/1132722/?format=api
{ "id": 1132722, "url": "http://patchwork.ozlabs.org/api/patches/1132722/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190716115745.12585-26-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190716115745.12585-26-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2019-07-16T11:57:13", "name": "[U-Boot,v3,25/57] ram: rk3399: Avoid two channel ZQ Cal Start at the same time", "commit_ref": "47627c8a5cfc0d5d60ca81446528705b3b56077b", "pull_url": null, "state": "accepted", "archived": false, "hash": "337e92b6827d87bbf4b973c8102528c844d5e163", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 93623, "url": "http://patchwork.ozlabs.org/api/users/93623/?format=api", "username": "kevery", "first_name": "Kever", "last_name": "Yang", "email": "ykai007@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190716115745.12585-26-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 119754, "url": "http://patchwork.ozlabs.org/api/series/119754/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=119754", "date": "2019-07-16T11:56:48", "name": "ram: rk3399: Add LPDDR4 support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/119754/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1132722/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1132722/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"A0wocJqo\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 45p00T6K30z9s3l\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 16 Jul 2019 22:22:49 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 87677C21C6A; Tue, 16 Jul 2019 12:03:11 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id C17FDC21E42;\n\tTue, 16 Jul 2019 12:00:52 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 4D75FC21DC1; Tue, 16 Jul 2019 11:59:30 +0000 (UTC)", "from mail-pl1-f195.google.com (mail-pl1-f195.google.com\n\t[209.85.214.195])\n\tby lists.denx.de (Postfix) with ESMTPS id 694D8C21D65\n\tfor <u-boot@lists.denx.de>; Tue, 16 Jul 2019 11:59:26 +0000 (UTC)", "by mail-pl1-f195.google.com with SMTP id 4so3043635pld.10\n\tfor <u-boot@lists.denx.de>; Tue, 16 Jul 2019 04:59:26 -0700 (PDT)", "from localhost.localdomain ([49.206.201.107])\n\tby smtp.gmail.com with ESMTPSA id\n\tz24sm36269566pfr.51.2019.07.16.04.59.21\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tTue, 16 Jul 2019 04:59:24 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amarulasolutions.com; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=Ytkg3u87YIDa47ShbV1haeOc0wg13Q/l2pqMvwhDtcY=;\n\tb=A0wocJqoUSHpz0XxE7jQIFT1oU4uexnHZcPfzIWGIw8QuJLI98W3rrdxJZeSVnyxUM\n\tAAJJ/ZVQs2prl9Co9HbQCZO2LdOf9YMLnFKHEBGuf0Q2Eapz/UX3mKI+n+u/Vdy73j/N\n\tFnML8piKVMNGwTNgOLvBQsdws4/aVxm4o0QIs=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=Ytkg3u87YIDa47ShbV1haeOc0wg13Q/l2pqMvwhDtcY=;\n\tb=XGnyFmf63a8nbJrWSCrqnfeePY7B1it3sDRFm18/CRMz91l+XAztVI/VpLr7BUQyyF\n\t+bA+IZQy+OhYSpQ94ywcK62hqY2BN13VuXeCUeVdYr2d+piqJa4CsMFYF+z/HSX7fC0k\n\ti11cgLqjKlxi2euootmZhMysKcyib1w/B40JXNphYjIXTEkdZ19l3YnN4zUusJnSAE4g\n\tZJCCA/aPBB8Yt469C+o6I7k83h8hbMGMy8VP3iU1Qzs+/Ba99KKVnVrrJaxtJAvpY1IQ\n\t+0EaWg9FhTvzLXbULU7nuPCBlUTmyVNIRg1PRdmYn4nwh+tiX/iyC1bLzYb35dFG3gKy\n\tyz/A==", "X-Gm-Message-State": "APjAAAV50U3j7c8d28J8hqizbPtOKLRS55OMrwYbLIt7VymZ5Af070lL\n\ta4s86LDTxkg6ohR3e5Tm2ETGrw==", "X-Google-Smtp-Source": "APXvYqytdvqF3efZKGu0paioQMVUdnaV66R5nTCO6ZkOw/KnwJUxduzojYumuTplMjzcO/JUpRuATg==", "X-Received": "by 2002:a17:902:54f:: with SMTP id\n\t73mr34128376plf.246.1563278365055; \n\tTue, 16 Jul 2019 04:59:25 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Simon Glass <sjg@chromium.org>,\n\tPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>,\n\tKever Yang <kever.yang@rock-chips.com>,\n\tYouMin Chen <cym@rock-chips.com>, u-boot@lists.denx.de", "Date": "Tue, 16 Jul 2019 17:27:13 +0530", "Message-Id": "<20190716115745.12585-26-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20190716115745.12585-1-jagan@amarulasolutions.com>", "References": "<20190716115745.12585-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com,\n\tlinux-amarula@amarulasolutions.com,\n\tManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>", "Subject": "[U-Boot] [PATCH v3 25/57] ram: rk3399: Avoid two channel ZQ Cal\n\tStart at the same time", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "It is possible in lpddr4 dram, where both the channels would\nstart at same time with ZQ Cal Start. If it uses ZQ Call start\nthen it will use RZQ.\n\nFor example LPDDR4 366 Dual-Die, Quad-Channel Package, RZQ maybe\nconnect to both channel. If ZQ Cal Start at the same time,\nit will use the same RZQ.\n\nIt is not a problem of using RZQ in both the channels, but can not\nuse at the same time.\n\nSo, to avoid this, we have an option of dram tINIT3 value for\nincreasing the frequency for channel 1.\n\nThis patch increase the available tINIT3 with existing running\ndram frequency.\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\nSigned-off-by: YouMin Chen <cym@rock-chips.com>\n---\n drivers/ram/rockchip/sdram_rk3399.c | 14 ++++++++++++++\n 1 file changed, 14 insertions(+)", "diff": "diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c\nindex 023838a301..beb4f6de54 100644\n--- a/drivers/ram/rockchip/sdram_rk3399.c\n+++ b/drivers/ram/rockchip/sdram_rk3399.c\n@@ -550,6 +550,20 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,\n \t\t sizeof(struct rk3399_ddr_pctl_regs) - 4);\n \twritel(params_ctl[0], &denali_ctl[0]);\n \n+\t/*\n+\t * two channel init at the same time, then ZQ Cal Start\n+\t * at the same time, it will use the same RZQ, but cannot\n+\t * start at the same time.\n+\t *\n+\t * So, increase tINIT3 for channel 1, will avoid two\n+\t * channel ZQ Cal Start at the same time\n+\t */\n+\tif (params->base.dramtype == LPDDR4 && channel == 1) {\n+\t\ttmp = ((params->base.ddr_freq * MHz + 999) / 1000);\n+\t\ttmp1 = readl(&denali_ctl[14]);\n+\t\twritel(tmp + tmp1, &denali_ctl[14]);\n+\t}\n+\n \tcopy_to_reg(denali_pi, ¶ms->pi_regs.denali_pi[0],\n \t\t sizeof(struct rk3399_ddr_pi_regs));\n \n", "prefixes": [ "U-Boot", "v3", "25/57" ] }