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GET /api/patches/1132720/?format=api
{ "id": 1132720, "url": "http://patchwork.ozlabs.org/api/patches/1132720/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190716115745.12585-39-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190716115745.12585-39-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2019-07-16T11:57:26", "name": "[U-Boot,v3,38/57] ram: rk3399: Update lpddr4 vref based on io settings", "commit_ref": "95be76eb5ce0d807d5b1b360efbac11f16a819af", "pull_url": null, "state": "accepted", "archived": false, "hash": "94cd3776cca02bdb7b2598cdbf8cd22c426d9760", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 93623, "url": "http://patchwork.ozlabs.org/api/users/93623/?format=api", "username": "kevery", "first_name": "Kever", "last_name": "Yang", "email": "ykai007@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190716115745.12585-39-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 119754, "url": "http://patchwork.ozlabs.org/api/series/119754/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=119754", "date": "2019-07-16T11:56:48", "name": "ram: rk3399: Add LPDDR4 support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/119754/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1132720/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1132720/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"kvnO2h2S\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 45p00B1pgRz9s3l\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 16 Jul 2019 22:22:34 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid E9364C21E52; Tue, 16 Jul 2019 12:12:48 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 46099C21E47;\n\tTue, 16 Jul 2019 12:09:29 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 2115DC21DA1; Tue, 16 Jul 2019 12:00:20 +0000 (UTC)", "from mail-pf1-f196.google.com (mail-pf1-f196.google.com\n\t[209.85.210.196])\n\tby lists.denx.de (Postfix) with ESMTPS id 23158C21E56\n\tfor <u-boot@lists.denx.de>; Tue, 16 Jul 2019 12:00:13 +0000 (UTC)", "by mail-pf1-f196.google.com with SMTP id 19so9012848pfa.4\n\tfor <u-boot@lists.denx.de>; Tue, 16 Jul 2019 05:00:13 -0700 (PDT)", "from localhost.localdomain ([49.206.201.107])\n\tby smtp.gmail.com with ESMTPSA id\n\tz24sm36269566pfr.51.2019.07.16.05.00.08\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tTue, 16 Jul 2019 05:00:11 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amarulasolutions.com; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=mh5Pf5jjoLLteLnqId9idbQ7tEs3dWgvjmHLOwZoIVk=;\n\tb=kvnO2h2SUjTqjxvSjusn4drwayoMc3XJayHc0h5Qs6ytAeZ/qb+meEseCezLsJoWSU\n\te/Vi+dGtdVCpXM89e3SSkFngDDRx2KlAWxAWNtSEzYS2g/zxBfQzwk6C/xuWK26cH67r\n\tLAPXFCt8Qapfqcm/5kBTITD3+1xkgopkA1ls8=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=mh5Pf5jjoLLteLnqId9idbQ7tEs3dWgvjmHLOwZoIVk=;\n\tb=imqSwAFam1xZEgW0fc60W1PGCahvf098qx4MLa5Q/CJHJIeVUodI45iotwYk8gSaIf\n\tf9vuUtc90NRcdA9QS3MrnQrPosj9vZs8zVvX226ZYjZ6Zmtzgx4AJDQ8l9kB4LZs/P/H\n\t+06EAJkFuy1SZVmK4Qn5Aed5ZKyzeTUPGfCyptr4Qp/+/YBGlre29yk5W7mYvvSuyuRW\n\tb1Warnb/yOfD9uuhg8dB0ugKVtq+Kk4eFpQJkR/qjxc+pHsLnObh94HIXYj8u6/RU/e4\n\tA8RkOUiF8h4sjZFBeobCg8z1feZ/sKf87/pP6nnQpdf4HJxHoQRvZacip1F5nJMlhlwq\n\tpCzg==", "X-Gm-Message-State": "APjAAAUn7XIaXYmWoXEK16Rfa1KkmGWiZN+elMI/VOL95aCZSzPr9XBf\n\t5tu9OW5xiDQADxsiS7PU6/s/4A==", "X-Google-Smtp-Source": "APXvYqyI82mkiX+yz4dw3lVtY/ozuKpAe3mzNw41moz/e3TvONjc4c+W2OayNzAxjCXp8s1NS7yqJg==", "X-Received": "by 2002:a63:2606:: with SMTP id\n\tm6mr32928694pgm.436.1563278411660; \n\tTue, 16 Jul 2019 05:00:11 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Simon Glass <sjg@chromium.org>,\n\tPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>,\n\tKever Yang <kever.yang@rock-chips.com>,\n\tYouMin Chen <cym@rock-chips.com>, u-boot@lists.denx.de", "Date": "Tue, 16 Jul 2019 17:27:26 +0530", "Message-Id": "<20190716115745.12585-39-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20190716115745.12585-1-jagan@amarulasolutions.com>", "References": "<20190716115745.12585-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com,\n\tlinux-amarula@amarulasolutions.com,\n\tManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>", "Subject": "[U-Boot] [PATCH v3 38/57] ram: rk3399: Update lpddr4 vref based on\n\tio settings", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "The vref_mode_dq, vref_value_dq on lpddr4 value is depending\non IO settings of rd_vref.\n\nAdd support for it.\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\nSigned-off-by: YouMin Chen <cym@rock-chips.com>\n---\n drivers/ram/rockchip/sdram_rk3399.c | 19 ++++++++++++++-----\n 1 file changed, 14 insertions(+), 5 deletions(-)", "diff": "diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c\nindex 9e40880835..4a2622a440 100644\n--- a/drivers/ram/rockchip/sdram_rk3399.c\n+++ b/drivers/ram/rockchip/sdram_rk3399.c\n@@ -338,7 +338,7 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,\n }\n \n static int phy_io_config(const struct chan_info *chan,\n-\t\t\t const struct rk3399_sdram_params *params)\n+\t\t\t const struct rk3399_sdram_params *params, u32 mr5)\n {\n \tu32 *denali_phy = chan->publ->denali_phy;\n \tu32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;\n@@ -349,9 +349,18 @@ static int phy_io_config(const struct chan_info *chan,\n \n \t/* vref setting */\n \tif (params->base.dramtype == LPDDR4) {\n-\t\t/* LPDDR4 */\n-\t\tvref_mode_dq = 0x6;\n-\t\tvref_value_dq = 0x1f;\n+\t\tstruct io_setting *io = lpddr4_get_io_settings(params, mr5);\n+\t\tu32 rd_vref = io->rd_vref * 1000;\n+\n+\t\tif (rd_vref < 36700) {\n+\t\t\t/* MODE_LV[2:0] = LPDDR4 (Range 2)*/\n+\t\t\tvref_mode_dq = 0x7;\n+\t\t\tvref_value_dq = (rd_vref - 3300) / 521;\n+\t\t} else {\n+\t\t\t/* MODE_LV[2:0] = LPDDR4 (Range 1)*/\n+\t\t\tvref_mode_dq = 0x6;\n+\t\t\tvref_value_dq = (rd_vref - 15300) / 521;\n+\t\t}\n \t\tvref_mode_ac = 0x6;\n \t\tvref_value_ac = 0x1f;\n \t\tmode_sel = 0x6;\n@@ -770,7 +779,7 @@ static void set_ds_odt(const struct chan_info *chan,\n \t/* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */\n \tclrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);\n \n-\tphy_io_config(chan, params);\n+\tphy_io_config(chan, params, mr5);\n }\n \n static void pctl_start(struct dram_info *dram, u8 channel)\n", "prefixes": [ "U-Boot", "v3", "38/57" ] }