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GET /api/patches/1132714/?format=api
{ "id": 1132714, "url": "http://patchwork.ozlabs.org/api/patches/1132714/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190716115745.12585-25-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190716115745.12585-25-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2019-07-16T11:57:12", "name": "[U-Boot,v3,24/57] ram: rk3399: Don't wait for PLL lock in lpddr4", "commit_ref": "5cbc8669819a69c22a50d2fb22c9d4962c8bbad5", "pull_url": null, "state": "accepted", "archived": false, "hash": "8c3654f7b1892a201c67afb3f993fb01b198b7ce", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 93623, "url": "http://patchwork.ozlabs.org/api/users/93623/?format=api", "username": "kevery", "first_name": "Kever", "last_name": "Yang", "email": "ykai007@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190716115745.12585-25-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 119754, "url": "http://patchwork.ozlabs.org/api/series/119754/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=119754", "date": "2019-07-16T11:56:48", "name": "ram: rk3399: Add LPDDR4 support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/119754/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1132714/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1132714/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"G9GmkIyM\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 45nzxD6mkrz9s3l\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 16 Jul 2019 22:20:00 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 8CC3CC21DA1; Tue, 16 Jul 2019 12:08:30 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 184A6C21C6A;\n\tTue, 16 Jul 2019 12:05:36 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid BC7B8C21DC1; Tue, 16 Jul 2019 11:59:26 +0000 (UTC)", "from mail-pl1-f195.google.com (mail-pl1-f195.google.com\n\t[209.85.214.195])\n\tby lists.denx.de (Postfix) with ESMTPS id E1AC6C21BE5\n\tfor <u-boot@lists.denx.de>; Tue, 16 Jul 2019 11:59:22 +0000 (UTC)", "by mail-pl1-f195.google.com with SMTP id b7so10008171pls.6\n\tfor <u-boot@lists.denx.de>; Tue, 16 Jul 2019 04:59:22 -0700 (PDT)", "from localhost.localdomain ([49.206.201.107])\n\tby smtp.gmail.com with ESMTPSA id\n\tz24sm36269566pfr.51.2019.07.16.04.59.18\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tTue, 16 Jul 2019 04:59:21 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amarulasolutions.com; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=QafmgbriflDoZckEsWmBvRP9dqWRhbWXJvx5leo6fWE=;\n\tb=G9GmkIyMxUCZafuwifwOyMOdvE4YUiW2Pyldq2P4jP7P9VWxjNyeR0Zl4daLeX2FQ5\n\tvkZA9rbjjBxHvMaG57CDiPasegRm6ilHtPPQPbRIRlFcHU3VoEdIKsX45VeZh0UF1H5/\n\tz2BKn0UCKoXyzrWy6NvoScWLGFnSm1HOwES/Q=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=QafmgbriflDoZckEsWmBvRP9dqWRhbWXJvx5leo6fWE=;\n\tb=t6I3mF05gbF/gnuK5bpzH0R4sIHYzhqR7LmFIKJSG/46aM8+s03KJmpbFU0nc4Hlxl\n\tLDMmDBF/G8HWFEt5V4QfOk2+KJFMevG693z+r7tSTIPRqQIYCI89izvNqn2ZqX4VYMvv\n\t/TNOexh9gNUgckJZxSzjBKlzyLtqvaplXa+rkMZGihQZnALk0ZCldFZtWYKrmVOmTnX0\n\tn1/a1CZSi1KkAKw68A2N86u6IKtmoK28zFCx5A4Zjuk0TskccXgdbguZaH2wQMAEQdUq\n\trFunm001IJa2okC7rSYAjraRuxykHXYa4EMACpBer5YB38kcZ4tNLw6DGclryqoewh60\n\t1ZVg==", "X-Gm-Message-State": "APjAAAVSG8KMCrOa6H55AWEcSwB0Sgbb4xWVN/uxUdDEEDQga55jxHpW\n\tupfVoCiidoDtfcaoP5gGTLB5CQ==", "X-Google-Smtp-Source": "APXvYqyE/7+HV9SffRiIsTWg8Q4mpOhgTo1TGjLp8atNtz70aONaZN0ZeQ00NncLC/3ZruCkqp89wQ==", "X-Received": "by 2002:a17:902:8c98:: with SMTP id\n\tt24mr35697603plo.320.1563278361602; \n\tTue, 16 Jul 2019 04:59:21 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Simon Glass <sjg@chromium.org>,\n\tPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>,\n\tKever Yang <kever.yang@rock-chips.com>,\n\tYouMin Chen <cym@rock-chips.com>, u-boot@lists.denx.de", "Date": "Tue, 16 Jul 2019 17:27:12 +0530", "Message-Id": "<20190716115745.12585-25-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20190716115745.12585-1-jagan@amarulasolutions.com>", "References": "<20190716115745.12585-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com,\n\tlinux-amarula@amarulasolutions.com,\n\tManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>", "Subject": "[U-Boot] [PATCH v3 24/57] ram: rk3399: Don't wait for PLL lock in\n\tlpddr4", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "lpddr4 has PLL bypass mode during phy initialization phase,\nwhich does all pll configurations.\n\nSo no need to wait explicitly during pctl config.\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\nSigned-off-by: YouMin Chen <cym@rock-chips.com>\n---\n drivers/ram/rockchip/sdram_rk3399.c | 26 ++++++++++++++++----------\n 1 file changed, 16 insertions(+), 10 deletions(-)", "diff": "diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c\nindex 88fbfa440d..023838a301 100644\n--- a/drivers/ram/rockchip/sdram_rk3399.c\n+++ b/drivers/ram/rockchip/sdram_rk3399.c\n@@ -570,16 +570,22 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,\n \tsetbits_le32(&denali_pi[0], START);\n \tsetbits_le32(&denali_ctl[0], START);\n \n-\t/* Waiting for phy DLL lock */\n-\twhile (1) {\n-\t\ttmp = readl(&denali_phy[920]);\n-\t\ttmp1 = readl(&denali_phy[921]);\n-\t\ttmp2 = readl(&denali_phy[922]);\n-\t\tif ((((tmp >> 16) & 0x1) == 0x1) &&\n-\t\t (((tmp1 >> 16) & 0x1) == 0x1) &&\n-\t\t (((tmp1 >> 0) & 0x1) == 0x1) &&\n-\t\t (((tmp2 >> 0) & 0x1) == 0x1))\n-\t\t\tbreak;\n+\t/**\n+\t * LPDDR4 use PLL bypass mode for init\n+\t * not need to wait for the PLL to lock\n+\t */\n+\tif (params->base.dramtype != LPDDR4) {\n+\t\t/* Waiting for phy DLL lock */\n+\t\twhile (1) {\n+\t\t\ttmp = readl(&denali_phy[920]);\n+\t\t\ttmp1 = readl(&denali_phy[921]);\n+\t\t\ttmp2 = readl(&denali_phy[922]);\n+\t\t\tif ((((tmp >> 16) & 0x1) == 0x1) &&\n+\t\t\t (((tmp1 >> 16) & 0x1) == 0x1) &&\n+\t\t\t (((tmp1 >> 0) & 0x1) == 0x1) &&\n+\t\t\t (((tmp2 >> 0) & 0x1) == 0x1))\n+\t\t\t\tbreak;\n+\t\t}\n \t}\n \n \tcopy_to_reg(&denali_phy[896], ¶ms_phy[896], (958 - 895) * 4);\n", "prefixes": [ "U-Boot", "v3", "24/57" ] }