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GET /api/patches/1132707/?format=api
{ "id": 1132707, "url": "http://patchwork.ozlabs.org/api/patches/1132707/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190716115745.12585-44-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190716115745.12585-44-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2019-07-16T11:57:31", "name": "[U-Boot,v3,43/57] ram: rk3399: Add LPPDR4 mr detection", "commit_ref": "a0ded6d317b0a12e1555080e55971bde8e932026", "pull_url": null, "state": "accepted", "archived": false, "hash": "1ae1c26c2afb0e06009e8ddc7caa8f1ee8f6b26c", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 93623, "url": "http://patchwork.ozlabs.org/api/users/93623/?format=api", "username": "kevery", "first_name": "Kever", "last_name": "Yang", "email": "ykai007@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190716115745.12585-44-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 119754, "url": "http://patchwork.ozlabs.org/api/series/119754/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=119754", "date": "2019-07-16T11:56:48", "name": "ram: rk3399: Add LPDDR4 support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/119754/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1132707/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1132707/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"K3lhGmSn\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 45nztJ74rJz9sDB\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 16 Jul 2019 22:17:28 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 9315CC21E49; Tue, 16 Jul 2019 12:07:48 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 8FB3AC21E68;\n\tTue, 16 Jul 2019 12:04:04 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid B6B50C21E57; Tue, 16 Jul 2019 12:00:35 +0000 (UTC)", "from mail-pf1-f194.google.com (mail-pf1-f194.google.com\n\t[209.85.210.194])\n\tby lists.denx.de (Postfix) with ESMTPS id 5071FC21D8A\n\tfor <u-boot@lists.denx.de>; Tue, 16 Jul 2019 12:00:31 +0000 (UTC)", "by mail-pf1-f194.google.com with SMTP id q10so9002761pff.9\n\tfor <u-boot@lists.denx.de>; Tue, 16 Jul 2019 05:00:31 -0700 (PDT)", "from localhost.localdomain ([49.206.201.107])\n\tby smtp.gmail.com with ESMTPSA id\n\tz24sm36269566pfr.51.2019.07.16.05.00.26\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tTue, 16 Jul 2019 05:00:29 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amarulasolutions.com; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=b4BLaekI2K9GhOfNexihMzKGNJDUcPNIWa3ew4v23qw=;\n\tb=K3lhGmSnzmnlgICT8KJWsY3bF5icg0jJS6zeejbF97kq31uvbGfrOOklqUA81yN9TB\n\tj866L+st/p+IjPQlgypBCgCwTvB71hcWr4ToIVNuur6MM3y5o71mNhAJGd3vPy6pGkfC\n\tDIWxT2WQpEs/1yWis8Ih/HeQdfqGek5m89N5o=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=b4BLaekI2K9GhOfNexihMzKGNJDUcPNIWa3ew4v23qw=;\n\tb=Ipob8D9mlR/bHkIRvgzCa85nRqhI+NUvdnLlIABbG2IezK867XQKxK3qEcFVxvCDNT\n\tYkceLh7GHopnX0Ub5H4LjnpLo67pnCkxcIZslL0tHC7lqquxwuLehoTZ7eZb1TzGMCKB\n\tbjS0PlKzcmeIGpr6WImTbHIWCB++bfOpO5UQVgxvsqkGGQWmP5MdYYQa1d1F8Mwkz+yP\n\tADHIMzcCjovv0qd89tBlS0krlppwjlpn+ytM6P05IfalJCSJr2wJ08xCqHx6HAs86nMP\n\tcFBZpch2CkN/ywpBtqdswJ73Ad05Nm2WxTLq/KpUntWNMv5KopzDeCb0uUwbKE4UdzbF\n\tknYg==", "X-Gm-Message-State": "APjAAAU5rvmhqgQ99KHLwFml6Z17ON+FdFNismYVd2tYBxk/yq4iwe6M\n\te1B/hjMleptbCtlZLQ8FHgzkGA==", "X-Google-Smtp-Source": "APXvYqwzAkNtImAs72C3PXNV1opZphi71baykhP/0Gunn4MMbiaRiBckMyF2ApCEyg8SE3efEW+aZg==", "X-Received": "by 2002:a63:fb14:: with SMTP id\n\to20mr22137271pgh.136.1563278429813; \n\tTue, 16 Jul 2019 05:00:29 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Simon Glass <sjg@chromium.org>,\n\tPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>,\n\tKever Yang <kever.yang@rock-chips.com>,\n\tYouMin Chen <cym@rock-chips.com>, u-boot@lists.denx.de", "Date": "Tue, 16 Jul 2019 17:27:31 +0530", "Message-Id": "<20190716115745.12585-44-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20190716115745.12585-1-jagan@amarulasolutions.com>", "References": "<20190716115745.12585-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com,\n\tlinux-amarula@amarulasolutions.com,\n\tManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>", "Subject": "[U-Boot] [PATCH v3 43/57] ram: rk3399: Add LPPDR4 mr detection", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Like data training in other sdram types, mr detection need\nto taken care for lpddr4 with looped rank and associated\nchannel to make sure the proper configuration held.\n\nOnce the mr detection successful for active and configured\nrank with channel number, the same can later reused during\nactual LPDDR4 initialization.\n\nSo, add code to support for it.\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\nSigned-off-by: YouMin Chen <cym@rock-chips.com>\n---\n drivers/ram/rockchip/sdram_rk3399.c | 226 ++++++++++++++++++++++++++++\n 1 file changed, 226 insertions(+)", "diff": "diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c\nindex da01f08732..623685e3c5 100644\n--- a/drivers/ram/rockchip/sdram_rk3399.c\n+++ b/drivers/ram/rockchip/sdram_rk3399.c\n@@ -1470,6 +1470,7 @@ static void dram_all_config(struct dram_info *dram,\n \tclrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);\n }\n \n+#if !defined(CONFIG_RAM_RK3399_LPDDR4)\n static int default_data_training(struct dram_info *dram, u32 channel, u8 rank,\n \t\t\t\t struct rk3399_sdram_params *params)\n {\n@@ -1486,6 +1487,7 @@ static int default_data_training(struct dram_info *dram, u32 channel, u8 rank,\n \n \treturn data_training(dram, channel, params, training_flag);\n }\n+#endif\n \n static int switch_to_phy_index1(struct dram_info *dram,\n \t\t\t\tconst struct rk3399_sdram_params *params)\n@@ -1532,6 +1534,226 @@ static int switch_to_phy_index1(struct dram_info *dram,\n \treturn 0;\n }\n \n+#if defined(CONFIG_RAM_RK3399_LPDDR4)\n+static u32 get_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf)\n+{\n+\treturn ((readl(&pmusgrf->soc_con4) >> 10) & 0x1F);\n+}\n+\n+static void set_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf, u32 stride)\n+{\n+\trk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, stride << 10);\n+}\n+\n+static void set_cap_relate_config(const struct chan_info *chan,\n+\t\t\t\t struct rk3399_sdram_params *params,\n+\t\t\t\t unsigned int channel)\n+{\n+\tu32 *denali_ctl = chan->pctl->denali_ctl;\n+\tu32 tmp;\n+\tstruct rk3399_msch_timings *noc_timing;\n+\n+\tif (params->base.dramtype == LPDDR3) {\n+\t\ttmp = (8 << params->ch[channel].cap_info.bw) /\n+\t\t\t(8 << params->ch[channel].cap_info.dbw);\n+\n+\t\t/**\n+\t\t * memdata_ratio\n+\t\t * 1 -> 0, 2 -> 1, 4 -> 2\n+\t\t */\n+\t\tclrsetbits_le32(&denali_ctl[197], 0x7,\n+\t\t\t\t(tmp >> 1));\n+\t\tclrsetbits_le32(&denali_ctl[198], 0x7 << 8,\n+\t\t\t\t(tmp >> 1) << 8);\n+\t}\n+\n+\tnoc_timing = ¶ms->ch[channel].noc_timings;\n+\n+\t/*\n+\t * noc timing bw relate timing is 32 bit, and real bw is 16bit\n+\t * actually noc reg is setting at function dram_all_config\n+\t */\n+\tif (params->ch[channel].cap_info.bw == 16 &&\n+\t noc_timing->ddrmode.b.mwrsize == 2) {\n+\t\tif (noc_timing->ddrmode.b.burstsize)\n+\t\t\tnoc_timing->ddrmode.b.burstsize -= 1;\n+\t\tnoc_timing->ddrmode.b.mwrsize -= 1;\n+\t\tnoc_timing->ddrtimingc0.b.burstpenalty *= 2;\n+\t\tnoc_timing->ddrtimingc0.b.wrtomwr *= 2;\n+\t}\n+}\n+\n+static u32 calculate_ddrconfig(struct rk3399_sdram_params *params, u32 channel)\n+{\n+\tunsigned int cs0_row = params->ch[channel].cap_info.cs0_row;\n+\tunsigned int col = params->ch[channel].cap_info.col;\n+\tunsigned int bw = params->ch[channel].cap_info.bw;\n+\tu16 ddr_cfg_2_rbc[] = {\n+\t\t/*\n+\t\t * [6]\t highest bit col\n+\t\t * [5:3] max row(14+n)\n+\t\t * [2] insertion row\n+\t\t * [1:0] col(9+n),col, data bus 32bit\n+\t\t *\n+\t\t * highbitcol, max_row, insertion_row, col\n+\t\t */\n+\t\t((0 << 6) | (2 << 3) | (0 << 2) | 0), /* 0 */\n+\t\t((0 << 6) | (2 << 3) | (0 << 2) | 1), /* 1 */\n+\t\t((0 << 6) | (1 << 3) | (0 << 2) | 2), /* 2 */\n+\t\t((0 << 6) | (0 << 3) | (0 << 2) | 3), /* 3 */\n+\t\t((0 << 6) | (2 << 3) | (1 << 2) | 1), /* 4 */\n+\t\t((0 << 6) | (1 << 3) | (1 << 2) | 2), /* 5 */\n+\t\t((1 << 6) | (0 << 3) | (0 << 2) | 2), /* 6 */\n+\t\t((1 << 6) | (1 << 3) | (0 << 2) | 2), /* 7 */\n+\t};\n+\tu32 i;\n+\n+\tcol -= (bw == 2) ? 0 : 1;\n+\tcol -= 9;\n+\n+\tfor (i = 0; i < 4; i++) {\n+\t\tif ((col == (ddr_cfg_2_rbc[i] & 0x3)) &&\n+\t\t (cs0_row <= (((ddr_cfg_2_rbc[i] >> 3) & 0x7) + 14)))\n+\t\t\tbreak;\n+\t}\n+\n+\tif (i >= 4)\n+\t\ti = -EINVAL;\n+\n+\treturn i;\n+}\n+\n+/**\n+ * read mr_num mode register\n+ * rank = 1: cs0\n+ * rank = 2: cs1\n+ */\n+static int read_mr(struct rk3399_ddr_pctl_regs *ddr_pctl_regs, u32 rank,\n+\t\t u32 mr_num, u32 *buf)\n+{\n+\ts32 timeout = 100;\n+\n+\twritel(((1 << 16) | (((rank == 2) ? 1 : 0) << 8) | mr_num) << 8,\n+\t &ddr_pctl_regs->denali_ctl[118]);\n+\n+\twhile (0 == (readl(&ddr_pctl_regs->denali_ctl[203]) &\n+\t\t\t((1 << 21) | (1 << 12)))) {\n+\t\tudelay(1);\n+\n+\t\tif (timeout <= 0) {\n+\t\t\tprintf(\"%s: pctl timeout!\\n\", __func__);\n+\t\t\treturn -ETIMEDOUT;\n+\t\t}\n+\n+\t\ttimeout--;\n+\t}\n+\n+\tif (!(readl(&ddr_pctl_regs->denali_ctl[203]) & (1 << 12))) {\n+\t\t*buf = readl(&ddr_pctl_regs->denali_ctl[119]) & 0xFF;\n+\t} else {\n+\t\tprintf(\"%s: read mr failed with 0x%x status\\n\", __func__,\n+\t\t readl(&ddr_pctl_regs->denali_ctl[17]) & 0x3);\n+\t\t*buf = 0;\n+\t}\n+\n+\tsetbits_le32(&ddr_pctl_regs->denali_ctl[205], (1 << 21) | (1 << 12));\n+\n+\treturn 0;\n+}\n+\n+static int lpddr4_mr_detect(struct dram_info *dram, u32 channel, u8 rank,\n+\t\t\t struct rk3399_sdram_params *params)\n+{\n+\tu64 cs0_cap;\n+\tu32 stride;\n+\tu32 cs = 0, col = 0, bk = 0, bw = 0, row_3_4 = 0;\n+\tu32 cs0_row = 0, cs1_row = 0, ddrconfig = 0;\n+\tu32 mr5, mr12, mr14;\n+\tstruct chan_info *chan = &dram->chan[channel];\n+\tstruct rk3399_ddr_pctl_regs *ddr_pctl_regs = chan->pctl;\n+\tvoid __iomem *addr = NULL;\n+\tint ret = 0;\n+\tu32 val;\n+\n+\tstride = get_ddr_stride(dram->pmusgrf);\n+\n+\tif (params->ch[channel].cap_info.col == 0) {\n+\t\tret = -EPERM;\n+\t\tgoto end;\n+\t}\n+\n+\tcs = params->ch[channel].cap_info.rank;\n+\tcol = params->ch[channel].cap_info.col;\n+\tbk = params->ch[channel].cap_info.bk;\n+\tbw = params->ch[channel].cap_info.bw;\n+\trow_3_4 = params->ch[channel].cap_info.row_3_4;\n+\tcs0_row = params->ch[channel].cap_info.cs0_row;\n+\tcs1_row = params->ch[channel].cap_info.cs1_row;\n+\tddrconfig = params->ch[channel].cap_info.ddrconfig;\n+\n+\t/* 2GB */\n+\tparams->ch[channel].cap_info.rank = 2;\n+\tparams->ch[channel].cap_info.col = 10;\n+\tparams->ch[channel].cap_info.bk = 3;\n+\tparams->ch[channel].cap_info.bw = 2;\n+\tparams->ch[channel].cap_info.row_3_4 = 0;\n+\tparams->ch[channel].cap_info.cs0_row = 15;\n+\tparams->ch[channel].cap_info.cs1_row = 15;\n+\tparams->ch[channel].cap_info.ddrconfig = 1;\n+\n+\tset_memory_map(chan, channel, params);\n+\tparams->ch[channel].cap_info.ddrconfig =\n+\t\t\tcalculate_ddrconfig(params, channel);\n+\tset_ddrconfig(chan, params, channel,\n+\t\t params->ch[channel].cap_info.ddrconfig);\n+\tset_cap_relate_config(chan, params, channel);\n+\n+\tcs0_cap = (1 << (params->ch[channel].cap_info.bw\n+\t\t\t+ params->ch[channel].cap_info.col\n+\t\t\t+ params->ch[channel].cap_info.bk\n+\t\t\t+ params->ch[channel].cap_info.cs0_row));\n+\n+\tif (params->ch[channel].cap_info.row_3_4)\n+\t\tcs0_cap = cs0_cap * 3 / 4;\n+\n+\tif (channel == 0)\n+\t\tset_ddr_stride(dram->pmusgrf, 0x17);\n+\telse\n+\t\tset_ddr_stride(dram->pmusgrf, 0x18);\n+\n+\t/* read and write data to DRAM, avoid be optimized by compiler. */\n+\tif (rank == 1)\n+\t\taddr = (void __iomem *)0x100;\n+\telse if (rank == 2)\n+\t\taddr = (void __iomem *)(cs0_cap + 0x100);\n+\n+\tval = readl(addr);\n+\twritel(val + 1, addr);\n+\n+\tread_mr(ddr_pctl_regs, rank, 5, &mr5);\n+\tread_mr(ddr_pctl_regs, rank, 12, &mr12);\n+\tread_mr(ddr_pctl_regs, rank, 14, &mr14);\n+\n+\tif (mr5 == 0 || mr12 != 0x4d || mr14 != 0x4d) {\n+\t\tret = -EINVAL;\n+\t\tgoto end;\n+\t}\n+end:\n+\tparams->ch[channel].cap_info.rank = cs;\n+\tparams->ch[channel].cap_info.col = col;\n+\tparams->ch[channel].cap_info.bk = bk;\n+\tparams->ch[channel].cap_info.bw = bw;\n+\tparams->ch[channel].cap_info.row_3_4 = row_3_4;\n+\tparams->ch[channel].cap_info.cs0_row = cs0_row;\n+\tparams->ch[channel].cap_info.cs1_row = cs1_row;\n+\tparams->ch[channel].cap_info.ddrconfig = ddrconfig;\n+\n+\tset_ddr_stride(dram->pmusgrf, stride);\n+\n+\treturn ret;\n+}\n+#endif /* CONFIG_RAM_RK3399_LPDDR4 */\n+\n static unsigned char calculate_stride(struct rk3399_sdram_params *params)\n {\n \tunsigned int stride = params->base.stride;\n@@ -1762,7 +1984,11 @@ static int conv_of_platdata(struct udevice *dev)\n #endif\n \n static const struct sdram_rk3399_ops rk3399_ops = {\n+#if !defined(CONFIG_RAM_RK3399_LPDDR4)\n \t.data_training = default_data_training,\n+#else\n+\t.data_training = lpddr4_mr_detect,\n+#endif\n };\n \n static int rk3399_dmc_init(struct udevice *dev)\n", "prefixes": [ "U-Boot", "v3", "43/57" ] }