Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/1132705/?format=api
{ "id": 1132705, "url": "http://patchwork.ozlabs.org/api/patches/1132705/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190716115745.12585-36-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190716115745.12585-36-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2019-07-16T11:57:23", "name": "[U-Boot,v3,35/57] ram: rk3399: Add tsel control clock drive", "commit_ref": "aa30aae8b4e8c871a263ad67c4b4fdca236bf7c1", "pull_url": null, "state": "accepted", "archived": false, "hash": "3bc4adc301a94ccb6796a05048ad590f047905b3", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 93623, "url": "http://patchwork.ozlabs.org/api/users/93623/?format=api", "username": "kevery", "first_name": "Kever", "last_name": "Yang", "email": "ykai007@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190716115745.12585-36-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 119754, "url": "http://patchwork.ozlabs.org/api/series/119754/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=119754", "date": "2019-07-16T11:56:48", "name": "ram: rk3399: Add LPDDR4 support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/119754/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1132705/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1132705/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"GKyNTgUx\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 45nzs42yS8z9sDB\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 16 Jul 2019 22:16:23 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid BAEC5C21E42; Tue, 16 Jul 2019 12:13:15 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id A60FEC21E34;\n\tTue, 16 Jul 2019 12:09:53 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid B85D3C21E29; Tue, 16 Jul 2019 12:00:07 +0000 (UTC)", "from mail-pf1-f193.google.com (mail-pf1-f193.google.com\n\t[209.85.210.193])\n\tby lists.denx.de (Postfix) with ESMTPS id 88021C21E0B\n\tfor <u-boot@lists.denx.de>; Tue, 16 Jul 2019 12:00:02 +0000 (UTC)", "by mail-pf1-f193.google.com with SMTP id y15so9016052pfn.5\n\tfor <u-boot@lists.denx.de>; Tue, 16 Jul 2019 05:00:02 -0700 (PDT)", "from localhost.localdomain ([49.206.201.107])\n\tby smtp.gmail.com with ESMTPSA id\n\tz24sm36269566pfr.51.2019.07.16.04.59.57\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tTue, 16 Jul 2019 05:00:00 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amarulasolutions.com; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=TGL2vZAdQiuNUHRO4mTXKyX2zgq3XTrcqwdNqg+WCgA=;\n\tb=GKyNTgUxA0VJOA7Gqy91j4UKiSQHC+1Xs2gPWDhtnIY2Cs2qMj/fyiJtHeAldpBR7L\n\t59MyCFGTUGO0ZQZ3AugH3nV0WHMx321xhRSRqVDd9w9ohU6OPAcY78fP210ppqMEjl3l\n\tepDWjbmvdcQqjBulYBkCigKcHgLr00hfmt4Aw=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=TGL2vZAdQiuNUHRO4mTXKyX2zgq3XTrcqwdNqg+WCgA=;\n\tb=TefRjtiFqfENWRZ2WHHpfrRAS5DS9naWIqitlpAq7FjJCil7NSzKwU/lC/1Ij2Jko4\n\t2tkx7UBU50v+vpg6mkjmJtYbCQ0nbfRsOaOLPE+p+1m7KDbfcQo2j7VBDb9NOuqnqZez\n\t8p+tbd61MTV2la6BC9+aa86KAYIY28T/zNod0wgQn32oy6nP9qOAnoGtTbvZKIeq8Dvr\n\thjU0gltc4HOlv6rjsrSz+Hdzx0cED4SF8E3+i7O9dEDEG1j6eOw9xT9pl4c5uvAaa00j\n\trHXUpV3PNcPODNWgx/YcvFJYNzdPFxgnNZij0yzMKhBLLijEgJD8KOK9WQY1n5ZTixPw\n\t2qbw==", "X-Gm-Message-State": "APjAAAWBrwGuP7K2wNC491W7OanECDN1bKz00KpOLxOo4vuMzk8HTyLo\n\tKTRuJLZ7iO21GgVZUtSpV/WZiQ==", "X-Google-Smtp-Source": "APXvYqxAHrIoSL9SI2ry+6xY2wXaj5kic12U6srR/jlDuIHmJkBpgnqQyqcT1QZU43ApsdveBRnr5w==", "X-Received": "by 2002:a17:90a:30e4:: with SMTP id\n\th91mr34311060pjb.37.1563278401129; \n\tTue, 16 Jul 2019 05:00:01 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Simon Glass <sjg@chromium.org>,\n\tPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>,\n\tKever Yang <kever.yang@rock-chips.com>,\n\tYouMin Chen <cym@rock-chips.com>, u-boot@lists.denx.de", "Date": "Tue, 16 Jul 2019 17:27:23 +0530", "Message-Id": "<20190716115745.12585-36-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20190716115745.12585-1-jagan@amarulasolutions.com>", "References": "<20190716115745.12585-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com,\n\tlinux-amarula@amarulasolutions.com,\n\tManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>", "Subject": "[U-Boot] [PATCH v3 35/57] ram: rk3399: Add tsel control clock drive", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "tsel contrl clock drives are required to configure PHY\n929, 939 controls drive settings.\n\nAdd support for these control clock for all dramtype\nsdrams.\n\nThse control clock drives are configure via tsel_ckcs_select_p\nand tsel_ckcs_select_n variables.\n\ntsel_ckcs_select_n is PHY_DRV_ODT_34_3 value where as\ntsel_ckcs_select_p is retrived from IO settings for lpddr4\nand rest uses PHY_DRV_ODT_34_3.\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\nSigned-off-by: YouMin Chen <cym@rock-chips.com>\n---\n drivers/ram/rockchip/sdram_rk3399.c | 16 ++++++++++++++--\n 1 file changed, 14 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c\nindex 1b8ce5160f..c38ea1d284 100644\n--- a/drivers/ram/rockchip/sdram_rk3399.c\n+++ b/drivers/ram/rockchip/sdram_rk3399.c\n@@ -560,6 +560,7 @@ static void set_ds_odt(const struct chan_info *chan,\n \tu32 tsel_idle_select_n, tsel_rd_select_n;\n \tu32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;\n \tu32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;\n+\tu32 tsel_ckcs_select_p, tsel_ckcs_select_n;\n \tstruct io_setting *io = NULL;\n \tu32 reg_value;\n \n@@ -577,6 +578,9 @@ static void set_ds_odt(const struct chan_info *chan,\n \n \t\ttsel_wr_select_ca_p = io->wr_ca_drv;\n \t\ttsel_wr_select_ca_n = PHY_DRV_ODT_40;\n+\n+\t\ttsel_ckcs_select_p = io->wr_ckcs_drv;\n+\t\ttsel_ckcs_select_n = PHY_DRV_ODT_34_3;\n \t} else if (params->base.dramtype == LPDDR3) {\n \t\ttsel_rd_select_p = PHY_DRV_ODT_240;\n \t\ttsel_rd_select_n = PHY_DRV_ODT_HI_Z;\n@@ -589,6 +593,9 @@ static void set_ds_odt(const struct chan_info *chan,\n \n \t\ttsel_wr_select_ca_p = PHY_DRV_ODT_48;\n \t\ttsel_wr_select_ca_n = PHY_DRV_ODT_48;\n+\n+\t\ttsel_ckcs_select_p = PHY_DRV_ODT_34_3;\n+\t\ttsel_ckcs_select_n = PHY_DRV_ODT_34_3;\n \t} else {\n \t\ttsel_rd_select_p = PHY_DRV_ODT_240;\n \t\ttsel_rd_select_n = PHY_DRV_ODT_240;\n@@ -601,6 +608,9 @@ static void set_ds_odt(const struct chan_info *chan,\n \n \t\ttsel_wr_select_ca_p = PHY_DRV_ODT_34_3;\n \t\ttsel_wr_select_ca_n = PHY_DRV_ODT_34_3;\n+\n+\t\ttsel_ckcs_select_p = PHY_DRV_ODT_34_3;\n+\t\ttsel_ckcs_select_n = PHY_DRV_ODT_34_3;\n \t}\n \n \tif (params->base.odt == 1)\n@@ -659,10 +669,12 @@ static void set_ds_odt(const struct chan_info *chan,\n \tclrsetbits_le32(&denali_phy[935], 0xff, reg_value);\n \n \t/* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */\n-\tclrsetbits_le32(&denali_phy[939], 0xff, reg_value);\n+\tclrsetbits_le32(&denali_phy[939], 0xff,\n+\t\t\ttsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4));\n \n \t/* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */\n-\tclrsetbits_le32(&denali_phy[929], 0xff, reg_value);\n+\tclrsetbits_le32(&denali_phy[929], 0xff,\n+\t\t\ttsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4));\n \n \t/* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */\n \tclrsetbits_le32(&denali_phy[924], 0xff,\n", "prefixes": [ "U-Boot", "v3", "35/57" ] }