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GET /api/patches/1132704/?format=api
{ "id": 1132704, "url": "http://patchwork.ozlabs.org/api/patches/1132704/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190716115745.12585-32-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190716115745.12585-32-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2019-07-16T11:57:19", "name": "[U-Boot,v3,31/57] ram: rk3399: Configure tsel write ca for lpddr4", "commit_ref": "66912baa0f00b915df5d2135c40e62b58c965669", "pull_url": null, "state": "accepted", "archived": false, "hash": "b11523305de4bd40ad2c4bb85792a592b367e05a", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 93623, "url": "http://patchwork.ozlabs.org/api/users/93623/?format=api", "username": "kevery", "first_name": "Kever", "last_name": "Yang", "email": "ykai007@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190716115745.12585-32-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 119754, "url": "http://patchwork.ozlabs.org/api/series/119754/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=119754", "date": "2019-07-16T11:56:48", "name": "ram: rk3399: Add LPDDR4 support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/119754/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1132704/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1132704/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"aX9gVM3W\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 45nzqL2fXvz9sDB\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 16 Jul 2019 22:14:54 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 12DB4C21E34; Tue, 16 Jul 2019 12:03:51 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 18D4AC21E70;\n\tTue, 16 Jul 2019 12:01:09 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid C5ECFC21E76; Tue, 16 Jul 2019 11:59:51 +0000 (UTC)", "from mail-pl1-f195.google.com (mail-pl1-f195.google.com\n\t[209.85.214.195])\n\tby lists.denx.de (Postfix) with ESMTPS id 0255BC21E12\n\tfor <u-boot@lists.denx.de>; Tue, 16 Jul 2019 11:59:48 +0000 (UTC)", "by mail-pl1-f195.google.com with SMTP id t14so9979101plr.11\n\tfor <u-boot@lists.denx.de>; Tue, 16 Jul 2019 04:59:47 -0700 (PDT)", "from localhost.localdomain ([49.206.201.107])\n\tby smtp.gmail.com with ESMTPSA id\n\tz24sm36269566pfr.51.2019.07.16.04.59.43\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tTue, 16 Jul 2019 04:59:46 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amarulasolutions.com; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=ShnizxVOFJJJ3jmxPzb0Nn+OAjZ/FrAS/NyUepu9UZE=;\n\tb=aX9gVM3WuboOXqKZ7clAOoMR64pgtwhMjTr/JXBVDuv8JKQxCdr5LWKoYfXUV/zA+7\n\tmV00iOIWwhtIxc5FYvoRXBJ5LODPW9SBoAUUiw/7HN6If4ESvEUG6ZqZYQ3KiSO60OQv\n\tdDSrAUj094v3HIyD/Z11uhh2djNVXBCVxDdE0=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=ShnizxVOFJJJ3jmxPzb0Nn+OAjZ/FrAS/NyUepu9UZE=;\n\tb=TrCCkXsP8TodJDUnP1gHcWDz0chHUfps3yf0bEo740crHoF4TAsh+BAfA2SU088a53\n\tvlgEzSzuV5/PA6rvx9XQT8Ap76EweZtSD2/mmib5+/BD5vvKylGvuyOWtN6Tg2bptHy4\n\tpJFQFih3kHRfYqDk3sxrxNn26LuiLF/n7RmA/A3Q8SVpsUZfVjzLrOH1tVd5ZcJs4KRE\n\t57USW29B0ZMyOMzjYJDz5D4jRBtpY+nBe5eN8aZAyoPZP5pf4y8zXizCKeveY3sizHdr\n\tAPTXTluGEmibzWyknhlW2IYMBhVJOYctyVyRDMiQ27EDJqOVF1W5zOwEzGRrM6h6JgBo\n\tR+QQ==", "X-Gm-Message-State": "APjAAAVEj/RjiBjGF9bc3UJtvNlO2gmWb/BhCXvD9Ge3FPwKyfALJsMK\n\tlUbLdnaK8CPAWOz7IE1IOeyGPg==", "X-Google-Smtp-Source": "APXvYqzxWT8p5VoYSAccA8eKL5WKV0H81x/AK5EFgGKCPkEpT6WVpAI+AaxA0eZaITNoyO5KOF67xw==", "X-Received": "by 2002:a17:902:8c98:: with SMTP id\n\tt24mr35700706plo.320.1563278386651; \n\tTue, 16 Jul 2019 04:59:46 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Simon Glass <sjg@chromium.org>,\n\tPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>,\n\tKever Yang <kever.yang@rock-chips.com>,\n\tYouMin Chen <cym@rock-chips.com>, u-boot@lists.denx.de", "Date": "Tue, 16 Jul 2019 17:27:19 +0530", "Message-Id": "<20190716115745.12585-32-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20190716115745.12585-1-jagan@amarulasolutions.com>", "References": "<20190716115745.12585-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com,\n\tlinux-amarula@amarulasolutions.com,\n\tManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>", "Subject": "[U-Boot] [PATCH v3 31/57] ram: rk3399: Configure tsel write ca for\n\tlpddr4", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "tsel write ca_p and ca_n values need to write on PHY 544, 672\nand 800 to configure ds odt.\n\nConfigure the same PHY register for lpddr4 would require a mask\nvalue of (300 << 8).\n\nAdd support for it.\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\nSigned-off-by: YouMin Chen <cym@rock-chips.com>\n---\n drivers/ram/rockchip/sdram_rk3399.c | 15 ++++++++++++---\n 1 file changed, 12 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c\nindex 7689711a99..1050cbdb07 100644\n--- a/drivers/ram/rockchip/sdram_rk3399.c\n+++ b/drivers/ram/rockchip/sdram_rk3399.c\n@@ -502,9 +502,18 @@ static void set_ds_odt(const struct chan_info *chan,\n \n \t/* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */\n \treg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4);\n-\tclrsetbits_le32(&denali_phy[544], 0xff, reg_value);\n-\tclrsetbits_le32(&denali_phy[672], 0xff, reg_value);\n-\tclrsetbits_le32(&denali_phy[800], 0xff, reg_value);\n+\tif (IS_ENABLED(CONFIG_RAM_RK3399_LPDDR4)) {\n+\t\t/* LPDDR4 these register read always return 0, so\n+\t\t * can not use clrsetbits_le32(), need to write32\n+\t\t */\n+\t\twritel((0x300 << 8) | reg_value, &denali_phy[544]);\n+\t\twritel((0x300 << 8) | reg_value, &denali_phy[672]);\n+\t\twritel((0x300 << 8) | reg_value, &denali_phy[800]);\n+\t} else {\n+\t\tclrsetbits_le32(&denali_phy[544], 0xff, reg_value);\n+\t\tclrsetbits_le32(&denali_phy[672], 0xff, reg_value);\n+\t\tclrsetbits_le32(&denali_phy[800], 0xff, reg_value);\n+\t}\n \n \t/* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */\n \tclrsetbits_le32(&denali_phy[928], 0xff, reg_value);\n", "prefixes": [ "U-Boot", "v3", "31/57" ] }