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GET /api/patches/1132702/?format=api
{ "id": 1132702, "url": "http://patchwork.ozlabs.org/api/patches/1132702/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190716115745.12585-43-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190716115745.12585-43-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2019-07-16T11:57:30", "name": "[U-Boot,v3,42/57] ram: rk3399: Handle data training via ops", "commit_ref": "299deecf4a8cd6bc5b17fd3691a39066601eca35", "pull_url": null, "state": "accepted", "archived": false, "hash": "28bfa3b9cb2024383be1e2e3792f957f65422668", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 93623, "url": "http://patchwork.ozlabs.org/api/users/93623/?format=api", "username": "kevery", "first_name": "Kever", "last_name": "Yang", "email": "ykai007@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190716115745.12585-43-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 119754, "url": "http://patchwork.ozlabs.org/api/series/119754/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=119754", "date": "2019-07-16T11:56:48", "name": "ram: rk3399: Add LPDDR4 support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/119754/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1132702/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1132702/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"EIdIpU5F\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 45nzpy01vhz9sDB\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 16 Jul 2019 22:14:33 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 7C9B9C21E39; Tue, 16 Jul 2019 12:09:12 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 53E56C21E88;\n\tTue, 16 Jul 2019 12:06:12 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 70024C21E3A; Tue, 16 Jul 2019 12:00:31 +0000 (UTC)", "from mail-pf1-f194.google.com (mail-pf1-f194.google.com\n\t[209.85.210.194])\n\tby lists.denx.de (Postfix) with ESMTPS id BE428C21BE5\n\tfor <u-boot@lists.denx.de>; Tue, 16 Jul 2019 12:00:27 +0000 (UTC)", "by mail-pf1-f194.google.com with SMTP id q10so9002682pff.9\n\tfor <u-boot@lists.denx.de>; Tue, 16 Jul 2019 05:00:27 -0700 (PDT)", "from localhost.localdomain ([49.206.201.107])\n\tby smtp.gmail.com with ESMTPSA id\n\tz24sm36269566pfr.51.2019.07.16.05.00.22\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tTue, 16 Jul 2019 05:00:25 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amarulasolutions.com; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=pvEnnrz0lb6LWaNsBzHfmbnfvu86FZMrrMpEWA2uhEI=;\n\tb=EIdIpU5FBAXI1xKG+1XTCJ/yhTnmzopcp7E6SGER73S/tsNPdzBIksm79tyhRmpRID\n\tNVyuVdADLmJvXJd0Vt4Cavnyvk8g9yGftZgEn2qE75w0m2mkJke0QQdGc7XQuX2RQU1k\n\tBfHFkjNX/1i3a8Cp6A2G7B8e3oiHtKfme5hTY=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=pvEnnrz0lb6LWaNsBzHfmbnfvu86FZMrrMpEWA2uhEI=;\n\tb=XsFj8e8h/0IyYu+pibhwqc6ONzrdlUUNJLJNlptoM/fLmzmMyG7zzd9o1/+mgB++Nb\n\teN2iDOBdX/1OoJehnklHJW6FN082lCKEGWPLjJlr4lDfvq6fxWjNsC/7FnQz1DZCuYBe\n\tfC30iSwGzE4msnZnEfkRylJ4BRH2bufadIdlNeDfqSZrPLqcMxR6e1zoSEnvqsae2iwn\n\tK12a7CDMFhQAwNF7Rllr0Cp9d+z43u8KhikYxXw0T2rnxitwF9hTU4AGKQPHDPHzgEvk\n\tOV5yhvL8UzN7NEFtFNPhW6SrUu8B6yjV7OSVX2CzXXXQkE2koPitU7q9s1VvLPsZcMol\n\tzvBA==", "X-Gm-Message-State": "APjAAAXG6lZ6eMiDoMug1pa747t75UYkZXsODH9oUjlldldBRc28lExL\n\t2oK6dIEVrTysAbuJsZ4t80T1vg==", "X-Google-Smtp-Source": "APXvYqyawtcy0B0iq6YAsO4xDtQAcSM8EJo04vDJO1ZsTkb1bC6rs5hpnKZuenoosfDDjYV78avyKw==", "X-Received": "by 2002:a63:550e:: with SMTP id\n\tj14mr29996532pgb.302.1563278426206; \n\tTue, 16 Jul 2019 05:00:26 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Simon Glass <sjg@chromium.org>,\n\tPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>,\n\tKever Yang <kever.yang@rock-chips.com>,\n\tYouMin Chen <cym@rock-chips.com>, u-boot@lists.denx.de", "Date": "Tue, 16 Jul 2019 17:27:30 +0530", "Message-Id": "<20190716115745.12585-43-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20190716115745.12585-1-jagan@amarulasolutions.com>", "References": "<20190716115745.12585-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com,\n\tlinux-amarula@amarulasolutions.com,\n\tManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>", "Subject": "[U-Boot] [PATCH v3 42/57] ram: rk3399: Handle data training via ops", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "data training can be even required for lpddr4 and we\nneed to keep the lpddr4 code to compile only for relevant\nboards which do support lpddr4.\n\nFor this requirement, and for code readability handle\ndata training via sdram_rk3399_ops and same will update\nin future while supporting lpddr4 code.\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\n---\n drivers/ram/rockchip/sdram_rk3399.c | 43 ++++++++++++++++++++++-------\n 1 file changed, 33 insertions(+), 10 deletions(-)", "diff": "diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c\nindex 1aaaeb5b88..da01f08732 100644\n--- a/drivers/ram/rockchip/sdram_rk3399.c\n+++ b/drivers/ram/rockchip/sdram_rk3399.c\n@@ -65,11 +65,17 @@ struct dram_info {\n \tstruct rk3399_pmucru *pmucru;\n \tstruct rk3399_pmusgrf_regs *pmusgrf;\n \tstruct rk3399_ddr_cic_regs *cic;\n+\tconst struct sdram_rk3399_ops *ops;\n #endif\n \tstruct ram_info info;\n \tstruct rk3399_pmugrf_regs *pmugrf;\n };\n \n+struct sdram_rk3399_ops {\n+\tint (*data_training)(struct dram_info *dram, u32 channel, u8 rank,\n+\t\t\t struct rk3399_sdram_params *sdram);\n+};\n+\n #if defined(CONFIG_TPL_BUILD) || \\\n \t(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))\n \n@@ -1464,6 +1470,23 @@ static void dram_all_config(struct dram_info *dram,\n \tclrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);\n }\n \n+static int default_data_training(struct dram_info *dram, u32 channel, u8 rank,\n+\t\t\t\t struct rk3399_sdram_params *params)\n+{\n+\tu8 training_flag = PI_READ_GATE_TRAINING;\n+\n+\t/*\n+\t * LPDDR3 CA training msut be trigger before\n+\t * other training.\n+\t * DDR3 is not have CA training.\n+\t */\n+\n+\tif (params->base.dramtype == LPDDR3)\n+\t\ttraining_flag |= PI_CA_TRAINING;\n+\n+\treturn data_training(dram, channel, params, training_flag);\n+}\n+\n static int switch_to_phy_index1(struct dram_info *dram,\n \t\t\t\tconst struct rk3399_sdram_params *params)\n {\n@@ -1626,7 +1649,6 @@ static int sdram_init(struct dram_info *dram,\n {\n \tunsigned char dramtype = params->base.dramtype;\n \tunsigned int ddr_freq = params->base.ddr_freq;\n-\tu32 training_flag = PI_READ_GATE_TRAINING;\n \tint channel, ch, rank;\n \tint ret;\n \n@@ -1654,16 +1676,12 @@ static int sdram_init(struct dram_info *dram,\n \n \t\t\tparams->ch[ch].cap_info.rank = rank;\n \n-\t\t\t/*\n-\t\t\t * LPDDR3 CA training msut be trigger before\n-\t\t\t * other training.\n-\t\t\t * DDR3 is not have CA training.\n-\t\t\t */\n-\t\t\tif (params->base.dramtype == LPDDR3)\n-\t\t\t\ttraining_flag |= PI_CA_TRAINING;\n-\n-\t\t\tif (!(data_training(dram, ch, params, training_flag)))\n+\t\t\tret = dram->ops->data_training(dram, ch, rank, params);\n+\t\t\tif (!ret) {\n+\t\t\t\tdebug(\"%s: data trained for rank %d, ch %d\\n\",\n+\t\t\t\t __func__, rank, ch);\n \t\t\t\tbreak;\n+\t\t\t}\n \t\t}\n \t\t/* Computed rank with associated channel number */\n \t\tparams->ch[ch].cap_info.rank = rank;\n@@ -1743,6 +1761,10 @@ static int conv_of_platdata(struct udevice *dev)\n }\n #endif\n \n+static const struct sdram_rk3399_ops rk3399_ops = {\n+\t.data_training = default_data_training,\n+};\n+\n static int rk3399_dmc_init(struct udevice *dev)\n {\n \tstruct dram_info *priv = dev_get_priv(dev);\n@@ -1760,6 +1782,7 @@ static int rk3399_dmc_init(struct udevice *dev)\n \t\treturn ret;\n #endif\n \n+\tpriv->ops = &rk3399_ops;\n \tpriv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);\n \tpriv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);\n \tpriv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);\n", "prefixes": [ "U-Boot", "v3", "42/57" ] }