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GET /api/patches/1132676/?format=api
{ "id": 1132676, "url": "http://patchwork.ozlabs.org/api/patches/1132676/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190716115745.12585-35-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190716115745.12585-35-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2019-07-16T11:57:22", "name": "[U-Boot,v3,34/57] ram: sdram: Configure lpddr4 tsel rd, wr based on IO settings", "commit_ref": "2fb2de33b2d89442d08a7d69f6afb9c7e46aa992", "pull_url": null, "state": "accepted", "archived": false, "hash": "af44e7d7225190b1de779ae410a19f5dcdeb96a1", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 93623, "url": "http://patchwork.ozlabs.org/api/users/93623/?format=api", "username": "kevery", "first_name": "Kever", "last_name": "Yang", "email": "ykai007@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190716115745.12585-35-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 119754, "url": "http://patchwork.ozlabs.org/api/series/119754/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=119754", "date": "2019-07-16T11:56:48", "name": "ram: rk3399: Add LPDDR4 support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/119754/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1132676/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1132676/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"YoO5VsGt\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 45nzdy1YBGz9sNT\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 16 Jul 2019 22:06:45 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid B349EC21E3A; Tue, 16 Jul 2019 12:05:42 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 55A32C21E73;\n\tTue, 16 Jul 2019 12:02:53 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 22505C21D65; Tue, 16 Jul 2019 12:00:02 +0000 (UTC)", "from mail-pl1-f196.google.com (mail-pl1-f196.google.com\n\t[209.85.214.196])\n\tby lists.denx.de (Postfix) with ESMTPS id F20CBC21E38\n\tfor <u-boot@lists.denx.de>; Tue, 16 Jul 2019 11:59:58 +0000 (UTC)", "by mail-pl1-f196.google.com with SMTP id t14so9979288plr.11\n\tfor <u-boot@lists.denx.de>; Tue, 16 Jul 2019 04:59:58 -0700 (PDT)", "from localhost.localdomain ([49.206.201.107])\n\tby smtp.gmail.com with ESMTPSA id\n\tz24sm36269566pfr.51.2019.07.16.04.59.54\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tTue, 16 Jul 2019 04:59:57 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amarulasolutions.com; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=JMHA9/oGc0uz7sXCCFBrC03P2fQlwGuty6qYiMMD5M0=;\n\tb=YoO5VsGtwBkTbMLYpRP5BTMj7eCzp1I28rr80+2ZUTuaKCdckPEFmhMD3mHMIqNCws\n\tr1NGxRYR7oSXsf+5DgmnNMLMlHjVuFNLuM7iN9b/sg6ItlKL7aXdQppYMBiR6oiIc7pM\n\t95qihNZroRI7PJC1OXcWT1NakZUrp4Gdtq6qk=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=JMHA9/oGc0uz7sXCCFBrC03P2fQlwGuty6qYiMMD5M0=;\n\tb=PJCCLdZoXVPI8FrJoTO7NGry0z4dfPTnHLkJJ6Epo22qvaMOhPja0n29LnMluNRD4a\n\tWGqa4U7geZ6YKpRYr3GiygBoI/R6MPKPkm8cvXXBVScFzHfgAi2/A/0xAu/xlLpoYQ5m\n\tfcrGZ5EtpXCIPSV5jK8SB2HQ3ac8vzqOl0X+nGKrO65s/TnWJKUeKiUujTlZWX7Dcfr5\n\tJiG6KJoeHgm8KLm/bFezDwDcXBTO8rdCJQf7qGpmObij54AoVSSYxMTFhr+YCyCmFtNR\n\tKomTOSYRkWel7PF4Qop4x0OL5iU51ignlxpPiwjHDdc9OPKMwIl5Zdpb6uP/9AynqiPZ\n\tYgvw==", "X-Gm-Message-State": "APjAAAWI6ePKR9hJKp0DesZaLHEK/0pR3c/4MK/aCj/pkeY10yqBjLid\n\t4yi/AkkOzBYqqyKaCuGUDEdDKQ==", "X-Google-Smtp-Source": "APXvYqyv31DvNSS+iqSsC/55foaF7A+Jz8ubY/h1r4iFfzFX5wgt7pLmkjV2HxAnETXB6KmzrC3Niw==", "X-Received": "by 2002:a17:902:2aa9:: with SMTP id\n\tj38mr33237354plb.206.1563278397609; \n\tTue, 16 Jul 2019 04:59:57 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Simon Glass <sjg@chromium.org>,\n\tPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>,\n\tKever Yang <kever.yang@rock-chips.com>,\n\tYouMin Chen <cym@rock-chips.com>, u-boot@lists.denx.de", "Date": "Tue, 16 Jul 2019 17:27:22 +0530", "Message-Id": "<20190716115745.12585-35-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20190716115745.12585-1-jagan@amarulasolutions.com>", "References": "<20190716115745.12585-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com,\n\tlinux-amarula@amarulasolutions.com,\n\tManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>", "Subject": "[U-Boot] [PATCH v3 34/57] ram: sdram: Configure lpddr4 tsel rd,\n\twr based on IO settings", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Now we have IO settings available for all supported sdram\nfrequencies, so retrieve these IO settings and make used\nfor LPDDR4 ds odt configuration.\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\nSigned-off-by: YouMin Chen <cym@rock-chips.com>\n---\n drivers/ram/rockchip/sdram_rk3399.c | 42 ++++++++++++++++++++++++-----\n 1 file changed, 36 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c\nindex 95d9f3a88b..1b8ce5160f 100644\n--- a/drivers/ram/rockchip/sdram_rk3399.c\n+++ b/drivers/ram/rockchip/sdram_rk3399.c\n@@ -184,6 +184,33 @@ struct io_setting {\n \t},\n };\n \n+/**\n+ * phy = 0, PHY boot freq\n+ * phy = 1, PHY index 0\n+ * phy = 2, PHY index 1\n+ */\n+static struct io_setting *\n+lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5)\n+{\n+\tstruct io_setting *io = NULL;\n+\tu32 n;\n+\n+\tfor (n = 0; n < ARRAY_SIZE(lpddr4_io_setting); n++) {\n+\t\tio = &lpddr4_io_setting[n];\n+\n+\t\tif (io->mr5 != 0) {\n+\t\t\tif (io->mhz >= params->base.ddr_freq &&\n+\t\t\t io->mr5 == mr5)\n+\t\t\t\tbreak;\n+\t\t} else {\n+\t\t\tif (io->mhz >= params->base.ddr_freq)\n+\t\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn io;\n+}\n+\n static void *get_ddrc0_con(struct dram_info *dram, u8 channel)\n {\n \treturn (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;\n@@ -524,7 +551,7 @@ static int phy_io_config(const struct chan_info *chan,\n }\n \n static void set_ds_odt(const struct chan_info *chan,\n-\t\t const struct rk3399_sdram_params *params)\n+\t\t const struct rk3399_sdram_params *params, u32 mr5)\n {\n \tu32 *denali_phy = chan->publ->denali_phy;\n \n@@ -533,19 +560,22 @@ static void set_ds_odt(const struct chan_info *chan,\n \tu32 tsel_idle_select_n, tsel_rd_select_n;\n \tu32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;\n \tu32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;\n+\tstruct io_setting *io = NULL;\n \tu32 reg_value;\n \n \tif (params->base.dramtype == LPDDR4) {\n+\t\tio = lpddr4_get_io_settings(params, mr5);\n+\n \t\ttsel_rd_select_p = PHY_DRV_ODT_HI_Z;\n-\t\ttsel_rd_select_n = PHY_DRV_ODT_240;\n+\t\ttsel_rd_select_n = io->rd_odt;\n \n \t\ttsel_idle_select_p = PHY_DRV_ODT_HI_Z;\n \t\ttsel_idle_select_n = PHY_DRV_ODT_240;\n \n-\t\ttsel_wr_select_dq_p = PHY_DRV_ODT_40;\n+\t\ttsel_wr_select_dq_p = io->wr_dq_drv;\n \t\ttsel_wr_select_dq_n = PHY_DRV_ODT_40;\n \n-\t\ttsel_wr_select_ca_p = PHY_DRV_ODT_40;\n+\t\ttsel_wr_select_ca_p = io->wr_ca_drv;\n \t\ttsel_wr_select_ca_n = PHY_DRV_ODT_40;\n \t} else if (params->base.dramtype == LPDDR3) {\n \t\ttsel_rd_select_p = PHY_DRV_ODT_240;\n@@ -723,7 +753,7 @@ static void pctl_start(struct dram_info *dram, u8 channel)\n }\n \n static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,\n-\t\t u32 channel, const struct rk3399_sdram_params *params)\n+\t\t u32 channel, struct rk3399_sdram_params *params)\n {\n \tu32 *denali_ctl = chan->pctl->denali_ctl;\n \tu32 *denali_pi = chan->pi->denali_pi;\n@@ -805,7 +835,7 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,\n \tcopy_to_reg(&denali_phy[512], ¶ms_phy[512], (549 - 512 + 1) * 4);\n \tcopy_to_reg(&denali_phy[640], ¶ms_phy[640], (677 - 640 + 1) * 4);\n \tcopy_to_reg(&denali_phy[768], ¶ms_phy[768], (805 - 768 + 1) * 4);\n-\tset_ds_odt(chan, params);\n+\tset_ds_odt(chan, params, 0);\n \n \t/*\n \t * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8\n", "prefixes": [ "U-Boot", "v3", "34/57" ] }