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GET /api/patches/1132187/?format=api
{ "id": 1132187, "url": "http://patchwork.ozlabs.org/api/patches/1132187/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190715182856.21688-17-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190715182856.21688-17-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2019-07-15T18:28:54", "name": "[U-Boot,v3,16/18] ram: rk3399: Add rank detection support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "14a7d282638b0a4ddc80316539a1a758951ca765", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 93623, "url": "http://patchwork.ozlabs.org/api/users/93623/?format=api", "username": "kevery", "first_name": "Kever", "last_name": "Yang", "email": "ykai007@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190715182856.21688-17-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 119574, "url": "http://patchwork.ozlabs.org/api/series/119574/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=119574", "date": "2019-07-15T18:28:43", "name": "ram: rk3399: Add rank detection", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/119574/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1132187/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1132187/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"F9mZj79u\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 45nXHp4gppz9s4Y\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 16 Jul 2019 04:34:29 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid BCC16C21FB1; Mon, 15 Jul 2019 18:33:06 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 4D03EC21F4D;\n\tMon, 15 Jul 2019 18:31:01 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 7368BC21FA5; Mon, 15 Jul 2019 18:30:09 +0000 (UTC)", "from mail-pg1-f196.google.com (mail-pg1-f196.google.com\n\t[209.85.215.196])\n\tby lists.denx.de (Postfix) with ESMTPS id EC850C21FD9\n\tfor <u-boot@lists.denx.de>; Mon, 15 Jul 2019 18:30:05 +0000 (UTC)", "by mail-pg1-f196.google.com with SMTP id t132so8108149pgb.9\n\tfor <u-boot@lists.denx.de>; Mon, 15 Jul 2019 11:30:05 -0700 (PDT)", "from localhost.localdomain ([49.206.201.107])\n\tby smtp.gmail.com with ESMTPSA id\n\ty133sm20250075pfb.28.2019.07.15.11.30.01\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tMon, 15 Jul 2019 11:30:04 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amarulasolutions.com; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=sqbrOYwvlaoeOAcZLAQeQHRuttDiSnuSC+eoRb7//98=;\n\tb=F9mZj79uQ/4vbxriBi3/a5DIfCaPwC33hGnbenaHD2AKqeP9pNvkHxk8bW1amvGuIh\n\t22gmbfttALShfo5TyY8rVql1kfjwiT2NrCJ5Txxd0oJdhocrTuu+hRcmz40UPCWtBivd\n\txJ8WHOLBdPasxZ6LIp2aph04xlYUZtOGs9EpI=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=sqbrOYwvlaoeOAcZLAQeQHRuttDiSnuSC+eoRb7//98=;\n\tb=iSeVXFDNI/XJ8UjGjdOZrVzwvGzOPwUNLHWapWtaF8dNYU5ATO/9ncuvQ/cvUUGgDH\n\tlbGsJDQQway5K5NxtlW0xfLIpgN4C07KbxdfZYKzxY1xC8vy5El4tHMSYr8GHaRtQt1w\n\tWyND/uGNpQDNwvI2l0+jrOuuBFVGePlz9sn+o6c5qjOGwKAjRP6Bxlw0gENQpb9nX6+4\n\tHI7bM5sfmHWmb08nRGulTxxF+uvewP4T0vBZ4BOaQ2aEqlAiGAWQGby7YHJT05lO7qeQ\n\tIcSca/e42eT3aneUjv83UH0lc7au+cXC5qzyaTCQSMhjZJg9tt6EFiKj5mwNA4zpIqUk\n\tdHaA==", "X-Gm-Message-State": "APjAAAWnQ+ea1oelG9boXkGy2dKLVLlgPQ65rVEAe6gUnUV8snLNEtux\n\tURfsfK/xMm2JB7GgHeSU7i4L8g==", "X-Google-Smtp-Source": "APXvYqyX5FW1HrlEjn0zT84YqgHPFNR+S1tf2IaigsXYUWm5iHrzzNBg4QWDWqZRqERJe8WBuvcAVw==", "X-Received": "by 2002:a17:90a:35e6:: with SMTP id\n\tr93mr31007925pjb.20.1563215404504; \n\tMon, 15 Jul 2019 11:30:04 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Simon Glass <sjg@chromium.org>,\n\tPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>,\n\tKever Yang <kever.yang@rock-chips.com>,\n\tYouMin Chen <cym@rock-chips.com>, u-boot@lists.denx.de", "Date": "Mon, 15 Jul 2019 23:58:54 +0530", "Message-Id": "<20190715182856.21688-17-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20190715182856.21688-1-jagan@amarulasolutions.com>", "References": "<20190715182856.21688-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com,\n\tlinux-amarula@amarulasolutions.com,\n\tManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>", "Subject": "[U-Boot] [PATCH v3 16/18] ram: rk3399: Add rank detection support", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Right now the rk3399 sdram driver assume that the board\nhas configured with 2 channels, so any possibility to\nenable single channel on the same driver will encounter\nchannel #1 data training failure.\n\nLog:\nU-Boot TPL board init\nsdram_init: data training failed\nrk3399_dmc_init DRAM init failed -5\n\nSo, add an algorithm that can capable to compute the active\nor configured rank with associated channel like\na) do rank loop to compute the active rank, with associated\n channel numbers\nb) then, succeed the data training only for configured channel\nc) preserve the rank for given channel\nd) do channel loop for setting the active channel\ne) if given rank is zero or inactive on the specific channel,\n clear the timings for the associated channel\nf) finally, return error if number of channels is zero\n\nTested in NanoPI-NEO4 since it support single channel sdram\nconfiguration.\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\nSigned-off-by: YouMin Chen <cym@rock-chips.com>\n---\n drivers/ram/rockchip/sdram_rk3399.c | 110 ++++++++++++++++++++++------\n 1 file changed, 86 insertions(+), 24 deletions(-)", "diff": "diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c\nindex 8bbacb5275..b83955f94e 100644\n--- a/drivers/ram/rockchip/sdram_rk3399.c\n+++ b/drivers/ram/rockchip/sdram_rk3399.c\n@@ -1254,13 +1254,52 @@ static unsigned char calculate_stride(struct rk3399_sdram_params *params)\n \treturn stride;\n }\n \n+static void clear_channel_params(struct rk3399_sdram_params *params, u8 channel)\n+{\n+\tparams->ch[channel].cap_info.rank = 0;\n+\tparams->ch[channel].cap_info.col = 0;\n+\tparams->ch[channel].cap_info.bk = 0;\n+\tparams->ch[channel].cap_info.bw = 32;\n+\tparams->ch[channel].cap_info.dbw = 32;\n+\tparams->ch[channel].cap_info.row_3_4 = 0;\n+\tparams->ch[channel].cap_info.cs0_row = 0;\n+\tparams->ch[channel].cap_info.cs1_row = 0;\n+\tparams->ch[channel].cap_info.ddrconfig = 0;\n+}\n+\n+static int pctl_init(struct dram_info *dram, struct rk3399_sdram_params *params)\n+{\n+\tint channel;\n+\tint ret;\n+\n+\tfor (channel = 0; channel < 2; channel++) {\n+\t\tconst struct chan_info *chan = &dram->chan[channel];\n+\t\tstruct rk3399_cru *cru = dram->cru;\n+\t\tstruct rk3399_ddr_publ_regs *publ = chan->publ;\n+\n+\t\tphy_pctrl_reset(cru, channel);\n+\t\tphy_dll_bypass_set(publ, params->base.ddr_freq);\n+\n+\t\tret = pctl_cfg(dram, chan, channel, params);\n+\t\tif (ret < 0) {\n+\t\t\tprintf(\"%s: pctl config failed\\n\", __func__);\n+\t\t\treturn ret;\n+\t\t}\n+\n+\t\t/* start to trigger initialization */\n+\t\tpctl_start(dram, channel);\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int sdram_init(struct dram_info *dram,\n \t\t struct rk3399_sdram_params *params)\n {\n \tunsigned char dramtype = params->base.dramtype;\n \tunsigned int ddr_freq = params->base.ddr_freq;\n-\tstruct rk3399_cru *cru = dram->cru;\n-\tint channel;\n+\tu32 training_flag = PI_READ_GATE_TRAINING;\n+\tint channel, ch, rank;\n \tint ret;\n \n \tdebug(\"Starting SDRAM initialization...\\n\");\n@@ -1272,36 +1311,59 @@ static int sdram_init(struct dram_info *dram,\n \t\treturn -E2BIG;\n \t}\n \n-\tfor (channel = 0; channel < 2; channel++) {\n-\t\tconst struct chan_info *chan = &dram->chan[channel];\n-\t\tstruct rk3399_ddr_publ_regs *publ = chan->publ;\n+\tfor (ch = 0; ch < 2; ch++) {\n+\t\tparams->ch[ch].cap_info.rank = 2;\n+\t\tfor (rank = 2; rank != 0; rank--) {\n+\t\t\tret = pctl_init(dram, params);\n+\t\t\tif (ret < 0) {\n+\t\t\t\tprintf(\"%s: pctl init failed\\n\", __func__);\n+\t\t\t\treturn ret;\n+\t\t\t}\n \n-\t\tphy_pctrl_reset(cru, channel);\n-\t\tphy_dll_bypass_set(publ, ddr_freq);\n+\t\t\t/* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */\n+\t\t\tif (dramtype == LPDDR3)\n+\t\t\t\tudelay(10);\n \n-\t\tif (channel >= params->base.num_channels)\n-\t\t\tcontinue;\n+\t\t\tparams->ch[ch].cap_info.rank = rank;\n \n-\t\tret = pctl_cfg(dram, chan, channel, params);\n-\t\tif (ret < 0) {\n-\t\t\tprintf(\"%s: pctl config failed\\n\", __func__);\n-\t\t\treturn ret;\n-\t\t}\n+\t\t\t/*\n+\t\t\t * LPDDR3 CA training msut be trigger before\n+\t\t\t * other training.\n+\t\t\t * DDR3 is not have CA training.\n+\t\t\t */\n+\t\t\tif (params->base.dramtype == LPDDR3)\n+\t\t\t\ttraining_flag |= PI_CA_TRAINING;\n \n-\t\t/* start to trigger initialization */\n-\t\tpctl_start(dram, channel);\n+\t\t\tif (!(data_training(&dram->chan[ch], ch,\n+\t\t\t\t\t params, training_flag)))\n+\t\t\t\tbreak;\n+\t\t}\n+\t\t/* Computed rank with associated channel number */\n+\t\tparams->ch[ch].cap_info.rank = rank;\n+\t}\n \n-\t\t/* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */\n-\t\tif (dramtype == LPDDR3)\n-\t\t\tudelay(10);\n+\tparams->base.num_channels = 0;\n+\tfor (channel = 0; channel < 2; channel++) {\n+\t\tconst struct chan_info *chan = &dram->chan[channel];\n+\t\tstruct sdram_cap_info *cap_info = ¶ms->ch[channel].cap_info;\n \n-\t\tif (data_training(chan, channel, params, PI_FULL_TRAINING)) {\n-\t\t\tprintf(\"%s: data training failed\\n\", __func__);\n-\t\t\treturn -EIO;\n+\t\tif (cap_info->rank == 0) {\n+\t\t\tclear_channel_params(params, channel);\n+\t\t\tcontinue;\n+\t\t} else {\n+\t\t\tparams->base.num_channels++;\n \t\t}\n \n-\t\tset_ddrconfig(chan, params, channel,\n-\t\t\t params->ch[channel].cap_info.ddrconfig);\n+\t\tdebug(\"Channel \");\n+\t\tdebug(channel ? \"1: \" : \"0: \");\n+\n+\t\tset_ddrconfig(chan, params, channel, cap_info->ddrconfig);\n+\t}\n+\n+\tif (params->base.num_channels == 0) {\n+\t\tprintf(\"%s: \", __func__);\n+\t\tprintf(\" - %dMHz failed!\\n\", params->base.ddr_freq);\n+\t\treturn -EINVAL;\n \t}\n \n \tparams->base.stride = calculate_stride(params);\n", "prefixes": [ "U-Boot", "v3", "16/18" ] }