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GET /api/patches/1132186/?format=api
{ "id": 1132186, "url": "http://patchwork.ozlabs.org/api/patches/1132186/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190715182856.21688-8-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190715182856.21688-8-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2019-07-15T18:28:45", "name": "[U-Boot,v3,07/18] ram: rk3399: Add pctl start support", "commit_ref": "a0aebe8398415b03c8f3e31a886e4dcbf74b9a6e", "pull_url": null, "state": "accepted", "archived": false, "hash": "7b65a506f53c7eeb6f1980ce72c08a2c4acf9bf7", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 93623, "url": "http://patchwork.ozlabs.org/api/users/93623/?format=api", "username": "kevery", "first_name": "Kever", "last_name": "Yang", "email": "ykai007@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190715182856.21688-8-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 119574, "url": "http://patchwork.ozlabs.org/api/series/119574/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=119574", "date": "2019-07-15T18:28:43", "name": "ram: rk3399: Add rank detection", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/119574/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1132186/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1132186/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"ab8ad8He\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 45nXHp4grPz9sN4\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 16 Jul 2019 04:34:30 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid F0118C21FC7; Mon, 15 Jul 2019 18:31:35 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 3EF16C21FC0;\n\tMon, 15 Jul 2019 18:29:52 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 4DCAAC21F9E; Mon, 15 Jul 2019 18:29:35 +0000 (UTC)", "from mail-pf1-f194.google.com (mail-pf1-f194.google.com\n\t[209.85.210.194])\n\tby lists.denx.de (Postfix) with ESMTPS id 945F4C21FC1\n\tfor <u-boot@lists.denx.de>; Mon, 15 Jul 2019 18:29:34 +0000 (UTC)", "by mail-pf1-f194.google.com with SMTP id g2so7825790pfq.0\n\tfor <u-boot@lists.denx.de>; Mon, 15 Jul 2019 11:29:34 -0700 (PDT)", "from localhost.localdomain ([49.206.201.107])\n\tby smtp.gmail.com with ESMTPSA id\n\ty133sm20250075pfb.28.2019.07.15.11.29.29\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tMon, 15 Jul 2019 11:29:32 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amarulasolutions.com; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=Cdy1dxv9t+oHKqeWpvE9O/P4Jm0ldwmB6m0flnPmlmM=;\n\tb=ab8ad8HeA/rIazW2Hr8sjikzhjjOaiOPsG8U7+0nkn8iA9kMXdpMMfUnOqvL3TJAVY\n\txVvuzffYrKGD3u7dMMAqF+hx0iES8tKkqqbNtm+5hxjPl/d3BJvLF9UYwSvCADewR+lt\n\tHB+yv4Mg9hOzyfqfevZJzyiE6Vw8v4TgMYMXY=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=Cdy1dxv9t+oHKqeWpvE9O/P4Jm0ldwmB6m0flnPmlmM=;\n\tb=cqSXem32oix+3hCD/KBjdXDJW1SWMxq9cMhFlm7sn34Cec7l68inx0uwx7UNm+ipDY\n\tfvPbF44maze08uEZ3CPTFkyTa6H1KOv/AjuQaWAxAb4C2T9ZUAx9iwCBdOx24w887caI\n\t8TCovshoJgXq76fgJgpX1p7T20NUxIKhJepA0X1YSHWXu/tzUFV8uQ21zq63kJTi44+y\n\tf4s2GB7Jq5JvnjD+xWmcBC5hJXapaVJqfhgBdALitFrfq3UuYhnNBJ9r8SnXhe8sKSfi\n\tTqUbGeENxrmcSXwEg6rs8u8M+nHVYGv+bjpVu/NooV65/NkSd/mDf4Oh47x0JM1qA7vn\n\tQaWw==", "X-Gm-Message-State": "APjAAAWYb4mn1jlfPQwVI0T1N3TBlVRrzxGh44TQ4KjxhWEpxe95rwkf\n\tBbyoCfV9/EFccUTTbSOvhaFUVQ==", "X-Google-Smtp-Source": "APXvYqwo5zstpG6kDfKbHc2egHCQm/+c9TRLrpD/gcFfrIuqaCgDq1DTO0M+Zp6y32qY6Qfg1C9fvg==", "X-Received": "by 2002:a17:90a:b387:: with SMTP id\n\te7mr31826321pjr.113.1563215373177; \n\tMon, 15 Jul 2019 11:29:33 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Simon Glass <sjg@chromium.org>,\n\tPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>,\n\tKever Yang <kever.yang@rock-chips.com>,\n\tYouMin Chen <cym@rock-chips.com>, u-boot@lists.denx.de", "Date": "Mon, 15 Jul 2019 23:58:45 +0530", "Message-Id": "<20190715182856.21688-8-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20190715182856.21688-1-jagan@amarulasolutions.com>", "References": "<20190715182856.21688-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com,\n\tlinux-amarula@amarulasolutions.com,\n\tManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>", "Subject": "[U-Boot] [PATCH v3 07/18] ram: rk3399: Add pctl start support", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Add support for pctl start for both channel 0, 1 control\nand phy registers.\n\nThis would also handle pwrup_srefresh_exit init based\non the channel number.\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\nSigned-off-by: YouMin Chen <cym@rock-chips.com>\n---\n drivers/ram/rockchip/sdram_rk3399.c | 75 +++++++++++++++++++++--------\n 1 file changed, 55 insertions(+), 20 deletions(-)", "diff": "diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c\nindex 6e944cafd9..084c949728 100644\n--- a/drivers/ram/rockchip/sdram_rk3399.c\n+++ b/drivers/ram/rockchip/sdram_rk3399.c\n@@ -49,10 +49,11 @@ struct chan_info {\n struct dram_info {\n #if defined(CONFIG_TPL_BUILD) || \\\n \t(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))\n-\tu32 pwrup_srefresh_exit;\n+\tu32 pwrup_srefresh_exit[2];\n \tstruct chan_info chan[2];\n \tstruct clk ddr_clk;\n \tstruct rk3399_cru *cru;\n+\tstruct rk3399_grf_regs *grf;\n \tstruct rk3399_pmucru *pmucru;\n \tstruct rk3399_pmusgrf_regs *pmusgrf;\n \tstruct rk3399_ddr_cic_regs *cic;\n@@ -73,6 +74,11 @@ struct rockchip_dmc_plat {\n \tstruct regmap *map;\n };\n \n+static void *get_ddrc0_con(struct dram_info *dram, u8 channel)\n+{\n+\treturn (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc0_con1;\n+}\n+\n static void copy_to_reg(u32 *dest, const u32 *src, u32 n)\n {\n \tint i;\n@@ -328,6 +334,48 @@ static void set_ds_odt(const struct chan_info *chan,\n \tclrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);\n }\n \n+static void pctl_start(struct dram_info *dram, u8 channel)\n+{\n+\tconst struct chan_info *chan = &dram->chan[channel];\n+\tu32 *denali_ctl = chan->pctl->denali_ctl;\n+\tu32 *denali_phy = chan->publ->denali_phy;\n+\tu32 *ddrc0_con = get_ddrc0_con(dram, channel);\n+\tu32 count = 0;\n+\tu32 byte, tmp;\n+\n+\twritel(0x01000000, &ddrc0_con);\n+\n+\tclrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);\n+\n+\twhile (!(readl(&denali_ctl[203]) & (1 << 3))) {\n+\t\tif (count > 1000) {\n+\t\t\tprintf(\"%s: Failed to init pctl for channel %d\\n\",\n+\t\t\t __func__, channel);\n+\t\t\twhile (1)\n+\t\t\t\t;\n+\t\t}\n+\n+\t\tudelay(1);\n+\t\tcount++;\n+\t}\n+\n+\twritel(0x01000100, &ddrc0_con);\n+\n+\tfor (byte = 0; byte < 4; byte++) {\n+\t\ttmp = 0x820;\n+\t\twritel((tmp << 16) | tmp, &denali_phy[53 + (128 * byte)]);\n+\t\twritel((tmp << 16) | tmp, &denali_phy[54 + (128 * byte)]);\n+\t\twritel((tmp << 16) | tmp, &denali_phy[55 + (128 * byte)]);\n+\t\twritel((tmp << 16) | tmp, &denali_phy[56 + (128 * byte)]);\n+\t\twritel((tmp << 16) | tmp, &denali_phy[57 + (128 * byte)]);\n+\n+\t\tclrsetbits_le32(&denali_phy[58 + (128 * byte)], 0xffff, tmp);\n+\t}\n+\n+\tclrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,\n+\t\t\tdram->pwrup_srefresh_exit[channel]);\n+}\n+\n static int phy_io_config(const struct chan_info *chan,\n \t\t\t const struct rk3399_sdram_params *params)\n {\n@@ -498,7 +546,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,\n \tconst u32 *params_phy = params->phy_regs.denali_phy;\n \tu32 tmp, tmp1, tmp2;\n \tint ret;\n-\tconst ulong timeout_ms = 200;\n \n \t/*\n \t * work around controller bug:\n@@ -518,8 +565,8 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,\n \twritel(params->phy_regs.denali_phy[911], &denali_phy[911]);\n \twritel(params->phy_regs.denali_phy[912], &denali_phy[912]);\n \n-\tdram->pwrup_srefresh_exit = readl(&denali_ctl[68]) &\n-\t\t\t\t PWRUP_SREFRESH_EXIT;\n+\tdram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) &\n+\t\t\t\t\t PWRUP_SREFRESH_EXIT;\n \tclrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);\n \n \t/* PHY_DLL_RST_EN */\n@@ -580,22 +627,6 @@ static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,\n \tif (ret)\n \t\treturn ret;\n \n-\t/* PHY_DLL_RST_EN */\n-\tclrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);\n-\n-\t/* Waiting for PHY and DRAM init complete */\n-\ttmp = get_timer(0);\n-\tdo {\n-\t\tif (get_timer(tmp) > timeout_ms) {\n-\t\t\tpr_err(\"DRAM (%s): phy failed to lock within %ld ms\\n\",\n-\t\t\t __func__, timeout_ms);\n-\t\t\treturn -ETIME;\n-\t\t}\n-\t} while (!(readl(&denali_ctl[203]) & (1 << 3)));\n-\tdebug(\"DRAM (%s): phy locked after %ld ms\\n\", __func__, get_timer(tmp));\n-\n-\tclrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT,\n-\t\t\tdram->pwrup_srefresh_exit);\n \treturn 0;\n }\n \n@@ -1186,6 +1217,9 @@ static int sdram_init(struct dram_info *dram,\n \t\t\treturn ret;\n \t\t}\n \n+\t\t/* start to trigger initialization */\n+\t\tpctl_start(dram, channel);\n+\n \t\t/* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */\n \t\tif (dramtype == LPDDR3)\n \t\t\tudelay(10);\n@@ -1262,6 +1296,7 @@ static int rk3399_dmc_init(struct udevice *dev)\n #endif\n \n \tpriv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);\n+\tpriv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);\n \tpriv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);\n \tpriv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);\n \tpriv->pmucru = rockchip_get_pmucru();\n", "prefixes": [ "U-Boot", "v3", "07/18" ] }