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GET /api/patches/1132177/?format=api
{ "id": 1132177, "url": "http://patchwork.ozlabs.org/api/patches/1132177/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190715182110.21336-11-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190715182110.21336-11-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2019-07-15T18:21:05", "name": "[U-Boot,v3,10/15] ram: rockchip: rk3399: Add cap_info structure", "commit_ref": "355490dc5c03f42033efd55940d3a6192b70656d", "pull_url": null, "state": "accepted", "archived": false, "hash": "9f337fb49f9b8ec678bbbfaa834f33501884d3b9", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 93623, "url": "http://patchwork.ozlabs.org/api/users/93623/?format=api", "username": "kevery", "first_name": "Kever", "last_name": "Yang", "email": "ykai007@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190715182110.21336-11-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 119571, "url": "http://patchwork.ozlabs.org/api/series/119571/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=119571", "date": "2019-07-15T18:20:55", "name": "ram: rk3399: Code cleanup", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/119571/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1132177/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1132177/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"JUmjZMbz\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 45nX9Y1yK4z9s3l\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 16 Jul 2019 04:29:05 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid DA133C21FAC; Mon, 15 Jul 2019 18:24:59 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 41AEAC21FB6;\n\tMon, 15 Jul 2019 18:24:11 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 80636C21F3D; Mon, 15 Jul 2019 18:22:06 +0000 (UTC)", "from mail-pg1-f195.google.com (mail-pg1-f195.google.com\n\t[209.85.215.195])\n\tby lists.denx.de (Postfix) with ESMTPS id E4DA1C21F94\n\tfor <u-boot@lists.denx.de>; Mon, 15 Jul 2019 18:21:56 +0000 (UTC)", "by mail-pg1-f195.google.com with SMTP id s1so1798111pgr.2\n\tfor <u-boot@lists.denx.de>; Mon, 15 Jul 2019 11:21:56 -0700 (PDT)", "from localhost.localdomain ([49.206.201.107])\n\tby smtp.gmail.com with ESMTPSA id\n\tl15sm18152405pgf.5.2019.07.15.11.21.52\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tMon, 15 Jul 2019 11:21:55 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=T_DKIM_INVALID\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amarulasolutions.com; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=+9/anVDS7Q12usMSqx4jEVXDSHZX9ttjNc+q4flrxR8=;\n\tb=JUmjZMbzG39U/XR0iu81iAMozMol0P2mR0HQJjNm3LV8w/Nm8T1SbulnQ3mDSSLd6N\n\t4uwjaTCodTfj02JfuR7A4hNCIuNxA2wUpcyOTMWUoVTfk0cdZCoS0KmLUQdiMIum0Fck\n\to0jGqgjtJ+iBHE3JyqvFzlBOgOgDhu0bGtNUg=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=+9/anVDS7Q12usMSqx4jEVXDSHZX9ttjNc+q4flrxR8=;\n\tb=EjdhEG7TgcbWbUpMOQXqZJOC7WykYxzaicfXfRP7Rqi+kexbWt96Wj0jLbWx7uRs/j\n\tsF9+VpR53sbEN4R/fiPb5LMyEfXybhiwDrcL2uzxZpU57e/Dhq0FORLrfvIegJIQ5ljo\n\t6d5NYTM/hM3fbOiVhU86vURSzNb562r5VJQw+mz75O3H65Hw/VIdsEClXy16y+j1VCET\n\t5DcoqZroX6/p/S4zsVsRddPJOR25BErean0fLGdCkYr4i+BfHMBsJsZrVy54+2sXSUEN\n\tVpNRRMrENLndg/Vts/W4OXWtFDiQEShOcVljDv7vCZqI2C4cbR9TgfmF9zUYpN6qpKRJ\n\t/bUA==", "X-Gm-Message-State": "APjAAAX+JOn90U9WbQd452tjPfIjCkf0srS9z1ga1bEcIjIEBKMRuu/S\n\t+PdVhLZKsYUeZQFm0bzOcxl69g==", "X-Google-Smtp-Source": "APXvYqzXa2HeqBnsh+LwHLaAz3Ao2m3ur9k9d2aUd7yeJL71bS+fQOfMomsvB+FP73nF8OIGDEf/rw==", "X-Received": "by 2002:a63:9c5:: with SMTP id 188mr3258004pgj.2.1563214915446; \n\tMon, 15 Jul 2019 11:21:55 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Simon Glass <sjg@chromium.org>,\n\tPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>,\n\tKever Yang <kever.yang@rock-chips.com>,\n\tYouMin Chen <cym@rock-chips.com>, u-boot@lists.denx.de", "Date": "Mon, 15 Jul 2019 23:51:05 +0530", "Message-Id": "<20190715182110.21336-11-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20190715182110.21336-1-jagan@amarulasolutions.com>", "References": "<20190715182110.21336-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com,\n\tlinux-amarula@amarulasolutions.com,\n\tManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>", "Subject": "[U-Boot] [PATCH v3 10/15] ram: rockchip: rk3399: Add cap_info\n\tstructure", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Group common ddr attributes like\n- rank\n- col\n- bk\n- bw\n- dbw\n- row_3_4\n- cs0_row\n- cs1_row\n- ddrconfig\n\ninto a common cap_info structure for more code readability and extend\nif possible based on the new features.\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\n---\n .../include/asm/arch-rockchip/sdram_rk3399.h | 6 +-\n drivers/ram/rockchip/sdram_rk3399.c | 73 ++++++++++---------\n 2 files changed, 45 insertions(+), 34 deletions(-)", "diff": "diff --git a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h\nindex c6a260bad8..683093d4ca 100644\n--- a/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h\n+++ b/arch/arm/include/asm/arch-rockchip/sdram_rk3399.h\n@@ -71,7 +71,7 @@ struct rk3399_ddr_cic_regs {\n /* DENALI_CTL_274 */\n #define MEM_RST_VALID\t1\n \n-struct rk3399_sdram_channel {\n+struct sdram_cap_info {\n \tunsigned int rank;\n \t/* dram column number, 0 means this channel is invalid */\n \tunsigned int col;\n@@ -89,6 +89,10 @@ struct rk3399_sdram_channel {\n \tunsigned int cs0_row;\n \tunsigned int cs1_row;\n \tunsigned int ddrconfig;\n+};\n+\n+struct rk3399_sdram_channel {\n+\tstruct sdram_cap_info cap_info;\n \tstruct rk3399_msch_timings noc_timings;\n };\n \ndiff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c\nindex 043b27737d..492b0975dd 100644\n--- a/drivers/ram/rockchip/sdram_rk3399.c\n+++ b/drivers/ram/rockchip/sdram_rk3399.c\n@@ -121,35 +121,36 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,\n \tu32 row;\n \n \t/* Get row number from ddrconfig setting */\n-\tif (sdram_ch->ddrconfig < 2 || sdram_ch->ddrconfig == 4)\n+\tif (sdram_ch->cap_info.ddrconfig < 2 ||\n+\t sdram_ch->cap_info.ddrconfig == 4)\n \t\trow = 16;\n-\telse if (sdram_ch->ddrconfig == 3)\n+\telse if (sdram_ch->cap_info.ddrconfig == 3)\n \t\trow = 14;\n \telse\n \t\trow = 15;\n \n-\tcs_map = (sdram_ch->rank > 1) ? 3 : 1;\n-\treduc = (sdram_ch->bw == 2) ? 0 : 1;\n+\tcs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1;\n+\treduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1;\n \n \t/* Set the dram configuration to ctrl */\n-\tclrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->col));\n+\tclrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col));\n \tclrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),\n-\t\t\t((3 - sdram_ch->bk) << 16) |\n+\t\t\t((3 - sdram_ch->cap_info.bk) << 16) |\n \t\t\t((16 - row) << 24));\n \n \tclrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16),\n \t\t\tcs_map | (reduc << 16));\n \n \t/* PI_199 PI_COL_DIFF:RW:0:4 */\n-\tclrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->col));\n+\tclrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col));\n \n \t/* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */\n \tclrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),\n-\t\t\t((3 - sdram_ch->bk) << 16) |\n+\t\t\t((3 - sdram_ch->cap_info.bk) << 16) |\n \t\t\t((16 - row) << 24));\n \t/* PI_41 PI_CS_MAP:RW:24:4 */\n \tclrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);\n-\tif (sdram_ch->rank == 1 && params->base.dramtype == DDR3)\n+\tif (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3)\n \t\twritel(0x2EC7FFFF, &denali_pi[34]);\n }\n \n@@ -624,7 +625,7 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,\n \tu32 *denali_phy = chan->publ->denali_phy;\n \tu32 i, tmp;\n \tu32 obs_0, obs_1, obs_2, obs_err = 0;\n-\tu32 rank = params->ch[channel].rank;\n+\tu32 rank = params->ch[channel].cap_info.rank;\n \n \tfor (i = 0; i < rank; i++) {\n \t\tselect_per_cs_training_index(chan, i);\n@@ -678,7 +679,7 @@ static int data_training_wl(const struct chan_info *chan, u32 channel,\n \tu32 *denali_phy = chan->publ->denali_phy;\n \tu32 i, tmp;\n \tu32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;\n-\tu32 rank = params->ch[channel].rank;\n+\tu32 rank = params->ch[channel].cap_info.rank;\n \n \tfor (i = 0; i < rank; i++) {\n \t\tselect_per_cs_training_index(chan, i);\n@@ -737,7 +738,7 @@ static int data_training_rg(const struct chan_info *chan, u32 channel,\n \tu32 *denali_phy = chan->publ->denali_phy;\n \tu32 i, tmp;\n \tu32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;\n-\tu32 rank = params->ch[channel].rank;\n+\tu32 rank = params->ch[channel].cap_info.rank;\n \n \tfor (i = 0; i < rank; i++) {\n \t\tselect_per_cs_training_index(chan, i);\n@@ -796,7 +797,7 @@ static int data_training_rl(const struct chan_info *chan, u32 channel,\n {\n \tu32 *denali_pi = chan->pi->denali_pi;\n \tu32 i, tmp;\n-\tu32 rank = params->ch[channel].rank;\n+\tu32 rank = params->ch[channel].cap_info.rank;\n \n \tfor (i = 0; i < rank; i++) {\n \t\tselect_per_cs_training_index(chan, i);\n@@ -841,7 +842,7 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,\n {\n \tu32 *denali_pi = chan->pi->denali_pi;\n \tu32 i, tmp;\n-\tu32 rank = params->ch[channel].rank;\n+\tu32 rank = params->ch[channel].cap_info.rank;\n \n \tfor (i = 0; i < rank; i++) {\n \t\tselect_per_cs_training_index(chan, i);\n@@ -940,14 +941,14 @@ static void set_ddrconfig(const struct chan_info *chan,\n \tunsigned int cs0_cap = 0;\n \tunsigned int cs1_cap = 0;\n \n-\tcs0_cap = (1 << (params->ch[channel].cs0_row\n-\t\t\t+ params->ch[channel].col\n-\t\t\t+ params->ch[channel].bk\n-\t\t\t+ params->ch[channel].bw - 20));\n-\tif (params->ch[channel].rank > 1)\n-\t\tcs1_cap = cs0_cap >> (params->ch[channel].cs0_row\n-\t\t\t\t- params->ch[channel].cs1_row);\n-\tif (params->ch[channel].row_3_4) {\n+\tcs0_cap = (1 << (params->ch[channel].cap_info.cs0_row\n+\t\t\t+ params->ch[channel].cap_info.col\n+\t\t\t+ params->ch[channel].cap_info.bk\n+\t\t\t+ params->ch[channel].cap_info.bw - 20));\n+\tif (params->ch[channel].cap_info.rank > 1)\n+\t\tcs1_cap = cs0_cap >> (params->ch[channel].cap_info.cs0_row\n+\t\t\t\t- params->ch[channel].cap_info.cs1_row);\n+\tif (params->ch[channel].cap_info.row_3_4) {\n \t\tcs0_cap = cs0_cap * 3 / 4;\n \t\tcs1_cap = cs1_cap * 3 / 4;\n \t}\n@@ -973,20 +974,26 @@ static void dram_all_config(struct dram_info *dram,\n \t\tstruct rk3399_msch_regs *ddr_msch_regs;\n \t\tconst struct rk3399_msch_timings *noc_timing;\n \n-\t\tif (params->ch[channel].col == 0)\n+\t\tif (params->ch[channel].cap_info.col == 0)\n \t\t\tcontinue;\n \t\tidx++;\n-\t\tsys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(channel);\n+\t\tsys_reg |= info->cap_info.row_3_4 <<\n+\t\t\t SYS_REG_ROW_3_4_SHIFT(channel);\n \t\tsys_reg |= 1 << SYS_REG_CHINFO_SHIFT(channel);\n-\t\tsys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel);\n-\t\tsys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel);\n-\t\tsys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel);\n-\t\tsys_reg |= (info->cs0_row - 13) <<\n+\t\tsys_reg |= (info->cap_info.rank - 1) <<\n+\t\t\t SYS_REG_RANK_SHIFT(channel);\n+\t\tsys_reg |= (info->cap_info.col - 9) <<\n+\t\t\t SYS_REG_COL_SHIFT(channel);\n+\t\tsys_reg |= info->cap_info.bk == 3 ? 0 : 1 <<\n+\t\t\t SYS_REG_BK_SHIFT(channel);\n+\t\tsys_reg |= (info->cap_info.cs0_row - 13) <<\n \t\t\t SYS_REG_CS0_ROW_SHIFT(channel);\n-\t\tsys_reg |= (info->cs1_row - 13) <<\n+\t\tsys_reg |= (info->cap_info.cs1_row - 13) <<\n \t\t\t SYS_REG_CS1_ROW_SHIFT(channel);\n-\t\tsys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel);\n-\t\tsys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel);\n+\t\tsys_reg |= (2 >> info->cap_info.bw) <<\n+\t\t\t SYS_REG_BW_SHIFT(channel);\n+\t\tsys_reg |= (2 >> info->cap_info.dbw) <<\n+\t\t\t SYS_REG_DBW_SHIFT(channel);\n \n \t\tddr_msch_regs = dram->chan[channel].msch;\n \t\tnoc_timing = ¶ms->ch[channel].noc_timings;\n@@ -1002,7 +1009,7 @@ static void dram_all_config(struct dram_info *dram,\n \t\t &ddr_msch_regs->ddrmode);\n \n \t\t/* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */\n-\t\tif (params->ch[channel].rank == 1)\n+\t\tif (params->ch[channel].cap_info.rank == 1)\n \t\t\tsetbits_le32(&dram->chan[channel].pctl->denali_ctl[276],\n \t\t\t\t 1 << 17);\n \t}\n@@ -1106,7 +1113,7 @@ static int sdram_init(struct dram_info *dram,\n \t\t}\n \n \t\tset_ddrconfig(chan, params, channel,\n-\t\t\t params->ch[channel].ddrconfig);\n+\t\t\t params->ch[channel].cap_info.ddrconfig);\n \t}\n \tdram_all_config(dram, params);\n \tswitch_to_phy_index1(dram, params);\n", "prefixes": [ "U-Boot", "v3", "10/15" ] }