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GET /api/patches/1132176/?format=api
{ "id": 1132176, "url": "http://patchwork.ozlabs.org/api/patches/1132176/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190715182110.21336-16-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190715182110.21336-16-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2019-07-15T18:21:10", "name": "[U-Boot,v3,15/15] clk: rockchip: rk3399: Fix check patch warnings and checks", "commit_ref": "dd7dfa217e799007f11f4649396d86ad8a40f95b", "pull_url": null, "state": "accepted", "archived": false, "hash": "936ff9255abbe2d56a33d0025e9d9104f0d56f31", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 93623, "url": "http://patchwork.ozlabs.org/api/users/93623/?format=api", "username": "kevery", "first_name": "Kever", "last_name": "Yang", "email": "ykai007@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190715182110.21336-16-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 119571, "url": "http://patchwork.ozlabs.org/api/series/119571/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=119571", "date": "2019-07-15T18:20:55", "name": "ram: rk3399: Code cleanup", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/119571/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1132176/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1132176/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"gMxdg588\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 45nX992fWjz9s00\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 16 Jul 2019 04:28:45 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 02E79C21FC7; Mon, 15 Jul 2019 18:24:29 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id DF131C21FAE;\n\tMon, 15 Jul 2019 18:23:56 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid C61A1C21EA2; Mon, 15 Jul 2019 18:22:22 +0000 (UTC)", "from mail-pf1-f196.google.com (mail-pf1-f196.google.com\n\t[209.85.210.196])\n\tby lists.denx.de (Postfix) with ESMTPS id C7124C21FC0\n\tfor <u-boot@lists.denx.de>; Mon, 15 Jul 2019 18:22:13 +0000 (UTC)", "by mail-pf1-f196.google.com with SMTP id b13so7810026pfo.1\n\tfor <u-boot@lists.denx.de>; Mon, 15 Jul 2019 11:22:13 -0700 (PDT)", "from localhost.localdomain ([49.206.201.107])\n\tby smtp.gmail.com with ESMTPSA id\n\tl15sm18152405pgf.5.2019.07.15.11.22.09\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tMon, 15 Jul 2019 11:22:11 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amarulasolutions.com; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=jYVJfJji5VncNUtRfq/ZDyMh3tw9MhBZTI5H0xl5J+I=;\n\tb=gMxdg588QAdzdeDAlHZRWXJ1LwvrnKaF50HXKA96FnQx8DM4ChzZNY41hD6SJ0ZqI7\n\t187yrSsUSMlq9Iz69qnoVUnnRf/GJwGfmZowSaajp8OSerquql4JGhINZQwSxzZ2VQw3\n\t4T1jG8Pd36M26NzV5tAkJR+ijuHcKZlkmuMk0=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=jYVJfJji5VncNUtRfq/ZDyMh3tw9MhBZTI5H0xl5J+I=;\n\tb=shyViPTA7pu/fBAhMD3bJR8M2MLbcyS1TnmxJXTGdkorKtyNTQR2D7H7D4xrBQ64bE\n\tLtcAq10Q1KhoQ1JJ/PkdNnLQZhU1vYb0n+mIYshYho2YAosnWD5qz0XxDkzlrwGwa4W/\n\tcY1GQeceG/vwS+UHYRZRLbl9daUwredQfjg/F2/hGO1UarRvptHsaLalV8pTUX200Mw3\n\t0pAG4wcWajDqKUR6CBJSlqXe9vYBA1U3z4KDMgbP4mSalkl0V62/9ikp6pYadEJvthD2\n\tPJkWLEy+AeTrSWwVBDZBZwrdeyVxMg90dloKzXquMqHvqR5p3PRe9RLZ9yOgsBhyUa5d\n\tcRrQ==", "X-Gm-Message-State": "APjAAAXSXmTXUF6rzLlbVrYHD8Nw4sfSpklf0bnQ6SdjOzE1c+7HsLcl\n\tfLvn0mmxzRcHngy2mbnodxdbkQ==", "X-Google-Smtp-Source": "APXvYqzGuI0WlfdgrQ09DVV3XO2neetyULjE0gKIcNd2Q20h5gKVIYZdg6UlZHb37hGc2X83fvgczA==", "X-Received": "by 2002:a63:d448:: with SMTP id i8mr9009773pgj.173.1563214932294;\n\tMon, 15 Jul 2019 11:22:12 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Simon Glass <sjg@chromium.org>,\n\tPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>,\n\tKever Yang <kever.yang@rock-chips.com>,\n\tYouMin Chen <cym@rock-chips.com>, u-boot@lists.denx.de", "Date": "Mon, 15 Jul 2019 23:51:10 +0530", "Message-Id": "<20190715182110.21336-16-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20190715182110.21336-1-jagan@amarulasolutions.com>", "References": "<20190715182110.21336-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com,\n\tlinux-amarula@amarulasolutions.com,\n\tManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>", "Subject": "[U-Boot] [PATCH v3 15/15] clk: rockchip: rk3399: Fix check patch\n\twarnings and checks", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "- CHECK: spaces preferred around that '*'\n- CHECK: spaces preferred around that '/'\n- CHECK: space preferred before that '|'\n- WARNING: macros should not use a trailing semicolon\n- CHECK: Unnecessary parentheses around 'fbdiv <= min_fbdiv'\n- CHECK: Unnecessary parentheses around 'parent->id == SCLK_MAC'\n- CHECK: Unnecessary parentheses around 'parent->dev == clk->dev'\n- WARNING: line over 80 characters\n- CHECK: Prefer kernel type 'u8' over 'uint8_t'\n- Add proper macro definitions arrangements\n\nNote: there are still line over 80 characters and other warnings but\nfixing those making code look unreadable, so I kept it as it is.\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\n---\n drivers/clk/rockchip/clk_rk3399.c | 68 ++++++++++++++-----------------\n 1 file changed, 31 insertions(+), 37 deletions(-)", "diff": "diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c\nindex aa6a8ad1c9..5d1ad94e85 100644\n--- a/drivers/clk/rockchip/clk_rk3399.c\n+++ b/drivers/clk/rockchip/clk_rk3399.c\n@@ -38,8 +38,8 @@ struct pll_div {\n };\n \n #define RATE_TO_DIV(input_rate, output_rate) \\\n-\t((input_rate) / (output_rate) - 1);\n-#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))\n+\t((input_rate) / (output_rate) - 1)\n+#define DIV_TO_RATE(input_rate, div)\t\t((input_rate) / ((div) + 1))\n \n #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\\\n \t.refdiv = _refdiv,\\\n@@ -53,15 +53,15 @@ static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);\n static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);\n #endif\n \n-static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1);\n-static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);\n+static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600 * MHz, 3, 1, 1);\n+static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);\n \n static const struct pll_div *apll_l_cfgs[] = {\n \t[APLL_L_1600_MHZ] = &apll_l_1600_cfg,\n \t[APLL_L_600_MHZ] = &apll_l_600_cfg,\n };\n \n-static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);\n+static const struct pll_div apll_b_600_cfg = PLL_DIVISORS(600 * MHz, 1, 2, 1);\n static const struct pll_div *apll_b_cfgs[] = {\n \t[APLL_B_600_MHZ] = &apll_b_600_cfg,\n };\n@@ -393,7 +393,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div)\n \t\tfref_khz = ref_khz / refdiv;\n \n \t\tfbdiv = vco_khz / fref_khz;\n-\t\tif ((fbdiv >= max_fbdiv) || (fbdiv <= min_fbdiv))\n+\t\tif (fbdiv >= max_fbdiv || fbdiv <= min_fbdiv)\n \t\t\tcontinue;\n \t\tdiff_khz = vco_khz - fbdiv * fref_khz;\n \t\tif (fbdiv + 1 < max_fbdiv && diff_khz > fref_khz / 2) {\n@@ -409,7 +409,7 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div)\n \t\tdiv->fbdiv = fbdiv;\n \t}\n \n-\tif (best_diff_khz > 4 * (MHz/KHz)) {\n+\tif (best_diff_khz > 4 * (MHz / KHz)) {\n \t\tprintf(\"%s: Failed to match output frequency %u, \"\n \t\t \"difference is %u Hz,exceed 4MHZ\\n\", __func__, freq_hz,\n \t\t best_diff_khz * KHz);\n@@ -489,28 +489,21 @@ void rk3399_configure_cpu_b(struct rk3399_cru *cru,\n }\n \n #define I2C_CLK_REG_MASK(bus) \\\n-\t\t\t(I2C_DIV_CON_MASK << \\\n-\t\t\tCLK_I2C ##bus## _DIV_CON_SHIFT | \\\n-\t\t\tCLK_I2C_PLL_SEL_MASK << \\\n-\t\t\tCLK_I2C ##bus## _PLL_SEL_SHIFT)\n+\t(I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT | \\\n+\t CLK_I2C_PLL_SEL_MASK << CLK_I2C ##bus## _PLL_SEL_SHIFT)\n \n #define I2C_CLK_REG_VALUE(bus, clk_div) \\\n-\t\t\t ((clk_div - 1) << \\\n-\t\t\t\t\tCLK_I2C ##bus## _DIV_CON_SHIFT | \\\n-\t\t\t CLK_I2C_PLL_SEL_GPLL << \\\n-\t\t\t\t\tCLK_I2C ##bus## _PLL_SEL_SHIFT)\n+\t((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT | \\\n+\t CLK_I2C_PLL_SEL_GPLL << CLK_I2C ##bus## _PLL_SEL_SHIFT)\n \n #define I2C_CLK_DIV_VALUE(con, bus) \\\n-\t\t\t(con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & \\\n-\t\t\t\tI2C_DIV_CON_MASK;\n+\t((con >> CLK_I2C ##bus## _DIV_CON_SHIFT) & I2C_DIV_CON_MASK)\n \n #define I2C_PMUCLK_REG_MASK(bus) \\\n-\t\t\t(I2C_DIV_CON_MASK << \\\n-\t\t\t CLK_I2C ##bus## _DIV_CON_SHIFT)\n+\t(I2C_DIV_CON_MASK << CLK_I2C ##bus## _DIV_CON_SHIFT)\n \n #define I2C_PMUCLK_REG_VALUE(bus, clk_div) \\\n-\t\t\t\t((clk_div - 1) << \\\n-\t\t\t\tCLK_I2C ##bus## _DIV_CON_SHIFT)\n+\t((clk_div - 1) << CLK_I2C ##bus## _DIV_CON_SHIFT)\n \n static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id)\n {\n@@ -597,9 +590,9 @@ static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)\n */\n \n struct spi_clkreg {\n-\tuint8_t reg; /* CLKSEL_CON[reg] register in CRU */\n-\tuint8_t div_shift;\n-\tuint8_t sel_shift;\n+\tu8 reg; /* CLKSEL_CON[reg] register in CRU */\n+\tu8 div_shift;\n+\tu8 sel_shift;\n };\n \n /*\n@@ -678,7 +671,7 @@ static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)\n static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)\n {\n \tstruct pll_div vpll_config = {0};\n-\tint aclk_vop = 198*MHz;\n+\tint aclk_vop = 198 * MHz;\n \tvoid *aclkreg_addr, *dclkreg_addr;\n \tu32 div;\n \n@@ -710,7 +703,7 @@ static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)\n \trkclk_set_pll(&cru->vpll_con[0], &vpll_config);\n \n \trk_clrsetreg(dclkreg_addr,\n-\t\t DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK|\n+\t\t DCLK_VOP_DCLK_SEL_MASK | DCLK_VOP_PLL_SEL_MASK |\n \t\t DCLK_VOP_DIV_CON_MASK,\n \t\t DCLK_VOP_DCLK_SEL_DIVOUT << DCLK_VOP_DCLK_SEL_SHIFT |\n \t\t DCLK_VOP_PLL_SEL_VPLL << DCLK_VOP_PLL_SEL_SHIFT |\n@@ -750,7 +743,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,\n \t\t\t\tulong clk_id, ulong set_rate)\n {\n \tint src_clk_div;\n-\tint aclk_emmc = 198*MHz;\n+\tint aclk_emmc = 198 * MHz;\n \n \tswitch (clk_id) {\n \tcase HCLK_SDMMC:\n@@ -776,7 +769,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,\n \t\tbreak;\n \tcase SCLK_EMMC:\n \t\t/* Select aclk_emmc source from GPLL */\n-\t\tsrc_clk_div = DIV_ROUND_UP(GPLL_HZ , aclk_emmc);\n+\t\tsrc_clk_div = DIV_ROUND_UP(GPLL_HZ, aclk_emmc);\n \t\tassert(src_clk_div - 1 < 32);\n \n \t\trk_clrsetreg(&cru->clksel_con[21],\n@@ -834,23 +827,23 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,\n \n \t/* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */\n \tswitch (set_rate) {\n-\tcase 200*MHz:\n+\tcase 200 * MHz:\n \t\tdpll_cfg = (struct pll_div)\n \t\t{.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};\n \t\tbreak;\n-\tcase 300*MHz:\n+\tcase 300 * MHz:\n \t\tdpll_cfg = (struct pll_div)\n \t\t{.refdiv = 2, .fbdiv = 100, .postdiv1 = 4, .postdiv2 = 1};\n \t\tbreak;\n-\tcase 666*MHz:\n+\tcase 666 * MHz:\n \t\tdpll_cfg = (struct pll_div)\n \t\t{.refdiv = 2, .fbdiv = 111, .postdiv1 = 2, .postdiv2 = 1};\n \t\tbreak;\n-\tcase 800*MHz:\n+\tcase 800 * MHz:\n \t\tdpll_cfg = (struct pll_div)\n \t\t{.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};\n \t\tbreak;\n-\tcase 933*MHz:\n+\tcase 933 * MHz:\n \t\tdpll_cfg = (struct pll_div)\n \t\t{.refdiv = 1, .fbdiv = 116, .postdiv1 = 3, .postdiv2 = 1};\n \t\tbreak;\n@@ -916,7 +909,6 @@ static ulong rk3399_clk_get_rate(struct clk *clk)\n \tcase SCLK_UART2:\n \tcase SCLK_UART3:\n \t\treturn 24000000;\n-\t\tbreak;\n \tcase PCLK_HDMI_CTRL:\n \t\tbreak;\n \tcase DCLK_VOP0:\n@@ -1014,7 +1006,8 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)\n \treturn ret;\n }\n \n-static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *parent)\n+static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk,\n+\t\t\t\t\t\t struct clk *parent)\n {\n \tstruct rk3399_clk_priv *priv = dev_get_priv(clk->dev);\n \tconst char *clock_output_name;\n@@ -1024,7 +1017,7 @@ static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *pa\n \t * If the requested parent is in the same clock-controller and\n \t * the id is SCLK_MAC (\"clk_gmac\"), switch to the internal clock.\n \t */\n-\tif ((parent->dev == clk->dev) && (parent->id == SCLK_MAC)) {\n+\tif (parent->dev == clk->dev && parent->id == SCLK_MAC) {\n \t\tdebug(\"%s: switching RGMII to SCLK_MAC\\n\", __func__);\n \t\trk_clrreg(&priv->cru->clksel_con[19], BIT(4));\n \t\treturn 0;\n@@ -1049,7 +1042,8 @@ static int __maybe_unused rk3399_gmac_set_parent(struct clk *clk, struct clk *pa\n \treturn -EINVAL;\n }\n \n-static int __maybe_unused rk3399_clk_set_parent(struct clk *clk, struct clk *parent)\n+static int __maybe_unused rk3399_clk_set_parent(struct clk *clk,\n+\t\t\t\t\t\tstruct clk *parent)\n {\n \tswitch (clk->id) {\n \tcase SCLK_RMII_SRC:\n", "prefixes": [ "U-Boot", "v3", "15/15" ] }