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GET /api/patches/1132165/?format=api
{ "id": 1132165, "url": "http://patchwork.ozlabs.org/api/patches/1132165/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190715182110.21336-3-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190715182110.21336-3-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2019-07-15T18:20:57", "name": "[U-Boot,v3,02/15] ram: rk3399: Some trivial code fixes", "commit_ref": "3eaf5398490f980f9b363cd3bafc7bc82e1d3235", "pull_url": null, "state": "accepted", "archived": false, "hash": "03be7a69fbf1727571e4f771a51fdaf3f902c510", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 93623, "url": "http://patchwork.ozlabs.org/api/users/93623/?format=api", "username": "kevery", "first_name": "Kever", "last_name": "Yang", "email": "ykai007@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190715182110.21336-3-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 119571, "url": "http://patchwork.ozlabs.org/api/series/119571/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=119571", "date": "2019-07-15T18:20:55", "name": "ram: rk3399: Code cleanup", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/119571/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1132165/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1132165/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"DFiE9O5X\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 45nX421NhXz9sN4\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 16 Jul 2019 04:24:18 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid B8DADC21E60; Mon, 15 Jul 2019 18:22:26 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 98BD2C21F52;\n\tMon, 15 Jul 2019 18:21:55 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid F27BFC21F98; Mon, 15 Jul 2019 18:21:33 +0000 (UTC)", "from mail-pf1-f194.google.com (mail-pf1-f194.google.com\n\t[209.85.210.194])\n\tby lists.denx.de (Postfix) with ESMTPS id 660C8C21F20\n\tfor <u-boot@lists.denx.de>; Mon, 15 Jul 2019 18:21:29 +0000 (UTC)", "by mail-pf1-f194.google.com with SMTP id u14so7815491pfn.2\n\tfor <u-boot@lists.denx.de>; Mon, 15 Jul 2019 11:21:29 -0700 (PDT)", "from localhost.localdomain ([49.206.201.107])\n\tby smtp.gmail.com with ESMTPSA id\n\tl15sm18152405pgf.5.2019.07.15.11.21.24\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tMon, 15 Jul 2019 11:21:27 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amarulasolutions.com; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=91XSnQx5BFEbjjDU1Kng5TwLgRBduu4DBFPUieipXW0=;\n\tb=DFiE9O5X2Fluynw7+arM5C4RDENZ7xOoonN1xYOhoZq10c6kyPGUrm7O6QmcY+GGLn\n\tLJq5bQUejm+DWCbS6jymkUs54VEyik2AvkJb97k4sfVJFiopubm5Xc9Ukekh7dAcNH61\n\tUIqpmm9xVBnICmxNEzta/oPHT9l423y4x+U1A=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=91XSnQx5BFEbjjDU1Kng5TwLgRBduu4DBFPUieipXW0=;\n\tb=qexvSgC3m7dSEOS9HQziPSYMnPcZkzSuETzrAdDBeOq5gKuqK67DYmmrXkgcv6fc/l\n\trqi2uZVwkiTL2I7RCNWADWvPDcq62wZJXG6FC9V1W7B5HdRApNQs36EoJGg4DKJNUbc+\n\tAuUBxaB5FeNDlr9ttqUPjYncMT1cklbTvCixSRB2TtAT5h5Psb9duDlE8MpLGEbXkxsf\n\t7sBOPIm/kw1Lx4zVH2ABhv83p60UouX96JVJNnD/8v7QdDObSfOykWWws9wagbjgo6Ub\n\tO19twjkQI3ZAn0NPYP6AYb+Zrhg4NQO67id5NMpFDKoiH/4+ogdKFELCHh3Zci4Sv9/4\n\tfSPw==", "X-Gm-Message-State": "APjAAAXc2i3mEtmNQ8eEn0Dzg9Y3ZGQI+SREyywM/YnDDsmgHr3OMwMB\n\t8+FY+0aibkS7GT9KmvWmXrFa2A==", "X-Google-Smtp-Source": "APXvYqw6M+0WZaSGgchasMscDnwlTt1GZHlALCRnaIY4IkIDUsdI1Uo4o0vtj/O1XG4Ax/TneqzhyA==", "X-Received": "by 2002:a63:d4c:: with SMTP id 12mr28947708pgn.30.1563214887849; \n\tMon, 15 Jul 2019 11:21:27 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Simon Glass <sjg@chromium.org>,\n\tPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>,\n\tKever Yang <kever.yang@rock-chips.com>,\n\tYouMin Chen <cym@rock-chips.com>, u-boot@lists.denx.de", "Date": "Mon, 15 Jul 2019 23:50:57 +0530", "Message-Id": "<20190715182110.21336-3-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20190715182110.21336-1-jagan@amarulasolutions.com>", "References": "<20190715182110.21336-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com,\n\tlinux-amarula@amarulasolutions.com,\n\tManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>", "Subject": "[U-Boot] [PATCH v3 02/15] ram: rk3399: Some trivial code fixes", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "- Add proper spaces in data training, rk3399_dmc_init, pctl_cfg\n- Order include files\n- Move macro after include files\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\n---\n drivers/ram/rockchip/sdram_rk3399.c | 60 +++++++++++++++++++++--------\n 1 file changed, 43 insertions(+), 17 deletions(-)", "diff": "diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c\nindex 541e4a4b1e..733864f5d2 100644\n--- a/drivers/ram/rockchip/sdram_rk3399.c\n+++ b/drivers/ram/rockchip/sdram_rk3399.c\n@@ -14,14 +14,27 @@\n #include <syscon.h>\n #include <asm/io.h>\n #include <asm/arch-rockchip/clock.h>\n-#include <asm/arch-rockchip/sdram_common.h>\n-#include <asm/arch-rockchip/sdram_rk3399.h>\n #include <asm/arch-rockchip/cru_rk3399.h>\n #include <asm/arch-rockchip/grf_rk3399.h>\n #include <asm/arch-rockchip/hardware.h>\n+#include <asm/arch-rockchip/sdram_common.h>\n+#include <asm/arch-rockchip/sdram_rk3399.h>\n #include <linux/err.h>\n #include <time.h>\n \n+#define PRESET_SGRF_HOLD(n)\t((0x1 << (6 + 16)) | ((n) << 6))\n+#define PRESET_GPIO0_HOLD(n)\t((0x1 << (7 + 16)) | ((n) << 7))\n+#define PRESET_GPIO1_HOLD(n)\t((0x1 << (8 + 16)) | ((n) << 8))\n+\n+#define PHY_DRV_ODT_HI_Z\t0x0\n+#define PHY_DRV_ODT_240\t\t0x1\n+#define PHY_DRV_ODT_120\t\t0x8\n+#define PHY_DRV_ODT_80\t\t0x9\n+#define PHY_DRV_ODT_60\t\t0xc\n+#define PHY_DRV_ODT_48\t\t0xd\n+#define PHY_DRV_ODT_40\t\t0xe\n+#define PHY_DRV_ODT_34_3\t0xf\n+\n struct chan_info {\n \tstruct rk3399_ddr_pctl_regs *pctl;\n \tstruct rk3399_ddr_pi_regs *pi;\n@@ -43,19 +56,6 @@ struct dram_info {\n \tstruct rk3399_pmugrf_regs *pmugrf;\n };\n \n-#define PRESET_SGRF_HOLD(n)\t((0x1 << (6 + 16)) | ((n) << 6))\n-#define PRESET_GPIO0_HOLD(n)\t((0x1 << (7 + 16)) | ((n) << 7))\n-#define PRESET_GPIO1_HOLD(n)\t((0x1 << (8 + 16)) | ((n) << 8))\n-\n-#define PHY_DRV_ODT_HI_Z\t0x0\n-#define PHY_DRV_ODT_240\t\t0x1\n-#define PHY_DRV_ODT_120\t\t0x8\n-#define PHY_DRV_ODT_80\t\t0x9\n-#define PHY_DRV_ODT_60\t\t0xc\n-#define PHY_DRV_ODT_48\t\t0xd\n-#define PHY_DRV_ODT_40\t\t0xe\n-#define PHY_DRV_ODT_34_3\t0xf\n-\n #if defined(CONFIG_TPL_BUILD) || \\\n \t(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))\n \n@@ -473,8 +473,10 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,\n \tcopy_to_reg(&denali_ctl[1], ¶ms_ctl[1],\n \t\t sizeof(struct rk3399_ddr_pctl_regs) - 4);\n \twritel(params_ctl[0], &denali_ctl[0]);\n+\n \tcopy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0],\n \t\t sizeof(struct rk3399_ddr_pi_regs));\n+\n \t/* rank count need to set for init */\n \tset_memory_map(chan, channel, sdram_params);\n \n@@ -620,8 +622,10 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,\n \n \tfor (i = 0; i < rank; i++) {\n \t\tselect_per_cs_training_index(chan, i);\n+\n \t\t/* PI_100 PI_CALVL_EN:RW:8:2 */\n \t\tclrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8);\n+\n \t\t/* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */\n \t\tclrsetbits_le32(&denali_pi[92],\n \t\t\t\t(0x1 << 16) | (0x3 << 24),\n@@ -651,9 +655,11 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,\n \t\t\t\t (obs_err == 1))\n \t\t\t\treturn -EIO;\n \t\t}\n+\n \t\t/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */\n \t\twritel(0x00003f7c, (&denali_pi[175]));\n \t}\n+\n \tclrbits_le32(&denali_pi[100], 0x3 << 8);\n \n \treturn 0;\n@@ -670,8 +676,10 @@ static int data_training_wl(const struct chan_info *chan, u32 channel,\n \n \tfor (i = 0; i < rank; i++) {\n \t\tselect_per_cs_training_index(chan, i);\n+\n \t\t/* PI_60 PI_WRLVL_EN:RW:8:2 */\n \t\tclrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8);\n+\n \t\t/* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */\n \t\tclrsetbits_le32(&denali_pi[59],\n \t\t\t\t(0x1 << 8) | (0x3 << 16),\n@@ -705,6 +713,7 @@ static int data_training_wl(const struct chan_info *chan, u32 channel,\n \t\t\t\t (obs_err == 1))\n \t\t\t\treturn -EIO;\n \t\t}\n+\n \t\t/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */\n \t\twritel(0x00003f7c, (&denali_pi[175]));\n \t}\n@@ -726,8 +735,10 @@ static int data_training_rg(const struct chan_info *chan, u32 channel,\n \n \tfor (i = 0; i < rank; i++) {\n \t\tselect_per_cs_training_index(chan, i);\n+\n \t\t/* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */\n \t\tclrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24);\n+\n \t\t/*\n \t\t * PI_74 PI_RDLVL_GATE_REQ:WR:16:1\n \t\t * PI_RDLVL_CS:RW:24:2\n@@ -764,9 +775,11 @@ static int data_training_rg(const struct chan_info *chan, u32 channel,\n \t\t\t\t (obs_err == 1))\n \t\t\t\treturn -EIO;\n \t\t}\n+\n \t\t/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */\n \t\twritel(0x00003f7c, (&denali_pi[175]));\n \t}\n+\n \tclrbits_le32(&denali_pi[80], 0x3 << 24);\n \n \treturn 0;\n@@ -781,8 +794,10 @@ static int data_training_rl(const struct chan_info *chan, u32 channel,\n \n \tfor (i = 0; i < rank; i++) {\n \t\tselect_per_cs_training_index(chan, i);\n+\n \t\t/* PI_80 PI_RDLVL_EN:RW:16:2 */\n \t\tclrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16);\n+\n \t\t/* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */\n \t\tclrsetbits_le32(&denali_pi[74],\n \t\t\t\t(0x1 << 8) | (0x3 << 24),\n@@ -805,9 +820,11 @@ static int data_training_rl(const struct chan_info *chan, u32 channel,\n \t\t\telse if (((tmp >> 2) & 0x1) == 0x1)\n \t\t\t\treturn -EIO;\n \t\t}\n+\n \t\t/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */\n \t\twritel(0x00003f7c, (&denali_pi[175]));\n \t}\n+\n \tclrbits_le32(&denali_pi[80], 0x3 << 16);\n \n \treturn 0;\n@@ -822,13 +839,16 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,\n \n \tfor (i = 0; i < rank; i++) {\n \t\tselect_per_cs_training_index(chan, i);\n+\n \t\t/*\n \t\t * disable PI_WDQLVL_VREF_EN before wdq leveling?\n \t\t * PI_181 PI_WDQLVL_VREF_EN:RW:8:1\n \t\t */\n \t\tclrbits_le32(&denali_pi[181], 0x1 << 8);\n+\n \t\t/* PI_124 PI_WDQLVL_EN:RW:16:2 */\n \t\tclrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16);\n+\n \t\t/* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */\n \t\tclrsetbits_le32(&denali_pi[121],\n \t\t\t\t(0x1 << 8) | (0x3 << 16),\n@@ -845,9 +865,11 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,\n \t\t\telse if (((tmp >> 6) & 0x1) == 0x1)\n \t\t\t\treturn -EIO;\n \t\t}\n+\n \t\t/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */\n \t\twritel(0x00003f7c, (&denali_pi[175]));\n \t}\n+\n \tclrbits_le32(&denali_pi[124], 0x3 << 16);\n \n \treturn 0;\n@@ -938,6 +960,7 @@ static void dram_all_config(struct dram_info *dram,\n \tsys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;\n \tsys_reg |= (sdram_params->base.num_channels - 1)\n \t\t << SYS_REG_NUM_CH_SHIFT;\n+\n \tfor (channel = 0, idx = 0;\n \t (idx < sdram_params->base.num_channels) && (channel < 2);\n \t channel++) {\n@@ -1164,6 +1187,7 @@ static int rk3399_dmc_init(struct udevice *dev)\n \t priv->chan[1].publ, priv->chan[1].msch);\n \tdebug(\"cru %p, cic %p, grf %p, sgrf %p, pmucru %p\\n\", priv->cru,\n \t priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru);\n+\n #if CONFIG_IS_ENABLED(OF_PLATDATA)\n \tret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk);\n #else\n@@ -1173,14 +1197,16 @@ static int rk3399_dmc_init(struct udevice *dev)\n \t\tprintf(\"%s clk get failed %d\\n\", __func__, ret);\n \t\treturn ret;\n \t}\n+\n \tret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz);\n \tif (ret < 0) {\n \t\tprintf(\"%s clk set failed %d\\n\", __func__, ret);\n \t\treturn ret;\n \t}\n+\n \tret = sdram_init(priv, params);\n \tif (ret < 0) {\n-\t\tprintf(\"%s DRAM init failed%d\\n\", __func__, ret);\n+\t\tprintf(\"%s DRAM init failed %d\\n\", __func__, ret);\n \t\treturn ret;\n \t}\n \n@@ -1198,7 +1224,7 @@ static int rk3399_dmc_probe(struct udevice *dev)\n \tstruct dram_info *priv = dev_get_priv(dev);\n \n \tpriv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);\n-\tdebug(\"%s: pmugrf=%p\\n\", __func__, priv->pmugrf);\n+\tdebug(\"%s: pmugrf = %p\\n\", __func__, priv->pmugrf);\n \tpriv->info.base = CONFIG_SYS_SDRAM_BASE;\n \tpriv->info.size =\n \t\trockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);\n", "prefixes": [ "U-Boot", "v3", "02/15" ] }