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GET /api/patches/1132162/?format=api
{ "id": 1132162, "url": "http://patchwork.ozlabs.org/api/patches/1132162/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190715182110.21336-4-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190715182110.21336-4-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2019-07-15T18:20:58", "name": "[U-Boot,v3,03/15] ram: rk3399: s/sdram_params/params", "commit_ref": "fde7f457e137e42f88a712089199bac72bc111ec", "pull_url": null, "state": "accepted", "archived": false, "hash": "b15eab6e105fdb0c3ed203242c4f3f517acf9e5d", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 93623, "url": "http://patchwork.ozlabs.org/api/users/93623/?format=api", "username": "kevery", "first_name": "Kever", "last_name": "Yang", "email": "ykai007@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190715182110.21336-4-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 119571, "url": "http://patchwork.ozlabs.org/api/series/119571/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=119571", "date": "2019-07-15T18:20:55", "name": "ram: rk3399: Code cleanup", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/119571/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1132162/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1132162/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"TIPHR5LT\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 45nX212rWwz9s3l\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 16 Jul 2019 04:22:33 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 0C4DAC21FA6; Mon, 15 Jul 2019 18:21:58 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id DB5D2C21F93;\n\tMon, 15 Jul 2019 18:21:53 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 88B1EC21EDC; Mon, 15 Jul 2019 18:21:37 +0000 (UTC)", "from mail-pf1-f195.google.com (mail-pf1-f195.google.com\n\t[209.85.210.195])\n\tby lists.denx.de (Postfix) with ESMTPS id 18500C21F9F\n\tfor <u-boot@lists.denx.de>; Mon, 15 Jul 2019 18:21:33 +0000 (UTC)", "by mail-pf1-f195.google.com with SMTP id 19so7805796pfa.4\n\tfor <u-boot@lists.denx.de>; Mon, 15 Jul 2019 11:21:33 -0700 (PDT)", "from localhost.localdomain ([49.206.201.107])\n\tby smtp.gmail.com with ESMTPSA id\n\tl15sm18152405pgf.5.2019.07.15.11.21.28\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tMon, 15 Jul 2019 11:21:30 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; 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s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=KmKFsDAGwxoAiqCijRqUKLZ7ZLjpJJLsduhpkwVMnGU=;\n\tb=tIQuwq3ZX6/IcS7VygoTQl0ND80FROMoz93XVNT3UuTAKoKp63YwWEZa/DOFKZeTxx\n\tuMpSLuVuv9i07NCHBfEJZdDEYxGXcG/bMexAPnKbBagC/msmggVHg8+mMd5X/bX9mmkz\n\t6c6lselxd9im5yJtRC7a6OVGC0Z8/NfPsvXViIWMALf9p6uEjJRikRIR9Ab4ZUz9h4et\n\tFVSaJ6SG1+mrdagVn8+dCEHMA0ImfDzSR2I6PtF0i+lCZZQHbdYWlgXcYZxe/EFvKgTs\n\tHO0/jjPd1lKkuqc0Fl+z+twk45svnuNcHjcUIGoY9fWmAjcM0dWITnaf/4NUmxts/Ika\n\tYsmA==", "X-Gm-Message-State": "APjAAAUza/gXzCyJP49vkAGs94r4K+FgsNEA9/U8iDUfXXaVvUa8xF5O\n\tWRwMRjwZt5+JUwzH8hjN9DQLZQ==", "X-Google-Smtp-Source": "APXvYqwQnmZHGFZYli1iIlTEOc44v4xttzrbZoLBu9to4ODU+Fs2mmfFP6SwabOoCBk9Nf73G3EslQ==", "X-Received": "by 2002:a63:da52:: with SMTP id\n\tl18mr28566377pgj.131.1563214891417; \n\tMon, 15 Jul 2019 11:21:31 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Simon Glass <sjg@chromium.org>,\n\tPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>,\n\tKever Yang <kever.yang@rock-chips.com>,\n\tYouMin Chen <cym@rock-chips.com>, u-boot@lists.denx.de", "Date": "Mon, 15 Jul 2019 23:50:58 +0530", "Message-Id": "<20190715182110.21336-4-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20190715182110.21336-1-jagan@amarulasolutions.com>", "References": "<20190715182110.21336-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com,\n\tlinux-amarula@amarulasolutions.com,\n\tManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>", "Subject": "[U-Boot] [PATCH v3 03/15] ram: rk3399: s/sdram_params/params", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Rename variable name of struct rk3399_sdram_params\nfrom sdram_params with params for more code readability.\n\nNo functionality change.\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\n---\n drivers/ram/rockchip/sdram_rk3399.c | 160 ++++++++++++++--------------\n 1 file changed, 78 insertions(+), 82 deletions(-)", "diff": "diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c\nindex 733864f5d2..c918c2e588 100644\n--- a/drivers/ram/rockchip/sdram_rk3399.c\n+++ b/drivers/ram/rockchip/sdram_rk3399.c\n@@ -111,10 +111,9 @@ static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs,\n }\n \n static void set_memory_map(const struct chan_info *chan, u32 channel,\n-\t\t\t const struct rk3399_sdram_params *sdram_params)\n+\t\t\t const struct rk3399_sdram_params *params)\n {\n-\tconst struct rk3399_sdram_channel *sdram_ch =\n-\t\t&sdram_params->ch[channel];\n+\tconst struct rk3399_sdram_channel *sdram_ch = ¶ms->ch[channel];\n \tu32 *denali_ctl = chan->pctl->denali_ctl;\n \tu32 *denali_pi = chan->pi->denali_pi;\n \tu32 cs_map;\n@@ -150,12 +149,12 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,\n \t\t\t((16 - row) << 24));\n \t/* PI_41 PI_CS_MAP:RW:24:4 */\n \tclrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);\n-\tif (sdram_ch->rank == 1 && sdram_params->base.dramtype == DDR3)\n+\tif (sdram_ch->rank == 1 && params->base.dramtype == DDR3)\n \t\twritel(0x2EC7FFFF, &denali_pi[34]);\n }\n \n static void set_ds_odt(const struct chan_info *chan,\n-\t\t const struct rk3399_sdram_params *sdram_params)\n+\t\t const struct rk3399_sdram_params *params)\n {\n \tu32 *denali_phy = chan->publ->denali_phy;\n \n@@ -165,7 +164,7 @@ static void set_ds_odt(const struct chan_info *chan,\n \tu32 tsel_idle_select_n, tsel_wr_select_n, tsel_rd_select_n;\n \tu32 reg_value;\n \n-\tif (sdram_params->base.dramtype == LPDDR4) {\n+\tif (params->base.dramtype == LPDDR4) {\n \t\ttsel_rd_select_p = PHY_DRV_ODT_HI_Z;\n \t\ttsel_wr_select_p = PHY_DRV_ODT_40;\n \t\tca_tsel_wr_select_p = PHY_DRV_ODT_40;\n@@ -175,7 +174,7 @@ static void set_ds_odt(const struct chan_info *chan,\n \t\ttsel_wr_select_n = PHY_DRV_ODT_40;\n \t\tca_tsel_wr_select_n = PHY_DRV_ODT_40;\n \t\ttsel_idle_select_n = PHY_DRV_ODT_240;\n-\t} else if (sdram_params->base.dramtype == LPDDR3) {\n+\t} else if (params->base.dramtype == LPDDR3) {\n \t\ttsel_rd_select_p = PHY_DRV_ODT_240;\n \t\ttsel_wr_select_p = PHY_DRV_ODT_34_3;\n \t\tca_tsel_wr_select_p = PHY_DRV_ODT_48;\n@@ -197,7 +196,7 @@ static void set_ds_odt(const struct chan_info *chan,\n \t\ttsel_idle_select_n = PHY_DRV_ODT_240;\n \t}\n \n-\tif (sdram_params->base.odt == 1)\n+\tif (params->base.odt == 1)\n \t\ttsel_rd_en = 1;\n \telse\n \t\ttsel_rd_en = 0;\n@@ -294,7 +293,7 @@ static void set_ds_odt(const struct chan_info *chan,\n }\n \n static int phy_io_config(const struct chan_info *chan,\n-\t\t\t const struct rk3399_sdram_params *sdram_params)\n+\t\t\t const struct rk3399_sdram_params *params)\n {\n \tu32 *denali_phy = chan->publ->denali_phy;\n \tu32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;\n@@ -304,14 +303,14 @@ static int phy_io_config(const struct chan_info *chan,\n \tu32 speed;\n \n \t/* vref setting */\n-\tif (sdram_params->base.dramtype == LPDDR4) {\n+\tif (params->base.dramtype == LPDDR4) {\n \t\t/* LPDDR4 */\n \t\tvref_mode_dq = 0x6;\n \t\tvref_value_dq = 0x1f;\n \t\tvref_mode_ac = 0x6;\n \t\tvref_value_ac = 0x1f;\n-\t} else if (sdram_params->base.dramtype == LPDDR3) {\n-\t\tif (sdram_params->base.odt == 1) {\n+\t} else if (params->base.dramtype == LPDDR3) {\n+\t\tif (params->base.odt == 1) {\n \t\t\tvref_mode_dq = 0x5; /* LPDDR3 ODT */\n \t\t\tdrv_value = (readl(&denali_phy[6]) >> 12) & 0xf;\n \t\t\todt_value = (readl(&denali_phy[6]) >> 4) & 0xf;\n@@ -370,7 +369,7 @@ static int phy_io_config(const struct chan_info *chan,\n \t\t}\n \t\tvref_mode_ac = 0x2;\n \t\tvref_value_ac = 0x1f;\n-\t} else if (sdram_params->base.dramtype == DDR3) {\n+\t} else if (params->base.dramtype == DDR3) {\n \t\t/* DDR3L */\n \t\tvref_mode_dq = 0x1;\n \t\tvref_value_dq = 0x1f;\n@@ -397,11 +396,11 @@ static int phy_io_config(const struct chan_info *chan,\n \t/* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */\n \tclrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);\n \n-\tif (sdram_params->base.dramtype == LPDDR4)\n+\tif (params->base.dramtype == LPDDR4)\n \t\tmode_sel = 0x6;\n-\telse if (sdram_params->base.dramtype == LPDDR3)\n+\telse if (params->base.dramtype == LPDDR3)\n \t\tmode_sel = 0x0;\n-\telse if (sdram_params->base.dramtype == DDR3)\n+\telse if (params->base.dramtype == DDR3)\n \t\tmode_sel = 0x1;\n \telse\n \t\treturn -EINVAL;\n@@ -424,11 +423,11 @@ static int phy_io_config(const struct chan_info *chan,\n \tclrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);\n \n \t/* speed setting */\n-\tif (sdram_params->base.ddr_freq < 400)\n+\tif (params->base.ddr_freq < 400)\n \t\tspeed = 0x0;\n-\telse if (sdram_params->base.ddr_freq < 800)\n+\telse if (params->base.ddr_freq < 800)\n \t\tspeed = 0x1;\n-\telse if (sdram_params->base.ddr_freq < 1200)\n+\telse if (params->base.ddr_freq < 1200)\n \t\tspeed = 0x2;\n \telse\n \t\tspeed = 0x3;\n@@ -454,13 +453,13 @@ static int phy_io_config(const struct chan_info *chan,\n }\n \n static int pctl_cfg(const struct chan_info *chan, u32 channel,\n-\t\t const struct rk3399_sdram_params *sdram_params)\n+\t\t const struct rk3399_sdram_params *params)\n {\n \tu32 *denali_ctl = chan->pctl->denali_ctl;\n \tu32 *denali_pi = chan->pi->denali_pi;\n \tu32 *denali_phy = chan->publ->denali_phy;\n-\tconst u32 *params_ctl = sdram_params->pctl_regs.denali_ctl;\n-\tconst u32 *params_phy = sdram_params->phy_regs.denali_phy;\n+\tconst u32 *params_ctl = params->pctl_regs.denali_ctl;\n+\tconst u32 *params_phy = params->phy_regs.denali_phy;\n \tu32 tmp, tmp1, tmp2;\n \tu32 pwrup_srefresh_exit;\n \tint ret;\n@@ -474,15 +473,15 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,\n \t\t sizeof(struct rk3399_ddr_pctl_regs) - 4);\n \twritel(params_ctl[0], &denali_ctl[0]);\n \n-\tcopy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0],\n+\tcopy_to_reg(denali_pi, ¶ms->pi_regs.denali_pi[0],\n \t\t sizeof(struct rk3399_ddr_pi_regs));\n \n \t/* rank count need to set for init */\n-\tset_memory_map(chan, channel, sdram_params);\n+\tset_memory_map(chan, channel, params);\n \n-\twritel(sdram_params->phy_regs.denali_phy[910], &denali_phy[910]);\n-\twritel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]);\n-\twritel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]);\n+\twritel(params->phy_regs.denali_phy[910], &denali_phy[910]);\n+\twritel(params->phy_regs.denali_phy[911], &denali_phy[911]);\n+\twritel(params->phy_regs.denali_phy[912], &denali_phy[912]);\n \n \tpwrup_srefresh_exit = readl(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT;\n \tclrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);\n@@ -513,7 +512,7 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,\n \tcopy_to_reg(&denali_phy[512], ¶ms_phy[512], (549 - 512 + 1) * 4);\n \tcopy_to_reg(&denali_phy[640], ¶ms_phy[640], (677 - 640 + 1) * 4);\n \tcopy_to_reg(&denali_phy[768], ¶ms_phy[768], (805 - 768 + 1) * 4);\n-\tset_ds_odt(chan, sdram_params);\n+\tset_ds_odt(chan, params);\n \n \t/*\n \t * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8\n@@ -541,7 +540,7 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,\n \ttmp = (readl(&denali_phy[467]) >> 16) & 0xff;\n \tclrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16);\n \n-\tret = phy_io_config(chan, sdram_params);\n+\tret = phy_io_config(chan, params);\n \tif (ret)\n \t\treturn ret;\n \n@@ -612,13 +611,13 @@ static void override_write_leveling_value(const struct chan_info *chan)\n }\n \n static int data_training_ca(const struct chan_info *chan, u32 channel,\n-\t\t\t const struct rk3399_sdram_params *sdram_params)\n+\t\t\t const struct rk3399_sdram_params *params)\n {\n \tu32 *denali_pi = chan->pi->denali_pi;\n \tu32 *denali_phy = chan->publ->denali_phy;\n \tu32 i, tmp;\n \tu32 obs_0, obs_1, obs_2, obs_err = 0;\n-\tu32 rank = sdram_params->ch[channel].rank;\n+\tu32 rank = params->ch[channel].rank;\n \n \tfor (i = 0; i < rank; i++) {\n \t\tselect_per_cs_training_index(chan, i);\n@@ -666,13 +665,13 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,\n }\n \n static int data_training_wl(const struct chan_info *chan, u32 channel,\n-\t\t\t const struct rk3399_sdram_params *sdram_params)\n+\t\t\t const struct rk3399_sdram_params *params)\n {\n \tu32 *denali_pi = chan->pi->denali_pi;\n \tu32 *denali_phy = chan->publ->denali_phy;\n \tu32 i, tmp;\n \tu32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;\n-\tu32 rank = sdram_params->ch[channel].rank;\n+\tu32 rank = params->ch[channel].rank;\n \n \tfor (i = 0; i < rank; i++) {\n \t\tselect_per_cs_training_index(chan, i);\n@@ -725,13 +724,13 @@ static int data_training_wl(const struct chan_info *chan, u32 channel,\n }\n \n static int data_training_rg(const struct chan_info *chan, u32 channel,\n-\t\t\t const struct rk3399_sdram_params *sdram_params)\n+\t\t\t const struct rk3399_sdram_params *params)\n {\n \tu32 *denali_pi = chan->pi->denali_pi;\n \tu32 *denali_phy = chan->publ->denali_phy;\n \tu32 i, tmp;\n \tu32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;\n-\tu32 rank = sdram_params->ch[channel].rank;\n+\tu32 rank = params->ch[channel].rank;\n \n \tfor (i = 0; i < rank; i++) {\n \t\tselect_per_cs_training_index(chan, i);\n@@ -786,11 +785,11 @@ static int data_training_rg(const struct chan_info *chan, u32 channel,\n }\n \n static int data_training_rl(const struct chan_info *chan, u32 channel,\n-\t\t\t const struct rk3399_sdram_params *sdram_params)\n+\t\t\t const struct rk3399_sdram_params *params)\n {\n \tu32 *denali_pi = chan->pi->denali_pi;\n \tu32 i, tmp;\n-\tu32 rank = sdram_params->ch[channel].rank;\n+\tu32 rank = params->ch[channel].rank;\n \n \tfor (i = 0; i < rank; i++) {\n \t\tselect_per_cs_training_index(chan, i);\n@@ -831,11 +830,11 @@ static int data_training_rl(const struct chan_info *chan, u32 channel,\n }\n \n static int data_training_wdql(const struct chan_info *chan, u32 channel,\n-\t\t\t const struct rk3399_sdram_params *sdram_params)\n+\t\t\t const struct rk3399_sdram_params *params)\n {\n \tu32 *denali_pi = chan->pi->denali_pi;\n \tu32 i, tmp;\n-\tu32 rank = sdram_params->ch[channel].rank;\n+\tu32 rank = params->ch[channel].rank;\n \n \tfor (i = 0; i < rank; i++) {\n \t\tselect_per_cs_training_index(chan, i);\n@@ -876,7 +875,7 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,\n }\n \n static int data_training(const struct chan_info *chan, u32 channel,\n-\t\t\t const struct rk3399_sdram_params *sdram_params,\n+\t\t\t const struct rk3399_sdram_params *params,\n \t\t\t u32 training_flag)\n {\n \tu32 *denali_phy = chan->publ->denali_phy;\n@@ -885,14 +884,14 @@ static int data_training(const struct chan_info *chan, u32 channel,\n \tsetbits_le32(&denali_phy[927], (1 << 22));\n \n \tif (training_flag == PI_FULL_TRAINING) {\n-\t\tif (sdram_params->base.dramtype == LPDDR4) {\n+\t\tif (params->base.dramtype == LPDDR4) {\n \t\t\ttraining_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |\n \t\t\t\t\tPI_READ_GATE_TRAINING |\n \t\t\t\t\tPI_READ_LEVELING | PI_WDQ_LEVELING;\n-\t\t} else if (sdram_params->base.dramtype == LPDDR3) {\n+\t\t} else if (params->base.dramtype == LPDDR3) {\n \t\t\ttraining_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |\n \t\t\t\t\tPI_READ_GATE_TRAINING;\n-\t\t} else if (sdram_params->base.dramtype == DDR3) {\n+\t\t} else if (params->base.dramtype == DDR3) {\n \t\t\ttraining_flag = PI_WRITE_LEVELING |\n \t\t\t\t\tPI_READ_GATE_TRAINING |\n \t\t\t\t\tPI_READ_LEVELING;\n@@ -901,23 +900,23 @@ static int data_training(const struct chan_info *chan, u32 channel,\n \n \t/* ca training(LPDDR4,LPDDR3 support) */\n \tif ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING)\n-\t\tdata_training_ca(chan, channel, sdram_params);\n+\t\tdata_training_ca(chan, channel, params);\n \n \t/* write leveling(LPDDR4,LPDDR3,DDR3 support) */\n \tif ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING)\n-\t\tdata_training_wl(chan, channel, sdram_params);\n+\t\tdata_training_wl(chan, channel, params);\n \n \t/* read gate training(LPDDR4,LPDDR3,DDR3 support) */\n \tif ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING)\n-\t\tdata_training_rg(chan, channel, sdram_params);\n+\t\tdata_training_rg(chan, channel, params);\n \n \t/* read leveling(LPDDR4,LPDDR3,DDR3 support) */\n \tif ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING)\n-\t\tdata_training_rl(chan, channel, sdram_params);\n+\t\tdata_training_rl(chan, channel, params);\n \n \t/* wdq leveling(LPDDR4 support) */\n \tif ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING)\n-\t\tdata_training_wdql(chan, channel, sdram_params);\n+\t\tdata_training_wdql(chan, channel, params);\n \n \t/* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */\n \tclrbits_le32(&denali_phy[927], (1 << 22));\n@@ -926,7 +925,7 @@ static int data_training(const struct chan_info *chan, u32 channel,\n }\n \n static void set_ddrconfig(const struct chan_info *chan,\n-\t\t\t const struct rk3399_sdram_params *sdram_params,\n+\t\t\t const struct rk3399_sdram_params *params,\n \t\t\t unsigned char channel, u32 ddrconfig)\n {\n \t/* only need to set ddrconfig */\n@@ -934,14 +933,14 @@ static void set_ddrconfig(const struct chan_info *chan,\n \tunsigned int cs0_cap = 0;\n \tunsigned int cs1_cap = 0;\n \n-\tcs0_cap = (1 << (sdram_params->ch[channel].cs0_row\n-\t\t\t+ sdram_params->ch[channel].col\n-\t\t\t+ sdram_params->ch[channel].bk\n-\t\t\t+ sdram_params->ch[channel].bw - 20));\n-\tif (sdram_params->ch[channel].rank > 1)\n-\t\tcs1_cap = cs0_cap >> (sdram_params->ch[channel].cs0_row\n-\t\t\t\t- sdram_params->ch[channel].cs1_row);\n-\tif (sdram_params->ch[channel].row_3_4) {\n+\tcs0_cap = (1 << (params->ch[channel].cs0_row\n+\t\t\t+ params->ch[channel].col\n+\t\t\t+ params->ch[channel].bk\n+\t\t\t+ params->ch[channel].bw - 20));\n+\tif (params->ch[channel].rank > 1)\n+\t\tcs1_cap = cs0_cap >> (params->ch[channel].cs0_row\n+\t\t\t\t- params->ch[channel].cs1_row);\n+\tif (params->ch[channel].row_3_4) {\n \t\tcs0_cap = cs0_cap * 3 / 4;\n \t\tcs1_cap = cs1_cap * 3 / 4;\n \t}\n@@ -952,24 +951,22 @@ static void set_ddrconfig(const struct chan_info *chan,\n }\n \n static void dram_all_config(struct dram_info *dram,\n-\t\t\t const struct rk3399_sdram_params *sdram_params)\n+\t\t\t const struct rk3399_sdram_params *params)\n {\n \tu32 sys_reg = 0;\n \tunsigned int channel, idx;\n \n-\tsys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;\n-\tsys_reg |= (sdram_params->base.num_channels - 1)\n-\t\t << SYS_REG_NUM_CH_SHIFT;\n+\tsys_reg |= params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;\n+\tsys_reg |= (params->base.num_channels - 1) << SYS_REG_NUM_CH_SHIFT;\n \n \tfor (channel = 0, idx = 0;\n-\t (idx < sdram_params->base.num_channels) && (channel < 2);\n+\t (idx < params->base.num_channels) && (channel < 2);\n \t channel++) {\n-\t\tconst struct rk3399_sdram_channel *info =\n-\t\t\t&sdram_params->ch[channel];\n+\t\tconst struct rk3399_sdram_channel *info = ¶ms->ch[channel];\n \t\tstruct rk3399_msch_regs *ddr_msch_regs;\n \t\tconst struct rk3399_msch_timings *noc_timing;\n \n-\t\tif (sdram_params->ch[channel].col == 0)\n+\t\tif (params->ch[channel].col == 0)\n \t\t\tcontinue;\n \t\tidx++;\n \t\tsys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(channel);\n@@ -985,7 +982,7 @@ static void dram_all_config(struct dram_info *dram,\n \t\tsys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel);\n \n \t\tddr_msch_regs = dram->chan[channel].msch;\n-\t\tnoc_timing = &sdram_params->ch[channel].noc_timings;\n+\t\tnoc_timing = ¶ms->ch[channel].noc_timings;\n \t\twritel(noc_timing->ddrtiminga0,\n \t\t &ddr_msch_regs->ddrtiminga0);\n \t\twritel(noc_timing->ddrtimingb0,\n@@ -998,14 +995,14 @@ static void dram_all_config(struct dram_info *dram,\n \t\t &ddr_msch_regs->ddrmode);\n \n \t\t/* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */\n-\t\tif (sdram_params->ch[channel].rank == 1)\n+\t\tif (params->ch[channel].rank == 1)\n \t\t\tsetbits_le32(&dram->chan[channel].pctl->denali_ctl[276],\n \t\t\t\t 1 << 17);\n \t}\n \n \twritel(sys_reg, &dram->pmugrf->os_reg2);\n \trk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,\n-\t\t sdram_params->base.stride << 10);\n+\t\t params->base.stride << 10);\n \n \t/* reboot hold register set */\n \twritel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) |\n@@ -1015,11 +1012,11 @@ static void dram_all_config(struct dram_info *dram,\n }\n \n static int switch_to_phy_index1(struct dram_info *dram,\n-\t\t\t\tconst struct rk3399_sdram_params *sdram_params)\n+\t\t\t\tconst struct rk3399_sdram_params *params)\n {\n \tu32 channel;\n \tu32 *denali_phy;\n-\tu32 ch_count = sdram_params->base.num_channels;\n+\tu32 ch_count = params->base.num_channels;\n \tint ret;\n \tint i = 0;\n \n@@ -1050,7 +1047,7 @@ static int switch_to_phy_index1(struct dram_info *dram,\n \t\tdenali_phy = dram->chan[channel].publ->denali_phy;\n \t\tclrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);\n \t\tret = data_training(&dram->chan[channel], channel,\n-\t\t\t\t sdram_params, PI_FULL_TRAINING);\n+\t\t\t\t params, PI_FULL_TRAINING);\n \t\tif (ret) {\n \t\t\tdebug(\"index1 training failed\\n\");\n \t\t\treturn ret;\n@@ -1061,10 +1058,10 @@ static int switch_to_phy_index1(struct dram_info *dram,\n }\n \n static int sdram_init(struct dram_info *dram,\n-\t\t const struct rk3399_sdram_params *sdram_params)\n+\t\t const struct rk3399_sdram_params *params)\n {\n-\tunsigned char dramtype = sdram_params->base.dramtype;\n-\tunsigned int ddr_freq = sdram_params->base.ddr_freq;\n+\tunsigned char dramtype = params->base.dramtype;\n+\tunsigned int ddr_freq = params->base.ddr_freq;\n \tint channel;\n \n \tdebug(\"Starting SDRAM initialization...\\n\");\n@@ -1082,10 +1079,10 @@ static int sdram_init(struct dram_info *dram,\n \n \t\tphy_dll_bypass_set(publ, ddr_freq);\n \n-\t\tif (channel >= sdram_params->base.num_channels)\n+\t\tif (channel >= params->base.num_channels)\n \t\t\tcontinue;\n \n-\t\tif (pctl_cfg(chan, channel, sdram_params) != 0) {\n+\t\tif (pctl_cfg(chan, channel, params) != 0) {\n \t\t\tprintf(\"pctl_cfg fail, reset\\n\");\n \t\t\treturn -EIO;\n \t\t}\n@@ -1094,17 +1091,16 @@ static int sdram_init(struct dram_info *dram,\n \t\tif (dramtype == LPDDR3)\n \t\t\tudelay(10);\n \n-\t\tif (data_training(chan, channel,\n-\t\t\t\t sdram_params, PI_FULL_TRAINING)) {\n+\t\tif (data_training(chan, channel, params, PI_FULL_TRAINING)) {\n \t\t\tprintf(\"SDRAM initialization failed, reset\\n\");\n \t\t\treturn -EIO;\n \t\t}\n \n-\t\tset_ddrconfig(chan, sdram_params, channel,\n-\t\t\t sdram_params->ch[channel].ddrconfig);\n+\t\tset_ddrconfig(chan, params, channel,\n+\t\t\t params->ch[channel].ddrconfig);\n \t}\n-\tdram_all_config(dram, sdram_params);\n-\tswitch_to_phy_index1(dram, sdram_params);\n+\tdram_all_config(dram, params);\n+\tswitch_to_phy_index1(dram, params);\n \n \tdebug(\"Finish SDRAM initialization...\\n\");\n \treturn 0;\n", "prefixes": [ "U-Boot", "v3", "03/15" ] }