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GET /api/patches/1132161/?format=api
{ "id": 1132161, "url": "http://patchwork.ozlabs.org/api/patches/1132161/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190715182110.21336-2-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190715182110.21336-2-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2019-07-15T18:20:56", "name": "[U-Boot,v3,01/15] ram: rk3399: Fix code warnings", "commit_ref": "63f4d716b1094f293096b2ef652be2b76c670ac9", "pull_url": null, "state": "accepted", "archived": false, "hash": "184b4fb8959d91383b57aeba0cd442b0952b4068", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 93623, "url": "http://patchwork.ozlabs.org/api/users/93623/?format=api", "username": "kevery", "first_name": "Kever", "last_name": "Yang", "email": "ykai007@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190715182110.21336-2-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 119571, "url": "http://patchwork.ozlabs.org/api/series/119571/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=119571", "date": "2019-07-15T18:20:55", "name": "ram: rk3399: Code cleanup", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/119571/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1132161/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1132161/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"NUbRoT4L\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 45nX1h0BL2z9s3l\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 16 Jul 2019 04:22:15 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid A0D10C21FC8; Mon, 15 Jul 2019 18:21:40 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 31514C21FA5;\n\tMon, 15 Jul 2019 18:21:36 +0000 (UTC)", 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s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=2PZmOlDxLIZ3hi1XK1/L5fS7ODHlI/voHjGPAwKMURw=;\n\tb=N5pz9kRKu7RGn8c4Xf/YO7UjHLB/56LGP9tDkdUjgDm18mgz8UfnLm955+FCE7Lawl\n\t7ky5+ZNHCLbEgsB1RvgFMfoNpNcXxzfZvNxDkL7SPz0E+YOAprBombbfknmmJn/aSNpn\n\tpYLerx/rJ9YlaDig/sVU5oBNF9vSSLYv9B6/Tro17ID9S5Qr82ywg22iEt/Rt1x6AkQH\n\tQjcsEjPjPMku2FYSOwOmAP78zXK5lxzJR6xZ/rBTe0NmCb1GRNPPmA+QBtgbS0SqU1GN\n\tbas72k8IKUnR4Jd+5LgZLTN1829GCQplox5YuOGBYtD3zcT7gcFR5r7QECoatkUMWuhB\n\tMzCQ==", "X-Gm-Message-State": "APjAAAUZrDj+2bNsU4Wro+e9ahGWywM9qdDGGxElduG7iI1ie7Mic94x\n\tfKidCQ9lvHOQauHVFXfFfgbquqG61GIECw==", "X-Google-Smtp-Source": "APXvYqxdyMIA8WbNp/Vg/SU/1F5HHraJvVG1qfYwDJ1xf5u91nk97WDaFd0GhaxWATx8marlDKzdIw==", "X-Received": "by 2002:a17:90a:e397:: with SMTP id\n\tb23mr30897202pjz.117.1563214884535; \n\tMon, 15 Jul 2019 11:21:24 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Simon Glass <sjg@chromium.org>,\n\tPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>,\n\tKever Yang <kever.yang@rock-chips.com>,\n\tYouMin Chen <cym@rock-chips.com>, u-boot@lists.denx.de", "Date": "Mon, 15 Jul 2019 23:50:56 +0530", "Message-Id": "<20190715182110.21336-2-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20190715182110.21336-1-jagan@amarulasolutions.com>", "References": "<20190715182110.21336-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com,\n\tlinux-amarula@amarulasolutions.com,\n\tManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>", "Subject": "[U-Boot] [PATCH v3 01/15] ram: rk3399: Fix code warnings", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "Fix checkpatch warninigs on sdram_rk3399.c like\n- Avoid CamelCase\n- Unnecessary parentheses\n- Alignment should match open parenthesis\n- multiple blank lines\n- misspelled\n- spaces preferred around that '>>'\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\n---\n drivers/ram/rockchip/sdram_rk3399.c | 48 ++++++++++++++---------------\n 1 file changed, 24 insertions(+), 24 deletions(-)", "diff": "diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c\nindex 52518656c4..541e4a4b1e 100644\n--- a/drivers/ram/rockchip/sdram_rk3399.c\n+++ b/drivers/ram/rockchip/sdram_rk3399.c\n@@ -47,7 +47,7 @@ struct dram_info {\n #define PRESET_GPIO0_HOLD(n)\t((0x1 << (7 + 16)) | ((n) << 7))\n #define PRESET_GPIO1_HOLD(n)\t((0x1 << (8 + 16)) | ((n) << 8))\n \n-#define PHY_DRV_ODT_Hi_Z\t0x0\n+#define PHY_DRV_ODT_HI_Z\t0x0\n #define PHY_DRV_ODT_240\t\t0x1\n #define PHY_DRV_ODT_120\t\t0x8\n #define PHY_DRV_ODT_80\t\t0x9\n@@ -150,7 +150,7 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,\n \t\t\t((16 - row) << 24));\n \t/* PI_41 PI_CS_MAP:RW:24:4 */\n \tclrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);\n-\tif ((sdram_ch->rank == 1) && (sdram_params->base.dramtype == DDR3))\n+\tif (sdram_ch->rank == 1 && sdram_params->base.dramtype == DDR3)\n \t\twritel(0x2EC7FFFF, &denali_pi[34]);\n }\n \n@@ -166,10 +166,10 @@ static void set_ds_odt(const struct chan_info *chan,\n \tu32 reg_value;\n \n \tif (sdram_params->base.dramtype == LPDDR4) {\n-\t\ttsel_rd_select_p = PHY_DRV_ODT_Hi_Z;\n+\t\ttsel_rd_select_p = PHY_DRV_ODT_HI_Z;\n \t\ttsel_wr_select_p = PHY_DRV_ODT_40;\n \t\tca_tsel_wr_select_p = PHY_DRV_ODT_40;\n-\t\ttsel_idle_select_p = PHY_DRV_ODT_Hi_Z;\n+\t\ttsel_idle_select_p = PHY_DRV_ODT_HI_Z;\n \n \t\ttsel_rd_select_n = PHY_DRV_ODT_240;\n \t\ttsel_wr_select_n = PHY_DRV_ODT_40;\n@@ -181,10 +181,10 @@ static void set_ds_odt(const struct chan_info *chan,\n \t\tca_tsel_wr_select_p = PHY_DRV_ODT_48;\n \t\ttsel_idle_select_p = PHY_DRV_ODT_240;\n \n-\t\ttsel_rd_select_n = PHY_DRV_ODT_Hi_Z;\n+\t\ttsel_rd_select_n = PHY_DRV_ODT_HI_Z;\n \t\ttsel_wr_select_n = PHY_DRV_ODT_34_3;\n \t\tca_tsel_wr_select_n = PHY_DRV_ODT_48;\n-\t\ttsel_idle_select_n = PHY_DRV_ODT_Hi_Z;\n+\t\ttsel_idle_select_n = PHY_DRV_ODT_HI_Z;\n \t} else {\n \t\ttsel_rd_select_p = PHY_DRV_ODT_240;\n \t\ttsel_wr_select_p = PHY_DRV_ODT_34_3;\n@@ -294,7 +294,7 @@ static void set_ds_odt(const struct chan_info *chan,\n }\n \n static int phy_io_config(const struct chan_info *chan,\n-\t\t\t const struct rk3399_sdram_params *sdram_params)\n+\t\t\t const struct rk3399_sdram_params *sdram_params)\n {\n \tu32 *denali_phy = chan->publ->denali_phy;\n \tu32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;\n@@ -423,7 +423,6 @@ static int phy_io_config(const struct chan_info *chan,\n \t/* PHY_939 PHY_PAD_CS_DRIVE */\n \tclrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);\n \n-\n \t/* speed setting */\n \tif (sdram_params->base.ddr_freq < 400)\n \t\tspeed = 0x0;\n@@ -492,7 +491,7 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,\n \tsetbits_le32(&denali_pi[0], START);\n \tsetbits_le32(&denali_ctl[0], START);\n \n-\t/* Wating for phy DLL lock */\n+\t/* Waiting for phy DLL lock */\n \twhile (1) {\n \t\ttmp = readl(&denali_phy[920]);\n \t\ttmp1 = readl(&denali_phy[921]);\n@@ -547,12 +546,12 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,\n \t/* PHY_DLL_RST_EN */\n \tclrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);\n \n-\t/* Wating for PHY and DRAM init complete */\n+\t/* Waiting for PHY and DRAM init complete */\n \ttmp = get_timer(0);\n \tdo {\n \t\tif (get_timer(tmp) > timeout_ms) {\n \t\t\tpr_err(\"DRAM (%s): phy failed to lock within %ld ms\\n\",\n-\t\t\t __func__, timeout_ms);\n+\t\t\t __func__, timeout_ms);\n \t\t\treturn -ETIME;\n \t\t}\n \t} while (!(readl(&denali_ctl[203]) & (1 << 3)));\n@@ -569,7 +568,7 @@ static void select_per_cs_training_index(const struct chan_info *chan,\n \tu32 *denali_phy = chan->publ->denali_phy;\n \n \t/* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */\n-\tif ((readl(&denali_phy[84])>>16) & 1) {\n+\tif ((readl(&denali_phy[84]) >> 16) & 1) {\n \t\t/*\n \t\t * PHY_8/136/264/392\n \t\t * phy_per_cs_training_index_X 1bit offset_24\n@@ -646,7 +645,7 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,\n \t\t\tif ((((tmp >> 11) & 0x1) == 0x1) &&\n \t\t\t (((tmp >> 13) & 0x1) == 0x1) &&\n \t\t\t (((tmp >> 5) & 0x1) == 0x0) &&\n-\t\t\t (obs_err == 0))\n+\t\t\t obs_err == 0)\n \t\t\t\tbreak;\n \t\t\telse if ((((tmp >> 5) & 0x1) == 0x1) ||\n \t\t\t\t (obs_err == 1))\n@@ -700,7 +699,7 @@ static int data_training_wl(const struct chan_info *chan, u32 channel,\n \t\t\tif ((((tmp >> 10) & 0x1) == 0x1) &&\n \t\t\t (((tmp >> 13) & 0x1) == 0x1) &&\n \t\t\t (((tmp >> 4) & 0x1) == 0x0) &&\n-\t\t\t (obs_err == 0))\n+\t\t\t obs_err == 0)\n \t\t\t\tbreak;\n \t\t\telse if ((((tmp >> 4) & 0x1) == 0x1) ||\n \t\t\t\t (obs_err == 1))\n@@ -759,7 +758,7 @@ static int data_training_rg(const struct chan_info *chan, u32 channel,\n \t\t\tif ((((tmp >> 9) & 0x1) == 0x1) &&\n \t\t\t (((tmp >> 13) & 0x1) == 0x1) &&\n \t\t\t (((tmp >> 3) & 0x1) == 0x0) &&\n-\t\t\t (obs_err == 0))\n+\t\t\t obs_err == 0)\n \t\t\t\tbreak;\n \t\t\telse if ((((tmp >> 3) & 0x1) == 0x1) ||\n \t\t\t\t (obs_err == 1))\n@@ -955,8 +954,10 @@ static void dram_all_config(struct dram_info *dram,\n \t\tsys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel);\n \t\tsys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel);\n \t\tsys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel);\n-\t\tsys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(channel);\n-\t\tsys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(channel);\n+\t\tsys_reg |= (info->cs0_row - 13) <<\n+\t\t\t SYS_REG_CS0_ROW_SHIFT(channel);\n+\t\tsys_reg |= (info->cs1_row - 13) <<\n+\t\t\t SYS_REG_CS1_ROW_SHIFT(channel);\n \t\tsys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel);\n \t\tsys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel);\n \n@@ -991,7 +992,7 @@ static void dram_all_config(struct dram_info *dram,\n }\n \n static int switch_to_phy_index1(struct dram_info *dram,\n-\t\t\t\t const struct rk3399_sdram_params *sdram_params)\n+\t\t\t\tconst struct rk3399_sdram_params *sdram_params)\n {\n \tu32 channel;\n \tu32 *denali_phy;\n@@ -1026,7 +1027,7 @@ static int switch_to_phy_index1(struct dram_info *dram,\n \t\tdenali_phy = dram->chan[channel].publ->denali_phy;\n \t\tclrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);\n \t\tret = data_training(&dram->chan[channel], channel,\n-\t\t\t\t sdram_params, PI_FULL_TRAINING);\n+\t\t\t\t sdram_params, PI_FULL_TRAINING);\n \t\tif (ret) {\n \t\t\tdebug(\"index1 training failed\\n\");\n \t\t\treturn ret;\n@@ -1116,8 +1117,8 @@ static int conv_of_platdata(struct udevice *dev)\n \tint ret;\n \n \tret = regmap_init_mem_platdata(dev, dtplat->reg,\n-\t\t\tARRAY_SIZE(dtplat->reg) / 2,\n-\t\t\t&plat->map);\n+\t\t\t\t ARRAY_SIZE(dtplat->reg) / 2,\n+\t\t\t\t &plat->map);\n \tif (ret)\n \t\treturn ret;\n \n@@ -1199,8 +1200,8 @@ static int rk3399_dmc_probe(struct udevice *dev)\n \tpriv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);\n \tdebug(\"%s: pmugrf=%p\\n\", __func__, priv->pmugrf);\n \tpriv->info.base = CONFIG_SYS_SDRAM_BASE;\n-\tpriv->info.size = rockchip_sdram_size(\n-\t\t\t(phys_addr_t)&priv->pmugrf->os_reg2);\n+\tpriv->info.size =\n+\t\trockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);\n #endif\n \treturn 0;\n }\n@@ -1218,7 +1219,6 @@ static struct ram_ops rk3399_dmc_ops = {\n \t.get_info = rk3399_dmc_get_info,\n };\n \n-\n static const struct udevice_id rk3399_dmc_ids[] = {\n \t{ .compatible = \"rockchip,rk3399-dmc\" },\n \t{ }\n", "prefixes": [ "U-Boot", "v3", "01/15" ] }