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GET /api/patches/1130382/?format=api
{ "id": 1130382, "url": "http://patchwork.ozlabs.org/api/patches/1130382/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190710130026.28009-1-chuanhua.han@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190710130026.28009-1-chuanhua.han@nxp.com>", "list_archive_url": null, "date": "2019-07-10T13:00:20", "name": "[U-Boot,v4,1/7] armv8: lx2160a: The lx2160a platform supports the I2C driver model.", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "e4826d6b69eda6125482654e57ecbc0e52cb51ac", "submitter": { "id": 74737, "url": "http://patchwork.ozlabs.org/api/people/74737/?format=api", "name": "Chuanhua Han", "email": "chuanhua.han@nxp.com" }, "delegate": { "id": 2467, "url": "http://patchwork.ozlabs.org/api/users/2467/?format=api", "username": "prabhu_kush", "first_name": "Prabhakar", "last_name": "Kushwaha", "email": "prabhakar@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190710130026.28009-1-chuanhua.han@nxp.com/mbox/", "series": [ { "id": 118772, "url": "http://patchwork.ozlabs.org/api/series/118772/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=118772", "date": "2019-07-10T13:00:20", "name": "[U-Boot,v4,1/7] armv8: lx2160a: The lx2160a platform supports the I2C driver model.", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/118772/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1130382/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1130382/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=nxp.com" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 45kKKR6wh4z9sNT\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 10 Jul 2019 23:09:47 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 7A991C21F85; Wed, 10 Jul 2019 13:09:43 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id D1E32C21E7F;\n\tWed, 10 Jul 2019 13:09:39 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 112D7C21E0D; Wed, 10 Jul 2019 13:09:39 +0000 (UTC)", "from inva020.nxp.com (inva020.nxp.com [92.121.34.13])\n\tby lists.denx.de (Postfix) with ESMTPS id 8BB81C21DFA\n\tfor <u-boot@lists.denx.de>; Wed, 10 Jul 2019 13:09:38 +0000 (UTC)", "from inva020.nxp.com (localhost [127.0.0.1])\n\tby inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 171101A0794;\n\tWed, 10 Jul 2019 15:09:38 +0200 (CEST)", "from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com\n\t[165.114.16.14])\n\tby inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id E6B161A00D7;\n\tWed, 10 Jul 2019 15:09:33 +0200 (CEST)", "from titan.ap.freescale.net (TITAN.ap.freescale.net\n\t[10.192.208.233])\n\tby invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id B81C2402DB;\n\tWed, 10 Jul 2019 21:09:28 +0800 (SGT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0", "From": "Chuanhua Han <chuanhua.han@nxp.com>", "To": "albert.u.boot@aribaud.net, priyanka.jain@nxp.com, udit.agarwal@nxp.com, \n\ths@denx.de, prabhakar.kushwaha@nxp.com", "Date": "Wed, 10 Jul 2019 21:00:20 +0800", "Message-Id": "<20190710130026.28009-1-chuanhua.han@nxp.com>", "X-Mailer": "git-send-email 2.9.5", "X-Virus-Scanned": "ClamAV using ClamSMTP", "Cc": "u-boot@lists.denx.de, Chuanhua Han <chuanhua.han@nxp.com>", "Subject": "[U-Boot] [PATCH v4 1/7] armv8: lx2160a: The lx2160a platform\n\tsupports the I2C driver model.", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C\nAPI when DM_I2C is used.When DM_I2C_COMPAT is not enabled for\ncompilation, a compilation error will be generated. This patch solves\nthe problem that the i2c-related api of the lx2160a platform does not\nsupport dm.\n\nSigned-off-by: Chuanhua Han <chuanhua.han@nxp.com>\n---\nChanges in v4:\n\t- No change.\nChanges in v3:\n\t- No change.\nChanges in v2: \n\t- No change.\n\n arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 8 ---\n board/freescale/common/emc2305.c | 21 +++++++\n board/freescale/common/qixis.c | 17 ++++++\n board/freescale/common/sys_eeprom.c | 84 +++++++++++++++++++++++++++--\n board/freescale/common/vid.c | 84 +++++++++++++++++++++++++++++\n board/freescale/lx2160a/lx2160a.c | 8 +++\n drivers/ddr/fsl/main.c | 36 ++++++++++++-\n 7 files changed, 245 insertions(+), 13 deletions(-)", "diff": "diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\nindex 3f6c983..ffda02a 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig\n@@ -235,14 +235,6 @@ config ARCH_LX2160A\n \tselect ARCH_EARLY_INIT_R\n \tselect BOARD_EARLY_INIT_F\n \tselect SYS_I2C_MXC\n-\tselect SYS_I2C_MXC_I2C1\n-\tselect SYS_I2C_MXC_I2C2\n-\tselect SYS_I2C_MXC_I2C3\n-\tselect SYS_I2C_MXC_I2C4\n-\tselect SYS_I2C_MXC_I2C5\n-\tselect SYS_I2C_MXC_I2C6\n-\tselect SYS_I2C_MXC_I2C7\n-\tselect SYS_I2C_MXC_I2C8\n \timply DISTRO_DEFAULTS\n \timply PANIC_HANG\n \timply SCSI\ndiff --git a/board/freescale/common/emc2305.c b/board/freescale/common/emc2305.c\nindex 8523084..b1ca051 100644\n--- a/board/freescale/common/emc2305.c\n+++ b/board/freescale/common/emc2305.c\n@@ -24,10 +24,22 @@ void set_fan_speed(u8 data)\n \t\t\t I2C_EMC2305_FAN5};\n \n \tfor (index = 0; index < NUM_OF_FANS; index++) {\n+#ifndef CONFIG_DM_I2C\n \t\tif (i2c_write(I2C_EMC2305_ADDR, Fan[index], 1, &data, 1) != 0) {\n \t\t\tprintf(\"Error: failed to change fan speed @%x\\n\",\n \t\t\t Fan[index]);\n \t\t}\n+#else\n+\t\tstruct udevice *dev;\n+\n+\t\tif (i2c_get_chip_for_busnum(0, I2C_EMC2305_ADDR, 1, &dev))\n+\t\t\tcontinue;\n+\n+\t\tif (dm_i2c_write(dev, Fan[index], &data, 1) != 0) {\n+\t\t\tprintf(\"Error: failed to change fan speed @%x\\n\",\n+\t\t\t Fan[index]);\n+\t\t}\n+#endif\n \t}\n }\n \n@@ -36,6 +48,15 @@ void emc2305_init(void)\n \tu8 data;\n \n \tdata = I2C_EMC2305_CMD;\n+#ifndef CONFIG_DM_I2C\n \tif (i2c_write(I2C_EMC2305_ADDR, I2C_EMC2305_CONF, 1, &data, 1) != 0)\n \t\tprintf(\"Error: failed to configure EMC2305\\n\");\n+#else\n+\tstruct udevice *dev;\n+\n+\tif (!i2c_get_chip_for_busnum(0, I2C_EMC2305_ADDR, 1, &dev))\n+\t\tif (dm_i2c_write(dev, I2C_EMC2305_CONF, &data, 1))\n+\t\t\tprintf(\"Error: failed to configure EMC2305\\n\");\n+#endif\n+\n }\ndiff --git a/board/freescale/common/qixis.c b/board/freescale/common/qixis.c\nindex f1b98bc..2c4c4ae 100644\n--- a/board/freescale/common/qixis.c\n+++ b/board/freescale/common/qixis.c\n@@ -24,13 +24,30 @@\n #ifdef CONFIG_SYS_I2C_FPGA_ADDR\n u8 qixis_read_i2c(unsigned int reg)\n {\n+#ifndef CONFIG_DM_I2C\n \treturn i2c_reg_read(CONFIG_SYS_I2C_FPGA_ADDR, reg);\n+#else\n+\tstruct udevice *dev;\n+\n+\tif (i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev))\n+\t\treturn 0xff;\n+\n+\treturn dm_i2c_reg_read(dev, reg);\n+#endif\n }\n \n void qixis_write_i2c(unsigned int reg, u8 value)\n {\n \tu8 val = value;\n+#ifndef CONFIG_DM_I2C\n \ti2c_reg_write(CONFIG_SYS_I2C_FPGA_ADDR, reg, val);\n+#else\n+\tstruct udevice *dev;\n+\n+\tif (!i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_FPGA_ADDR, 1, &dev))\n+\t\tdm_i2c_reg_write(dev, reg, val);\n+#endif\n+\n }\n #endif\n \ndiff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c\nindex ab0fe0b..ff76cef 100644\n--- a/board/freescale/common/sys_eeprom.c\n+++ b/board/freescale/common/sys_eeprom.c\n@@ -148,23 +148,42 @@ static int read_eeprom(void)\n {\n \tint ret;\n #ifdef CONFIG_SYS_EEPROM_BUS_NUM\n+#ifndef CONFIG_DM_I2C\n \tunsigned int bus;\n #endif\n+#endif\n \n \tif (has_been_read)\n \t\treturn 0;\n \n #ifdef CONFIG_SYS_EEPROM_BUS_NUM\n+#ifndef CONFIG_DM_I2C\n \tbus = i2c_get_bus_num();\n \ti2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);\n #endif\n+#endif\n \n-\tret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,\n-\t\t(void *)&e, sizeof(e));\n+#ifndef CONFIG_DM_I2C\n+\tret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,\n+\t\t CONFIG_SYS_I2C_EEPROM_ADDR_LEN,\n+\t\t (void *)&e, sizeof(e));\n+#else\n+\tstruct udevice *dev;\n+#ifdef CONFIG_SYS_EEPROM_BUS_NUM\n+\tret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,\n+\t\t\t\t CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev);\n+#else\n+\tret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR, 1, &dev);\n+#endif\n+\tif (!ret)\n+\t\tret = dm_i2c_read(dev, 0, (void *)&e, sizeof(e));\n+#endif\n \n #ifdef CONFIG_SYS_EEPROM_BUS_NUM\n+#ifndef CONFIG_DM_I2C\n \ti2c_set_bus_num(bus);\n #endif\n+#endif\n \n #ifdef DEBUG\n \tshow_eeprom();\n@@ -198,8 +217,10 @@ static int prog_eeprom(void)\n \tint i;\n \tvoid *p;\n #ifdef CONFIG_SYS_EEPROM_BUS_NUM\n+#ifndef CONFIG_DM_I2C\n \tunsigned int bus;\n #endif\n+#endif\n \n \t/* Set the reserved values to 0xFF */\n #ifdef CONFIG_SYS_I2C_EEPROM_NXID\n@@ -210,10 +231,12 @@ static int prog_eeprom(void)\n #endif\n \tupdate_crc();\n \n+#ifndef CONFIG_DM_I2C\n #ifdef CONFIG_SYS_EEPROM_BUS_NUM\n \tbus = i2c_get_bus_num();\n \ti2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);\n #endif\n+#endif\n \n \t/*\n \t * The AT24C02 datasheet says that data can only be written in page\n@@ -221,8 +244,26 @@ static int prog_eeprom(void)\n \t * complete a given write.\n \t */\n \tfor (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) {\n-\t\tret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,\n+#ifndef CONFIG_DM_I2C\n+\t\tret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i,\n+\t\t\t\tCONFIG_SYS_I2C_EEPROM_ADDR_LEN,\n \t\t\t\tp, min((int)(sizeof(e) - i), 8));\n+#else\n+\t\tstruct udevice *dev;\n+#ifdef CONFIG_SYS_EEPROM_BUS_NUM\n+\t\tret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,\n+\t\t\t\t\t CONFIG_SYS_I2C_EEPROM_ADDR,\n+\t\t\t\t\t CONFIG_SYS_I2C_EEPROM_ADDR_LEN,\n+\t\t\t\t\t &dev);\n+#else\n+\t\tret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,\n+\t\t\t\t\t CONFIG_SYS_I2C_EEPROM_ADDR_LEN,\n+\t\t\t\t\t &dev);\n+#endif\n+\t\tif (!ret)\n+\t\t\tret = dm_i2c_write(dev, i, p, min((int)(sizeof(e) - i),\n+\t\t\t\t\t\t\t 8));\n+#endif\n \t\tif (ret)\n \t\t\tbreak;\n \t\tudelay(5000);\t/* 5ms write cycle timing */\n@@ -232,15 +273,34 @@ static int prog_eeprom(void)\n \t\t/* Verify the write by reading back the EEPROM and comparing */\n \t\tstruct eeprom e2;\n \n+#ifndef CONFIG_DM_I2C\n \t\tret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,\n-\t\t\tCONFIG_SYS_I2C_EEPROM_ADDR_LEN, (void *)&e2, sizeof(e2));\n+\t\t\t CONFIG_SYS_I2C_EEPROM_ADDR_LEN,\n+\t\t\t (void *)&e2, sizeof(e2));\n+#else\n+\t\tstruct udevice *dev;\n+#ifdef CONFIG_SYS_EEPROM_BUS_NUM\n+\t\tret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,\n+\t\t\t\t\t CONFIG_SYS_I2C_EEPROM_ADDR,\n+\t\t\t\t\t CONFIG_SYS_I2C_EEPROM_ADDR_LEN,\n+\t\t\t\t\t &dev);\n+#else\n+\t\tret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,\n+\t\t\t\t\t CONFIG_SYS_I2C_EEPROM_ADDR_LEN,\n+\t\t\t\t\t &dev);\n+#endif\n+\t\tif (!ret)\n+\t\t\tret = dm_i2c_read(dev, 0, (void *)&e2, sizeof(e2));\n+#endif\n \t\tif (!ret && memcmp(&e, &e2, sizeof(e)))\n \t\t\tret = -1;\n \t}\n \n+#ifndef CONFIG_DM_I2C\n #ifdef CONFIG_SYS_EEPROM_BUS_NUM\n \ti2c_set_bus_num(bus);\n #endif\n+#endif\n \n \tif (ret) {\n \t\tprintf(\"Programming failed.\\n\");\n@@ -528,8 +588,24 @@ unsigned int get_cpu_board_revision(void)\n \t\tu8 minor; /* 0x05 Board revision, minor */\n \t} be;\n \n+#ifndef CONFIG_DM_I2C\n \ti2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,\n \t\t(void *)&be, sizeof(be));\n+#else\n+\tstruct udevice *dev;\n+#ifdef CONFIG_SYS_EEPROM_BUS_NUM\n+\tret = i2c_get_chip_for_busnum(CONFIG_SYS_EEPROM_BUS_NUM,\n+\t\t\t\t CONFIG_SYS_I2C_EEPROM_ADDR,\n+\t\t\t\t CONFIG_SYS_I2C_EEPROM_ADDR_LEN,\n+\t\t\t\t &dev);\n+#else\n+\tret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_EEPROM_ADDR,\n+\t\t\t\t CONFIG_SYS_I2C_EEPROM_ADDR_LEN,\n+\t\t\t\t &dev)\n+#endif\n+\tif (!ret)\n+\t\tdm_i2c_read(dev, 0, (void *)&be, sizeof(be));\n+#endif\n \n \tif (be.id != (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D'))\n \t\treturn MPC85XX_CPU_BOARD_REV(0, 0);\ndiff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c\nindex 0ca389c..49b4cd1 100644\n--- a/board/freescale/common/vid.c\n+++ b/board/freescale/common/vid.c\n@@ -60,13 +60,23 @@ static int find_ir_chip_on_i2c(void)\n \tu8 byte;\n \tint i;\n \tconst int ir_i2c_addr[] = {0x38, 0x08, 0x09};\n+#ifdef CONFIG_DM_I2C\n+\tstruct udevice *dev;\n+#endif\n \n \t/* Check all the address */\n \tfor (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) {\n \t\ti2caddress = ir_i2c_addr[i];\n+#ifndef CONFIG_DM_I2C\n \t\tret = i2c_read(i2caddress,\n \t\t\t IR36021_MFR_ID_OFFSET, 1, (void *)&byte,\n \t\t\t sizeof(byte));\n+#else\n+\t\tret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);\n+\t\tif (!ret)\n+\t\t\tret = dm_i2c_read(dev, IR36021_MFR_ID_OFFSET,\n+\t\t\t\t\t (void *)&byte, sizeof(byte));\n+#endif\n \t\tif ((ret >= 0) && (byte == IR36021_MFR_ID))\n \t\t\treturn i2caddress;\n \t}\n@@ -102,11 +112,21 @@ static int read_voltage_from_INA220(int i2caddress)\n \tint i, ret, voltage_read = 0;\n \tu16 vol_mon;\n \tu8 buf[2];\n+#ifdef CONFIG_DM_I2C\n+\tstruct udevice *dev;\n+#endif\n \n \tfor (i = 0; i < NUM_READINGS; i++) {\n+#ifndef CONFIG_DM_I2C\n \t\tret = i2c_read(I2C_VOL_MONITOR_ADDR,\n \t\t\t I2C_VOL_MONITOR_BUS_V_OFFSET, 1,\n \t\t\t (void *)&buf, 2);\n+#else\n+\t\tret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);\n+\t\tif (!ret)\n+\t\t\tret = dm_i2c_read(dev, I2C_VOL_MONITOR_BUS_V_OFFSET,\n+\t\t\t\t\t (void *)&buf, 2);\n+#endif\n \t\tif (ret) {\n \t\t\tprintf(\"VID: failed to read core voltage\\n\");\n \t\t\treturn ret;\n@@ -135,11 +155,21 @@ static int read_voltage_from_IR(int i2caddress)\n \tint i, ret, voltage_read = 0;\n \tu16 vol_mon;\n \tu8 buf;\n+#ifdef CONFIG_DM_I2C\n+\tstruct udevice *dev;\n+#endif\n \n \tfor (i = 0; i < NUM_READINGS; i++) {\n+#ifndef CONFIG_DM_I2C\n \t\tret = i2c_read(i2caddress,\n \t\t\t IR36021_LOOP1_VOUT_OFFSET,\n \t\t\t 1, (void *)&buf, 1);\n+#else\n+\t\tret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);\n+\t\tif (!ret)\n+\t\t\tret = dm_i2c_read(dev, IR36021_LOOP1_VOUT_OFFSET,\n+\t\t\t\t\t (void *)&buf, 1);\n+#endif\n \t\tif (ret) {\n \t\t\tprintf(\"VID: failed to read vcpu\\n\");\n \t\t\treturn ret;\n@@ -178,17 +208,33 @@ static int read_voltage_from_LTC(int i2caddress)\n \tint ret, vcode = 0;\n \tu8 chan = PWM_CHANNEL0;\n \n+#ifndef CONFIG_DM_I2C\n \t/* select the PAGE 0 using PMBus commands PAGE for VDD*/\n \tret = i2c_write(I2C_VOL_MONITOR_ADDR,\n \t\t\tPMBUS_CMD_PAGE, 1, &chan, 1);\n+#else\n+\tstruct udevice *dev;\n+\n+\tret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);\n+\tif (!ret)\n+\t\tret = dm_i2c_write(dev, PMBUS_CMD_PAGE, &chan, 1);\n+#endif\n \tif (ret) {\n \t\tprintf(\"VID: failed to select VDD Page 0\\n\");\n \t\treturn ret;\n \t}\n \n+#ifndef CONFIG_DM_I2C\n \t/*read the output voltage using PMBus command READ_VOUT*/\n \tret = i2c_read(I2C_VOL_MONITOR_ADDR,\n \t\t PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);\n+#else\n+\tret = dm_i2c_read(dev, PMBUS_CMD_READ_VOUT, (void *)&vcode, 2);\n+\tif (ret) {\n+\t\tprintf(\"VID: failed to read the volatge\\n\");\n+\t\treturn ret;\n+\t}\n+#endif\n \tif (ret) {\n \t\tprintf(\"VID: failed to read the volatge\\n\");\n \t\treturn ret;\n@@ -293,8 +339,18 @@ static int set_voltage_to_IR(int i2caddress, int vdd)\n \tvid = DIV_ROUND_UP(vdd - 245, 5);\n #endif\n \n+#ifndef CONFIG_DM_I2C\n \tret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET,\n \t\t\t1, (void *)&vid, sizeof(vid));\n+#else\n+\tstruct udevice *dev;\n+\n+\tret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);\n+\tif (!ret)\n+\t\tret = dm_i2c_write(dev, IR36021_LOOP1_MANUAL_ID_OFFSET,\n+\t\t\t\t (void *)&vid, sizeof(vid));\n+\n+#endif\n \tif (ret) {\n \t\tprintf(\"VID: failed to write VID\\n\");\n \t\treturn -1;\n@@ -330,8 +386,17 @@ static int set_voltage_to_LTC(int i2caddress, int vdd)\n \t\t\tvdd & 0xFF, (vdd & 0xFF00) >> 8};\n \n \t/* Write the desired voltage code to the regulator */\n+#ifndef CONFIG_DM_I2C\n \tret = i2c_write(I2C_VOL_MONITOR_ADDR,\n \t\t\tPMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);\n+#else\n+\tstruct udevice *dev;\n+\n+\tret = i2c_get_chip_for_busnum(0, I2C_VOL_MONITOR_ADDR, 1, &dev);\n+\tif (!ret)\n+\t\tret = dm_i2c_write(dev, PMBUS_CMD_PAGE_PLUS_WRITE,\n+\t\t\t\t (void *)&buff, 5);\n+#endif\n \tif (ret) {\n \t\tprintf(\"VID: I2C failed to write to the volatge regulator\\n\");\n \t\treturn -1;\n@@ -515,14 +580,24 @@ int adjust_vdd(ulong vdd_override)\n \t}\n \n \t/* check IR chip work on Intel mode*/\n+#ifndef CONFIG_DM_I2C\n \tret = i2c_read(i2caddress,\n \t\t IR36021_INTEL_MODE_OOFSET,\n \t\t 1, (void *)&buf, 1);\n+#else\n+\tstruct udevice *dev;\n+\n+\tret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);\n+\tif (!ret)\n+\t\tret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET,\n+\t\t\t\t (void *)&buf, 1);\n+#endif\n \tif (ret) {\n \t\tprintf(\"VID: failed to read IR chip mode.\\n\");\n \t\tret = -1;\n \t\tgoto exit;\n \t}\n+\n \tif ((buf & IR36021_MODE_MASK) != IR36021_INTEL_MODE) {\n \t\tprintf(\"VID: IR Chip is not used in Intel mode.\\n\");\n \t\tret = -1;\n@@ -687,9 +762,18 @@ int adjust_vdd(ulong vdd_override)\n \t}\n \n \t/* check IR chip work on Intel mode*/\n+#ifndef CONFIG_DM_I2C\n \tret = i2c_read(i2caddress,\n \t\t IR36021_INTEL_MODE_OOFSET,\n \t\t 1, (void *)&buf, 1);\n+#else\n+\tstruct udevice *dev;\n+\n+\tret = i2c_get_chip_for_busnum(0, i2caddress, 1, &dev);\n+\tif (!ret)\n+\t\tret = dm_i2c_read(dev, IR36021_INTEL_MODE_OOFSET,\n+\t\t\t\t (void *)&buf, 1);\n+#endif\n \tif (ret) {\n \t\tprintf(\"VID: failed to read IR chip mode.\\n\");\n \t\tret = -1;\ndiff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c\nindex 3b4cb86..679afd2 100644\n--- a/board/freescale/lx2160a/lx2160a.c\n+++ b/board/freescale/lx2160a/lx2160a.c\n@@ -74,7 +74,15 @@ int select_i2c_ch_pca9547(u8 ch)\n {\n \tint ret;\n \n+#ifndef CONFIG_DM_I2C\n \tret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);\n+#else\n+\tstruct udevice *dev;\n+\n+\tret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);\n+\tif (!ret)\n+\t\tret = dm_i2c_write(dev, 0, &ch, 1);\n+#endif\n \tif (ret) {\n \t\tputs(\"PCA: failed to select proper channel\\n\");\n \t\treturn ret;\ndiff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c\nindex e1f69a1..ac0783b 100644\n--- a/drivers/ddr/fsl/main.c\n+++ b/drivers/ddr/fsl/main.c\n@@ -92,7 +92,10 @@ static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)\n \tuint8_t dummy = 0;\n #endif\n \n+#ifndef CONFIG_DM_I2C\n \ti2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);\n+#endif\n+\n \n #ifdef CONFIG_SYS_FSL_DDR4\n \t/*\n@@ -101,6 +104,7 @@ static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)\n \t * To access the upper 256 bytes, we need to set EE page address to 1\n \t * See Jedec standar No. 21-C for detail\n \t */\n+#ifndef CONFIG_DM_I2C\n \ti2c_write(SPD_SPA0_ADDRESS, 0, 1, &dummy, 1);\n \tret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 256);\n \tif (!ret) {\n@@ -111,8 +115,38 @@ static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)\n \t\t\t\t (int)sizeof(generic_spd_eeprom_t) - 256));\n \t}\n #else\n+\tstruct udevice *dev;\n+\tint read_len = min(256, (int)sizeof(generic_spd_eeprom_t) - 256);\n+\n+\tret = i2c_get_chip_for_busnum(0, SPD_SPA0_ADDRESS, 1, &dev);\n+\tif (!ret)\n+\t\tdm_i2c_write(dev, 0, &dummy, 1);\n+\tret = i2c_get_chip_for_busnum(0, i2c_address, 1, &dev);\n+\tif (!ret) {\n+\t\tif (!dm_i2c_read(dev, 0, (uchar *)spd, 256)) {\n+\t\t\tif (!i2c_get_chip_for_busnum(0, SPD_SPA1_ADDRESS,\n+\t\t\t\t\t\t 1, &dev))\n+\t\t\t\tdm_i2c_write(dev, 0, &dummy, 1);\n+\t\t\tif (!i2c_get_chip_for_busnum(0, i2c_address, 1, &dev))\n+\t\t\t\tret = dm_i2c_read(dev, 0,\n+\t\t\t\t\t\t (uchar *)((ulong)spd + 256),\n+\t\t\t\t\t\t read_len);\n+\t\t}\n+\t}\n+#endif\n+\n+#else\n+\n+#ifndef CONFIG_DM_I2C\n \tret = i2c_read(i2c_address, 0, 1, (uchar *)spd,\n-\t\t\t\tsizeof(generic_spd_eeprom_t));\n+\t\t\tsizeof(generic_spd_eeprom_t));\n+#else\n+\tret = i2c_get_chip_for_busnum(0, i2c_address, 1, &dev);\n+\tif (!ret)\n+\t\tret = dm_i2c_read(dev, 0, (uchar *)spd,\n+\t\t\t\t sizeof(generic_spd_eeprom_t));\n+#endif\n+\n #endif\n \n \tif (ret) {\n", "prefixes": [ "U-Boot", "v4", "1/7" ] }