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GET /api/patches/1126829/?format=api
{ "id": 1126829, "url": "http://patchwork.ozlabs.org/api/patches/1126829/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190703104426.3515-1-piotrx.skajewski@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190703104426.3515-1-piotrx.skajewski@intel.com>", "list_archive_url": null, "date": "2019-07-03T10:44:26", "name": "ixgbe: added support for NVM update via ixgbe driver", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "a2e5e86563fb95139bac906058b73674ce2cc3f7", "submitter": { "id": 75225, "url": "http://patchwork.ozlabs.org/api/people/75225/?format=api", "name": "Piotr Skajewski", "email": "piotrx.skajewski@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190703104426.3515-1-piotrx.skajewski@intel.com/mbox/", "series": [ { "id": 117538, "url": "http://patchwork.ozlabs.org/api/series/117538/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=117538", "date": "2019-07-03T10:44:26", "name": "ixgbe: added support for NVM update via ixgbe driver", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/117538/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1126829/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1126829/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.138; helo=whitealder.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from whitealder.osuosl.org (smtp1.osuosl.org [140.211.166.138])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 45dyS96tRSz9s00\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 3 Jul 2019 20:45:29 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id EC455846C0;\n\tWed, 3 Jul 2019 10:45:27 +0000 (UTC)", "from whitealder.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id rFQQDfZPBysL; Wed, 3 Jul 2019 10:45:23 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby whitealder.osuosl.org (Postfix) with ESMTP id DC2E185BDF;\n\tWed, 3 Jul 2019 10:45:23 +0000 (UTC)", "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\tby ash.osuosl.org (Postfix) with ESMTP id 73D471BF3CB\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 3 Jul 2019 10:45:22 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 6FAEC82D57\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 3 Jul 2019 10:45:22 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id NTJcdk428MYD for <intel-wired-lan@lists.osuosl.org>;\n\tWed, 3 Jul 2019 10:45:20 +0000 (UTC)", "from mga17.intel.com (mga17.intel.com [192.55.52.151])\n\tby fraxinus.osuosl.org (Postfix) with ESMTPS id B908381EB5\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tWed, 3 Jul 2019 10:45:20 +0000 (UTC)", "from orsmga008.jf.intel.com ([10.7.209.65])\n\tby fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t03 Jul 2019 03:45:20 -0700", "from unknown (HELO s240.localdomain) ([10.237.94.19])\n\tby orsmga008.jf.intel.com with ESMTP; 03 Jul 2019 03:45:17 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.63,446,1557212400\"; d=\"scan'208\";a=\"157930768\"", "From": "Piotr Skajewski <piotrx.skajewski@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Wed, 3 Jul 2019 12:44:26 +0200", "Message-Id": "<20190703104426.3515-1-piotrx.skajewski@intel.com>", "X-Mailer": "git-send-email 2.22.0.rc3", "MIME-Version": "1.0", "Subject": "[Intel-wired-lan] [PATCH] ixgbe: added support for NVM update via\n\tixgbe driver", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Cc": "Piotr Skajewski <piotrx.skajewski@intel.com>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "When Secure Boot is enabled access to the /dev/mem is forbidden\nfor user-space applications and clients are reporting inability\nto use tools in Secure Boot Mode. The way to perform NVM update\nis to use ixgbe driver. Currently 10G Linux Base Driver has API\nwhich allows only EEPROM access. There is a need to extend IOCTL\nAPI to allow NVM and registers access.\n\nSigned-off-by: Piotr Skajewski <piotrx.skajewski@intel.com>\n---\n .../net/ethernet/intel/ixgbe/ixgbe_82599.c | 38 ++++++\n .../net/ethernet/intel/ixgbe/ixgbe_common.c | 17 +++\n .../net/ethernet/intel/ixgbe/ixgbe_common.h | 3 +\n .../net/ethernet/intel/ixgbe/ixgbe_ethtool.c | 74 +++++++++-\n drivers/net/ethernet/intel/ixgbe/ixgbe_main.c | 3 +\n drivers/net/ethernet/intel/ixgbe/ixgbe_type.h | 50 +++++--\n drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c | 41 ++++++\n drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c | 129 ++++++++++++++++++\n 8 files changed, 346 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c\nindex 109f8de5a1c2..fad82d27f958 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c\n@@ -2159,6 +2159,43 @@ static s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,\n \treturn status;\n }\n \n+/**\n+ * ixgbe_validate_register_82599 - Validate requested offset\n+ * @offset: offset to validate\n+ * @eeprom_len: EEPROM length\n+ *\n+ * Validate requested offset for NVM Update API\n+ *\n+ * Returns -ENOTTY if the offset is not available on the list\n+ **/\n+s32 ixgbe_validate_register_82599(u32 offset, u32 eeprom_len)\n+{\n+\tswitch (offset) {\n+\tcase IXGBE_STATUS:\n+\tcase IXGBE_ESDP:\n+\tcase IXGBE_MSCA:\n+\tcase IXGBE_MSRWD:\n+\tcase IXGBE_AUTOC:\n+\tcase IXGBE_EEC_8259X:\n+\tcase IXGBE_EERD:\n+\tcase IXGBE_FLA_8259X:\n+\tcase IXGBE_FLOP:\n+\tcase IXGBE_SWSM_8259X:\n+\tcase IXGBE_FWSM_8259X:\n+\tcase IXGBE_FACTPS_8259X:\n+\tcase IXGBE_GSSR:\n+\tcase IXGBE_BARCTRL:\n+\t\treturn 0;\n+\tdefault:\n+\t\tif ((offset >= IXGBE_MAVTV(0) && offset <= IXGBE_MAVTV(7)) ||\n+\t\t (offset >= IXGBE_RAL(0) && offset <= IXGBE_RAH(15)) ||\n+\t\t (offset >= 0x00020000 && offset <= eeprom_len))\n+\t\t\treturn 0;\n+\t}\n+\n+\treturn -ENOTTY;\n+}\n+\n static const struct ixgbe_mac_operations mac_ops_82599 = {\n \t.init_hw = &ixgbe_init_hw_generic,\n \t.reset_hw = &ixgbe_reset_hw_82599,\n@@ -2243,6 +2280,7 @@ static const struct ixgbe_phy_operations phy_ops_82599 = {\n \t.read_i2c_eeprom\t= &ixgbe_read_i2c_eeprom_generic,\n \t.write_i2c_eeprom\t= &ixgbe_write_i2c_eeprom_generic,\n \t.check_overtemp\t\t= &ixgbe_tn_check_overtemp,\n+\t.validate_register\t= &ixgbe_validate_register_82599,\n };\n \n const struct ixgbe_info ixgbe_82599_info = {\ndiff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c\nindex 0bd1294ba517..a4386c099841 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c\n@@ -837,6 +837,23 @@ s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)\n \treturn 0;\n }\n \n+/**\n+ * ixgbe_init_nvmupd_features - Initialize NVM Update params\n+ * @hw: pointer to hardware structure\n+ **/\n+void ixgbe_init_nvmupd_features(struct ixgbe_hw *hw)\n+{\n+\thw->nvmupd_features.major = IXGBE_NVMUPD_FEATURES_API_VER_MAJOR;\n+\thw->nvmupd_features.minor = IXGBE_NVMUPD_FEATURES_API_VER_MINOR;\n+\thw->nvmupd_features.size = sizeof(hw->nvmupd_features);\n+\tmemset(hw->nvmupd_features.features, 0x0,\n+\t IXGBE_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN *\n+\t sizeof(*hw->nvmupd_features.features));\n+\n+\thw->nvmupd_features.features[0] =\n+\t\tIXGBE_NVMUPD_FEATURE_REGISTER_ACCESS_SUPPORT;\n+}\n+\n /**\n * ixgbe_init_eeprom_params_generic - Initialize EEPROM params\n * @hw: pointer to hardware structure\ndiff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.h\nindex 4b531e8ae38a..227515057ce3 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.h\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.h\n@@ -26,6 +26,7 @@ s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index);\n s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index);\n s32 ixgbe_init_led_link_act_generic(struct ixgbe_hw *hw);\n \n+void ixgbe_init_nvmupd_features(struct ixgbe_hw *hw);\n s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw);\n s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data);\n s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,\n@@ -172,6 +173,8 @@ static inline void ixgbe_write_reg64(struct ixgbe_hw *hw, u32 reg, u64 value)\n \n u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg);\n #define IXGBE_READ_REG(a, reg) ixgbe_read_reg((a), (reg))\n+#define IXGBE_R32(a, reg) ixgbe_read_reg((a), (reg))\n+#define IXGBE_R8(a, reg) readb(READ_ONCE((a)->hw_addr) + (reg))\n \n #define IXGBE_WRITE_REG_ARRAY(a, reg, offset, value) \\\n \t\tixgbe_write_reg((a), (reg) + ((offset) << 2), (value))\ndiff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c\nindex acba067cc15a..c845019fad66 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.c\n@@ -889,7 +889,59 @@ static void ixgbe_get_regs(struct net_device *netdev,\n static int ixgbe_get_eeprom_len(struct net_device *netdev)\n {\n \tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n-\treturn adapter->hw.eeprom.word_size * 2;\n+\treturn pci_resource_len(adapter->pdev, 0);\n+}\n+\n+static u8 ixgbe_nvmupd_get_module(u32 val)\n+{\n+\treturn (u8)(val & IXGBE_NVMUPD_MOD_PNT_MASK);\n+}\n+\n+static int ixgbe_nvmupd_command(struct ixgbe_hw *hw,\n+\t\t\t\tstruct ixgbe_nvm_access *nvm,\n+\t\t\t\tu8 *bytes)\n+{\n+\tstruct ixgbe_adapter *adapter = hw->back;\n+\tstruct net_device *netdev = adapter->netdev;\n+\tu32 eeprom_len = ixgbe_get_eeprom_len(netdev);\n+\tu32 command;\n+\tint ret_val = 0;\n+\tu8 module;\n+\n+\tcommand = nvm->command;\n+\tmodule = ixgbe_nvmupd_get_module(nvm->config);\n+\n+\tswitch (command) {\n+\tcase IXGBE_NVMUPD_CMD_REG_READ:\n+\t\tswitch (module) {\n+\t\tcase IXGBE_NVMUPD_EXEC_FEATURES:\n+\t\t\tif (nvm->data_size == hw->nvmupd_features.size)\n+\t\t\t\tmemcpy(bytes, &hw->nvmupd_features,\n+\t\t\t\t hw->nvmupd_features.size);\n+\t\t\telse\n+\t\t\t\tret_val = -ENOMEM;\n+\t\tbreak;\n+\t\tdefault:\n+\t\t\tif (hw->phy.ops.validate_register(nvm->offset,\n+\t\t\t\t\t\t\t eeprom_len))\n+\t\t\t\treturn -ENOTTY;\n+\n+\t\t\tif (nvm->data_size == 1)\n+\t\t\t\t*((u8 *)bytes) = IXGBE_R8(hw, nvm->offset);\n+\t\t\telse\n+\t\t\t\t*((u32 *)bytes) = IXGBE_R32(hw, nvm->offset);\n+\t\tbreak;\n+\t\t}\n+\tbreak;\n+\tcase IXGBE_NVMUPD_CMD_REG_WRITE:\n+\t\tif (hw->phy.ops.validate_register(nvm->offset, eeprom_len))\n+\t\t\treturn -ENOTTY;\n+\n+\t\tIXGBE_WRITE_REG(hw, nvm->offset, *((u32 *)bytes));\n+\tbreak;\n+\t}\n+\n+\treturn ret_val;\n }\n \n static int ixgbe_get_eeprom(struct net_device *netdev,\n@@ -897,14 +949,24 @@ static int ixgbe_get_eeprom(struct net_device *netdev,\n {\n \tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n \tstruct ixgbe_hw *hw = &adapter->hw;\n+\tstruct ixgbe_nvm_access *nvm;\n \tu16 *eeprom_buff;\n \tint first_word, last_word, eeprom_len;\n \tint ret_val = 0;\n+\tu32 magic;\n \tu16 i;\n \n \tif (eeprom->len == 0)\n \t\treturn -EINVAL;\n \n+\tmagic = hw->vendor_id | (hw->device_id << 16);\n+\tif (eeprom->magic && eeprom->magic != magic) {\n+\t\tnvm = (struct ixgbe_nvm_access *)eeprom;\n+\t\tret_val = ixgbe_nvmupd_command(hw, nvm, bytes);\n+\t\treturn ret_val;\n+\t}\n+\n+\t/* normal ethtool get_eeprom support */\n \teeprom->magic = hw->vendor_id | (hw->device_id << 16);\n \n \tfirst_word = eeprom->offset >> 1;\n@@ -933,7 +995,9 @@ static int ixgbe_set_eeprom(struct net_device *netdev,\n {\n \tstruct ixgbe_adapter *adapter = netdev_priv(netdev);\n \tstruct ixgbe_hw *hw = &adapter->hw;\n+\tstruct ixgbe_nvm_access *nvm;\n \tu16 *eeprom_buff;\n+\tu32 magic;\n \tvoid *ptr;\n \tint max_len, first_word, last_word, ret_val = 0;\n \tu16 i;\n@@ -941,6 +1005,14 @@ static int ixgbe_set_eeprom(struct net_device *netdev,\n \tif (eeprom->len == 0)\n \t\treturn -EINVAL;\n \n+\tmagic = hw->vendor_id | (hw->device_id << 16);\n+\tif (eeprom->magic && eeprom->magic != magic) {\n+\t\tnvm = (struct ixgbe_nvm_access *)eeprom;\n+\t\tret_val = ixgbe_nvmupd_command(hw, nvm, bytes);\n+\t\treturn ret_val;\n+\t}\n+\n+\t/* normal ethtool set_eeprom support */\n \tif (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))\n \t\treturn -EINVAL;\n \ndiff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c\nindex b613e72c8ee4..de7b0aa5666e 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c\n@@ -6400,6 +6400,9 @@ static int ixgbe_sw_init(struct ixgbe_adapter *adapter,\n \t/* set default work limits */\n \tadapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;\n \n+\t/* NVM Update features initialization */\n+\tixgbe_init_nvmupd_features(hw);\n+\n \t/* initialize eeprom parameters */\n \tif (ixgbe_init_eeprom_params_generic(hw)) {\n \t\te_dev_err(\"EEPROM initialization failed\\n\");\ndiff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h\nindex 2be1c4c72435..f42e7879233b 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h\n@@ -136,6 +136,7 @@\n \n #define IXGBE_VPDDIAG0 0x10204\n #define IXGBE_VPDDIAG1 0x10208\n+#define IXGBE_SRAMREL 0x10210\n \n /* I2CCTL Bit Masks */\n #define IXGBE_I2C_CLK_IN_8259X\t\t0x00000001\n@@ -929,13 +930,15 @@ struct ixgbe_nvm_version {\n #define IXGBE_FWSM_FW_VAL_BIT\tBIT(15)\n \n /* ARC Subsystem registers */\n-#define IXGBE_HICR 0x15F00\n-#define IXGBE_FWSTS 0x15F0C\n-#define IXGBE_HSMC0R 0x15F04\n-#define IXGBE_HSMC1R 0x15F08\n-#define IXGBE_SWSR 0x15F10\n-#define IXGBE_HFDR 0x15FE8\n-#define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */\n+#define IXGBE_HICR\t\t0x15F00\n+#define IXGBE_FWSTS\t\t0x15F0C\n+#define IXGBE_HSMC0R\t\t0x15F04\n+#define IXGBE_HSMC1R\t\t0x15F08\n+#define IXGBE_SWSR\t\t0x15F10\n+#define IXGBE_FWRESETCNT\t0x15F40\n+#define IXGBE_HFDR\t\t0x15FE8\n+#define IXGBE_FLEX_MNG\t\t0x15800 /* 0x15800 - 0x15EFC */\n+#define IXGBE_FLEX_MNG_PTR(_i)\t(IXGBE_FLEX_MNG + ((_i) * 4))\n \n #define IXGBE_HICR_EN 0x01 /* Enable bit - RO */\n /* Driver sets this bit when done to put command in RAM */\n@@ -996,7 +999,7 @@ struct ixgbe_nvm_version {\n #define IXGBE_GSCL_8_82599 0x1103C\n #define IXGBE_PHYADR_82599 0x11040\n #define IXGBE_PHYDAT_82599 0x11044\n-#define IXGBE_PHYCTL_82599 0x11048\n+#define IXGBE_PHYCTL 0x11048\n #define IXGBE_PBACLR_82599 0x11068\n \n #define IXGBE_CIAA_8259X\t0x11088\n@@ -3513,6 +3516,7 @@ struct ixgbe_phy_operations {\n \t\t\t\t u8 *value);\n \ts32 (*write_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr,\n \t\t\t\t u8 value);\n+\ts32 (*validate_register)(u32 offset, u32 eeprom_len);\n };\n \n struct ixgbe_link_operations {\n@@ -3539,6 +3543,35 @@ struct ixgbe_eeprom_info {\n \tu16\t\t\t\tctrl_word_3;\n };\n \n+/* NVM Update commands */\n+#define IXGBE_NVMUPD_CMD_REG_READ\t0x0000000B\n+#define IXGBE_NVMUPD_CMD_REG_WRITE\t0x0000000C\n+\n+/* NVM Update features API */\n+#define IXGBE_NVMUPD_FEATURES_API_VER_MAJOR\t\t0\n+#define IXGBE_NVMUPD_FEATURES_API_VER_MINOR\t\t0\n+#define IXGBE_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN\t12\n+#define IXGBE_NVMUPD_EXEC_FEATURES\t\t\t0xe\n+#define IXGBE_NVMUPD_FEATURE_FLAT_NVM_SUPPORT\t\tBIT(0)\n+#define IXGBE_NVMUPD_FEATURE_REGISTER_ACCESS_SUPPORT\tBIT(1)\n+\n+#define IXGBE_NVMUPD_MOD_PNT_MASK\t\t\t0xFF\n+\n+struct ixgbe_nvm_access {\n+\tu32 command;\n+\tu32 config;\n+\tu32 offset;\t/* in bytes */\n+\tu32 data_size;\t/* in bytes */\n+\tu8 data[1];\n+};\n+\n+struct ixgbe_nvm_features {\n+\tu8 major;\n+\tu8 minor;\n+\tu16 size;\n+\tu8 features[IXGBE_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN];\n+};\n+\n #define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED\t0x01\n struct ixgbe_mac_info {\n \tstruct ixgbe_mac_operations ops;\n@@ -3637,6 +3670,7 @@ struct ixgbe_hw {\n \tstruct ixgbe_eeprom_info\teeprom;\n \tstruct ixgbe_bus_info\t\tbus;\n \tstruct ixgbe_mbx_info\t\tmbx;\n+\tstruct ixgbe_nvm_features\tnvmupd_features;\n \tconst u32\t\t\t*mvals;\n \tu16\t\t\t\tdevice_id;\n \tu16\t\t\t\tvendor_id;\ndiff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c\nindex de563cfd294d..9f470fbdd84c 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_x540.c\n@@ -822,6 +822,46 @@ s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)\n \n \treturn 0;\n }\n+\n+/**\n+ * ixgbe_validate_register_x540 - Validate requested offset\n+ * @offset: offset to validate\n+ * @eeprom_len: EEPROM length\n+ *\n+ * Validate requested offset for NVM Update API\n+ *\n+ * Returns -ENOTTY if the offset is not available on the list\n+ **/\n+s32 ixgbe_validate_register_x540(u32 offset, u32 eeprom_len)\n+{\n+\tswitch (offset) {\n+\tcase IXGBE_STATUS:\n+\tcase IXGBE_ESDP:\n+\tcase IXGBE_MSCA:\n+\tcase IXGBE_MSRWD:\n+\tcase IXGBE_EEC_X540:\n+\tcase IXGBE_EERD:\n+\tcase IXGBE_EEWR:\n+\tcase IXGBE_FLA_X540:\n+\tcase IXGBE_FLOP:\n+\tcase IXGBE_SWSM_X540:\n+\tcase IXGBE_FWSM_X540:\n+\tcase IXGBE_FACTPS_X540:\n+\tcase IXGBE_GSSR:\n+\tcase IXGBE_SRAMREL:\n+\tcase IXGBE_BARCTRL:\n+\t\treturn 0;\n+\tdefault:\n+\t\tif ((offset >= IXGBE_MAVTV(0) && offset <= IXGBE_MAVTV(7)) ||\n+\t\t (offset >= IXGBE_RAL(0) && offset <= IXGBE_RAH(15)) ||\n+\t\t (offset >= 0x00020000 &&\n+\t\t offset <= eeprom_len))\n+\t\t\treturn 0;\n+\t}\n+\n+\treturn -ENOTTY;\n+}\n+\n static const struct ixgbe_mac_operations mac_ops_X540 = {\n \t.init_hw = &ixgbe_init_hw_generic,\n \t.reset_hw = &ixgbe_reset_hw_X540,\n@@ -906,6 +946,7 @@ static const struct ixgbe_phy_operations phy_ops_X540 = {\n \t.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,\n \t.check_overtemp = &ixgbe_tn_check_overtemp,\n \t.set_phy_power = &ixgbe_set_copper_phy_power,\n+\t.validate_register\t= &ixgbe_validate_register_x540,\n };\n \n static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = {\ndiff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c\nindex 9c42f741ed5e..99a5d327abcf 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c\n@@ -3793,6 +3793,132 @@ static s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,\n \treturn status;\n }\n \n+/**\n+ * ixgbe_validate_register_x550 - Validate requested offset\n+ * @offset: offset to validate\n+ * @eeprom_len: EEPROM length\n+ *\n+ * Validate requested offset for NVM Update API\n+ *\n+ * Returns -ENOTTY if the offset is not available on the list\n+ **/\n+s32 ixgbe_validate_register_x550(u32 offset, __always_unused u32 eeprom_len)\n+{\n+\tswitch (offset) {\n+\tcase IXGBE_STATUS:\n+\tcase IXGBE_ESDP:\n+\tcase IXGBE_MSCA:\n+\tcase IXGBE_MSRWD:\n+\tcase IXGBE_EEC_X550:\n+\tcase IXGBE_EEWR:\n+\tcase IXGBE_FLA_X550:\n+\tcase IXGBE_FLOP:\n+\tcase IXGBE_SWSM_X550:\n+\tcase IXGBE_FWSM_X550:\n+\tcase IXGBE_FACTPS_X550:\n+\tcase IXGBE_GSSR:\n+\tcase IXGBE_SRAMREL:\n+\tcase IXGBE_PHYCTL:\n+\tcase IXGBE_HICR:\n+\tcase IXGBE_FWSTS:\n+\tcase IXGBE_FWRESETCNT:\n+\t\treturn 0;\n+\tdefault:\n+\t\tif ((offset >= IXGBE_MAVTV(0) && offset <= IXGBE_MAVTV(7)) ||\n+\t\t (offset >= IXGBE_RAL(0) && offset <= IXGBE_RAH(15)) ||\n+\t\t (offset >= IXGBE_FLEX_MNG_PTR(0) &&\n+\t\t offset <= IXGBE_FLEX_MNG_PTR(447)))\n+\t\t\treturn 0;\n+\t}\n+\n+\treturn -ENOTTY;\n+}\n+\n+/**\n+ * ixgbe_validate_register_x550em_x - Validate requested offset\n+ * @offset: offset to validate\n+ * @eeprom_len: EEPROM length\n+ *\n+ * Validate requested offset for NVM Update API\n+ *\n+ * Returns -ENOTTY if the offset is not available on the list\n+ **/\n+s32 ixgbe_validate_register_x550em_x(u32 offset, __always_unused u32 eeprom_len)\n+{\n+\tswitch (offset) {\n+\tcase IXGBE_STATUS:\n+\tcase IXGBE_ESDP:\n+\tcase IXGBE_MSCA:\n+\tcase IXGBE_MSRWD:\n+\tcase IXGBE_EEC_X550EM_x:\n+\tcase IXGBE_FLA_X550EM_x:\n+\tcase IXGBE_FLOP:\n+\tcase IXGBE_SWSM_X550EM_x:\n+\tcase IXGBE_FWSM_X550EM_x:\n+\tcase IXGBE_FACTPS_X550EM_x:\n+\tcase IXGBE_GSSR:\n+\tcase IXGBE_PHYCTL:\n+\tcase IXGBE_NW_MNG_IF_SEL:\n+\tcase IXGBE_HICR:\n+\tcase IXGBE_FWSTS:\n+\tcase IXGBE_FWRESETCNT:\n+\tcase IXGBE_I2CCTL_X550EM_x:\n+\t\treturn 0;\n+\tdefault:\n+\t\tif ((offset >= IXGBE_MAVTV(0) && offset <= IXGBE_MAVTV(7)) ||\n+\t\t (offset >= IXGBE_RAL(0) && offset <= IXGBE_RAH(15)) ||\n+\t\t (offset >= IXGBE_FLEX_MNG_PTR(0) &&\n+\t\t offset <= IXGBE_FLEX_MNG_PTR(447)) ||\n+\t\t (offset >= IXGBE_FUSES0_GROUP(0) &&\n+\t\t offset <= IXGBE_FUSES0_GROUP(7)))\n+\t\t\treturn 0;\n+\t}\n+\n+\treturn -ENOTTY;\n+}\n+\n+/**\n+ * ixgbe_validate_register_x550em_a - Validate requested offset\n+ * @offset: offset to validate\n+ * @eeprom_len: EEPROM length\n+ *\n+ * Validate requested offset for NVM Update API\n+ *\n+ * Returns -ENOTTY if the offset is not available on the list\n+ **/\n+s32 ixgbe_validate_register_x550em_a(u32 offset, __always_unused u32 eeprom_len)\n+{\n+\tswitch (offset) {\n+\tcase IXGBE_STATUS:\n+\tcase IXGBE_ESDP:\n+\tcase IXGBE_MSCA:\n+\tcase IXGBE_MSRWD:\n+\tcase IXGBE_EEC_X550EM_a:\n+\tcase IXGBE_FLA_X550EM_a:\n+\tcase IXGBE_FLOP:\n+\tcase IXGBE_SWSM_X550EM_a:\n+\tcase IXGBE_FWSM_X550EM_a:\n+\tcase IXGBE_SWFW_SYNC_X550EM_a:\n+\tcase IXGBE_FACTPS_X550EM_a:\n+\tcase IXGBE_GSSR:\n+\tcase IXGBE_PHYCTL:\n+\tcase IXGBE_NW_MNG_IF_SEL:\n+\tcase IXGBE_HICR:\n+\tcase IXGBE_FWSTS:\n+\tcase IXGBE_FWRESETCNT:\n+\tcase IXGBE_I2CCTL_X550EM_a:\n+\t\treturn 0;\n+\tdefault:\n+\t\tif ((offset >= IXGBE_MAVTV(0) && offset <= IXGBE_MAVTV(7)) ||\n+\t\t (offset >= IXGBE_RAL(0) && offset <= IXGBE_RAH(15)) ||\n+\t\t (offset >= IXGBE_FLEX_MNG_PTR(0) &&\n+\t\t offset <= IXGBE_FLEX_MNG_PTR(447)))\n+\t\t\treturn 0;\n+\t}\n+\n+\treturn -ENOTTY;\n+}\n+\n #define X550_COMMON_MAC \\\n \t.init_hw\t\t\t= &ixgbe_init_hw_generic, \\\n \t.start_hw\t\t\t= &ixgbe_start_hw_X540, \\\n@@ -3982,6 +4108,7 @@ static const struct ixgbe_phy_operations phy_ops_X550 = {\n \t.identify\t\t= &ixgbe_identify_phy_generic,\n \t.read_reg\t\t= &ixgbe_read_phy_reg_generic,\n \t.write_reg\t\t= &ixgbe_write_phy_reg_generic,\n+\t.validate_register\t= &ixgbe_validate_register_x550,\n };\n \n static const struct ixgbe_phy_operations phy_ops_X550EM_x = {\n@@ -3991,6 +4118,7 @@ static const struct ixgbe_phy_operations phy_ops_X550EM_x = {\n \t.identify\t\t= &ixgbe_identify_phy_x550em,\n \t.read_reg\t\t= &ixgbe_read_phy_reg_generic,\n \t.write_reg\t\t= &ixgbe_write_phy_reg_generic,\n+\t.validate_register\t= &ixgbe_validate_register_x550em_x,\n };\n \n static const struct ixgbe_phy_operations phy_ops_x550em_x_fw = {\n@@ -4013,6 +4141,7 @@ static const struct ixgbe_phy_operations phy_ops_x550em_a = {\n \t.write_reg\t\t= &ixgbe_write_phy_reg_x550a,\n \t.read_reg_mdi\t\t= &ixgbe_read_phy_reg_mdi,\n \t.write_reg_mdi\t\t= &ixgbe_write_phy_reg_mdi,\n+\t.validate_register\t= &ixgbe_validate_register_x550em_a,\n };\n \n static const struct ixgbe_phy_operations phy_ops_x550em_a_fw = {\n", "prefixes": [] }