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GET /api/patches/1124833/?format=api
{ "id": 1124833, "url": "http://patchwork.ozlabs.org/api/patches/1124833/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190629185405.1601-11-shiraz.saleem@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190629185405.1601-11-shiraz.saleem@intel.com>", "list_archive_url": null, "date": "2019-06-29T18:53:58", "name": "[rdma-next,10/17] RDMA/irdma: Add RoCEv2 UD OP support", "commit_ref": null, "pull_url": null, "state": "rejected", "archived": false, "hash": "6d6a8452448ae612a36dff922f642cd59a79b851", "submitter": { "id": 69500, "url": "http://patchwork.ozlabs.org/api/people/69500/?format=api", "name": "Saleem, Shiraz", "email": "shiraz.saleem@intel.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190629185405.1601-11-shiraz.saleem@intel.com/mbox/", "series": [ { "id": 116886, "url": "http://patchwork.ozlabs.org/api/series/116886/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=116886", "date": "2019-06-29T18:53:48", "name": "Add unified Intel Ethernet RDMA driver (irdma)", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/116886/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1124833/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1124833/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.133; helo=hemlock.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=intel.com" ], "Received": [ "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 45bjVH0XtMz9s3Z\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSun, 30 Jun 2019 04:54:30 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id B2E0887E8E;\n\tSat, 29 Jun 2019 18:54:28 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id JJqxa2bA1a+c; Sat, 29 Jun 2019 18:54:26 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 6908487E4D;\n\tSat, 29 Jun 2019 18:54:26 +0000 (UTC)", "from hemlock.osuosl.org (smtp2.osuosl.org [140.211.166.133])\n\tby ash.osuosl.org (Postfix) with ESMTP id 503E01BF3AD\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tSat, 29 Jun 2019 18:54:24 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby hemlock.osuosl.org (Postfix) with ESMTP id 4D8F987E94\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tSat, 29 Jun 2019 18:54:24 +0000 (UTC)", "from hemlock.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id rrFxzK0fGh24 for <intel-wired-lan@lists.osuosl.org>;\n\tSat, 29 Jun 2019 18:54:21 +0000 (UTC)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n\tby hemlock.osuosl.org (Postfix) with ESMTPS id 52EB987E4D\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tSat, 29 Jun 2019 18:54:21 +0000 (UTC)", "from fmsmga004.fm.intel.com ([10.253.24.48])\n\tby fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t29 Jun 2019 11:54:21 -0700", "from ssaleem-mobl.amr.corp.intel.com ([10.254.177.95])\n\tby fmsmga004.fm.intel.com with ESMTP; 29 Jun 2019 11:54:20 -0700" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.63,432,1557212400\"; d=\"scan'208\";a=\"185972881\"", "From": "Shiraz Saleem <shiraz.saleem@intel.com>", "To": "intel-wired-lan@lists.osuosl.org", "Date": "Sat, 29 Jun 2019 13:53:58 -0500", "Message-Id": "<20190629185405.1601-11-shiraz.saleem@intel.com>", "X-Mailer": "git-send-email 2.21.0", "In-Reply-To": "<20190629185405.1601-1-shiraz.saleem@intel.com>", "References": "<20190629185405.1601-1-shiraz.saleem@intel.com>", "MIME-Version": "1.0", "Subject": "[Intel-wired-lan] [PATCH rdma-next 10/17] RDMA/irdma: Add RoCEv2 UD\n\tOP support", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Cc": "Mustafa Ismail <mustafa.ismail@intel.com>,\n\tShiraz Saleem <shiraz.saleem@intel.com>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Mustafa Ismail <mustafa.ismail@intel.com>\n\nAdd the header, data structures and functions\nto populate the WQE descriptors and issue the\nControl QP commands that support RoCEv2 UD operations.\n\nSigned-off-by: Mustafa Ismail <mustafa.ismail@intel.com>\nSigned-off-by: Shiraz Saleem <shiraz.saleem@intel.com>\n---\n drivers/infiniband/hw/irdma/uda.c | 391 ++++++++++++++++++++++++++++++++++++\n drivers/infiniband/hw/irdma/uda.h | 65 ++++++\n drivers/infiniband/hw/irdma/uda_d.h | 383 +++++++++++++++++++++++++++++++++++\n 3 files changed, 839 insertions(+)\n create mode 100644 drivers/infiniband/hw/irdma/uda.c\n create mode 100644 drivers/infiniband/hw/irdma/uda.h\n create mode 100644 drivers/infiniband/hw/irdma/uda_d.h", "diff": "diff --git a/drivers/infiniband/hw/irdma/uda.c b/drivers/infiniband/hw/irdma/uda.c\nnew file mode 100644\nindex 0000000..2bcb3c4\n--- /dev/null\n+++ b/drivers/infiniband/hw/irdma/uda.c\n@@ -0,0 +1,391 @@\n+// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB\n+/* Copyright (c) 2019, Intel Corporation. */\n+\n+#include \"osdep.h\"\n+#include \"status.h\"\n+#include \"hmc.h\"\n+#include \"defs.h\"\n+#include \"type.h\"\n+#include \"protos.h\"\n+#include \"uda.h\"\n+#include \"uda_d.h\"\n+\n+/**\n+ * irdma_sc_ah_init - initialize sc ah struct\n+ * @dev: sc device struct\n+ * @ah: sc ah ptr\n+ */\n+static void irdma_sc_init_ah(struct irdma_sc_dev *dev, struct irdma_sc_ah *ah)\n+{\n+\tah->dev = dev;\n+}\n+\n+/**\n+ * irdma_sc_access_ah() - Create, modify or delete AH\n+ * @cqp: struct for cqp hw\n+ * @info: ah information\n+ * @op: Operation\n+ * @scratch: u64 saved to be used during cqp completion\n+ */\n+static enum irdma_status_code irdma_sc_access_ah(struct irdma_sc_cqp *cqp,\n+\t\t\t\t\t\t struct irdma_ah_info *info,\n+\t\t\t\t\t\t u32 op, u64 scratch)\n+{\n+\t__le64 *wqe;\n+\tu64 qw1, qw2;\n+\n+\twqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);\n+\tif (!wqe)\n+\t\treturn IRDMA_ERR_RING_FULL;\n+\n+\tset_64bit_val(wqe, 0, LS_64_1(info->mac_addr[5], 16) |\n+\t\t\t\t\t LS_64_1(info->mac_addr[4], 24) |\n+\t\t\t\t\t LS_64_1(info->mac_addr[3], 32) |\n+\t\t\t\t\t LS_64_1(info->mac_addr[2], 40) |\n+\t\t\t\t\t LS_64_1(info->mac_addr[1], 48) |\n+\t\t\t\t\t LS_64_1(info->mac_addr[0], 56));\n+\n+\tqw1 = LS_64(info->pd_idx, IRDMA_UDA_CQPSQ_MAV_PDINDEXLO) |\n+\t LS_64(info->tc_tos, IRDMA_UDA_CQPSQ_MAV_TC) |\n+\t LS_64(info->vlan_tag, IRDMA_UDAQPC_VLANTAG);\n+\n+\tqw2 = LS_64(info->dst_arpindex, IRDMA_UDA_CQPSQ_MAV_ARPINDEX) |\n+\t LS_64(info->flow_label, IRDMA_UDA_CQPSQ_MAV_FLOWLABEL) |\n+\t LS_64(info->hop_ttl, IRDMA_UDA_CQPSQ_MAV_HOPLIMIT) |\n+\t LS_64(info->pd_idx >> 16, IRDMA_UDA_CQPSQ_MAV_PDINDEXHI);\n+\n+\tif (!info->ipv4_valid) {\n+\t\tset_64bit_val(wqe, 40,\n+\t\t\t LS_64(info->dest_ip_addr[0], IRDMA_UDA_CQPSQ_MAV_ADDR0) |\n+\t\t\t LS_64(info->dest_ip_addr[1], IRDMA_UDA_CQPSQ_MAV_ADDR1));\n+\t\tset_64bit_val(wqe, 32,\n+\t\t\t LS_64(info->dest_ip_addr[2], IRDMA_UDA_CQPSQ_MAV_ADDR2) |\n+\t\t\t LS_64(info->dest_ip_addr[3], IRDMA_UDA_CQPSQ_MAV_ADDR3));\n+\n+\t\tset_64bit_val(wqe, 56,\n+\t\t\t LS_64(info->src_ip_addr[0], IRDMA_UDA_CQPSQ_MAV_ADDR0) |\n+\t\t\t LS_64(info->src_ip_addr[1], IRDMA_UDA_CQPSQ_MAV_ADDR1));\n+\t\tset_64bit_val(wqe, 48,\n+\t\t\t LS_64(info->src_ip_addr[2], IRDMA_UDA_CQPSQ_MAV_ADDR2) |\n+\t\t\t LS_64(info->src_ip_addr[3], IRDMA_UDA_CQPSQ_MAV_ADDR3));\n+\t} else {\n+\t\tset_64bit_val(wqe, 32,\n+\t\t\t LS_64(info->dest_ip_addr[0], IRDMA_UDA_CQPSQ_MAV_ADDR3));\n+\n+\t\tset_64bit_val(wqe, 48,\n+\t\t\t LS_64(info->src_ip_addr[0], IRDMA_UDA_CQPSQ_MAV_ADDR3));\n+\t}\n+\n+\tset_64bit_val(wqe, 8, qw1);\n+\tset_64bit_val(wqe, 16, qw2);\n+\n+\tdma_wmb(); /* need write block before writing WQE header */\n+\n+\tset_64bit_val(\n+\t\twqe, 24,\n+\t\tLS_64(cqp->polarity, IRDMA_UDA_CQPSQ_MAV_WQEVALID) |\n+\t\tLS_64(op, IRDMA_UDA_CQPSQ_MAV_OPCODE) |\n+\t\tLS_64(info->do_lpbk, IRDMA_UDA_CQPSQ_MAV_DOLOOPBACKK) |\n+\t\tLS_64(info->ipv4_valid, IRDMA_UDA_CQPSQ_MAV_IPV4VALID) |\n+\t\tLS_64(info->ah_idx, IRDMA_UDA_CQPSQ_MAV_AVIDX) |\n+\t\tLS_64(info->insert_vlan_tag,\n+\t\t IRDMA_UDA_CQPSQ_MAV_INSERTVLANTAG));\n+\n+\tirdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, \"MANAGE_AH WQE\", wqe,\n+\t\t\tIRDMA_CQP_WQE_SIZE * 8);\n+\tirdma_sc_cqp_post_sq(cqp);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * irdma_sc_create_ah() - Create AH\n+ * @cqp: struct for cqp hw\n+ * @info: ah information\n+ * @scratch: u64 saved to be used during cqp completion\n+ */\n+static enum irdma_status_code irdma_sc_create_ah(struct irdma_sc_cqp *cqp,\n+\t\t\t\t\t\t struct irdma_ah_info *info,\n+\t\t\t\t\t\t u64 scratch)\n+{\n+\treturn irdma_sc_access_ah(cqp, info, IRDMA_CQP_OP_CREATE_ADDR_HANDLE,\n+\t\t\t\t scratch);\n+}\n+\n+/**\n+ * irdma_sc_modify_ah() - Modify AH\n+ * @cqp: struct for cqp hw\n+ * @info: ah information\n+ * @scratch: u64 saved to be used during cqp completion\n+ */\n+static enum irdma_status_code irdma_sc_modify_ah(struct irdma_sc_cqp *cqp,\n+\t\t\t\t\t\t struct irdma_ah_info *info,\n+\t\t\t\t\t\t u64 scratch)\n+{\n+\treturn irdma_sc_access_ah(cqp, info, IRDMA_CQP_OP_MODIFY_ADDR_HANDLE,\n+\t\t\t\t scratch);\n+}\n+\n+/**\n+ * irdma_sc_destroy_ah() - Delete AH\n+ * @cqp: struct for cqp hw\n+ * @info: ah information\n+ * @scratch: u64 saved to be used during cqp completion\n+ */\n+static enum irdma_status_code irdma_sc_destroy_ah(struct irdma_sc_cqp *cqp,\n+\t\t\t\t\t\t struct irdma_ah_info *info,\n+\t\t\t\t\t\t u64 scratch)\n+{\n+\treturn irdma_sc_access_ah(cqp, info, IRDMA_CQP_OP_DESTROY_ADDR_HANDLE,\n+\t\t\t\t scratch);\n+}\n+\n+/**\n+ * create_mg_ctx() - create a mcg context\n+ * @info: multicast group context info\n+ */\n+static enum irdma_status_code\n+irdma_create_mg_ctx(struct irdma_mcast_grp_info *info)\n+{\n+\tstruct irdma_mcast_grp_ctx_entry_info *entry_info = NULL;\n+\tu8 idx = 0; /* index in the array */\n+\tu8 ctx_idx = 0; /* index in the MG context */\n+\n+\tmemset(info->dma_mem_mc.va, 0, IRDMA_MAX_MGS_PER_CTX * sizeof(u64));\n+\n+\tfor (idx = 0; idx < IRDMA_MAX_MGS_PER_CTX; idx++) {\n+\t\tentry_info = &info->mg_ctx_info[idx];\n+\t\tif (entry_info->valid_entry) {\n+\t\t\tset_64bit_val((__le64 *)info->dma_mem_mc.va,\n+\t\t\t\t ctx_idx * sizeof(u64),\n+\t\t\t\t LS_64(entry_info->dest_port, IRDMA_UDA_MGCTX_DESTPORT) |\n+\t\t\t\t LS_64(entry_info->valid_entry, IRDMA_UDA_MGCTX_VALIDENT) |\n+\t\t\t\t LS_64(entry_info->qp_id, IRDMA_UDA_MGCTX_QPID));\n+\t\t\tctx_idx++;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * irdma_access_mcast_grp() - Access mcast group based on op\n+ * @cqp: Control QP\n+ * @info: multicast group context info\n+ * @op: operation to perform\n+ * @scratch: u64 saved to be used during cqp completion\n+ */\n+static enum irdma_status_code\n+irdma_access_mcast_grp(struct irdma_sc_cqp *cqp,\n+\t\t struct irdma_mcast_grp_info *info, u32 op, u64 scratch)\n+{\n+\t__le64 *wqe;\n+\tenum irdma_status_code ret_code = 0;\n+\n+\tif (info->mg_id >= IRDMA_UDA_MAX_FSI_MGS) {\n+\t\tdev_dbg(rfdev_to_dev(cqp->dev), \"WQE: mg_id out of range\\n\");\n+\t\treturn IRDMA_ERR_PARAM;\n+\t}\n+\n+\twqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch);\n+\tif (!wqe) {\n+\t\tdev_dbg(rfdev_to_dev(cqp->dev), \"WQE: ring full\\n\");\n+\t\treturn IRDMA_ERR_RING_FULL;\n+\t}\n+\n+\tret_code = irdma_create_mg_ctx(info);\n+\tif (ret_code)\n+\t\treturn ret_code;\n+\n+\tset_64bit_val(wqe, 32, info->dma_mem_mc.pa);\n+\tset_64bit_val(wqe, 16,\n+\t\t LS_64(info->vlan_id, IRDMA_UDA_CQPSQ_MG_VLANID) |\n+\t\t LS_64(info->qs_handle, IRDMA_UDA_CQPSQ_QS_HANDLE));\n+\tset_64bit_val(wqe, 0, LS_64_1(info->dest_mac_addr[5], 0) |\n+\t\t\t\t\t LS_64_1(info->dest_mac_addr[4], 8) |\n+\t\t\t\t\t LS_64_1(info->dest_mac_addr[3], 16) |\n+\t\t\t\t\t LS_64_1(info->dest_mac_addr[2], 24) |\n+\t\t\t\t\t LS_64_1(info->dest_mac_addr[1], 32) |\n+\t\t\t\t\t LS_64_1(info->dest_mac_addr[0], 40));\n+\tset_64bit_val(wqe, 8,\n+\t\t LS_64(info->hmc_fcn_id, IRDMA_UDA_CQPSQ_MG_HMC_FCN_ID));\n+\n+\tif (!info->ipv4_valid) {\n+\t\tset_64bit_val(wqe, 56,\n+\t\t\t LS_64(info->dest_ip_addr[0], IRDMA_UDA_CQPSQ_MAV_ADDR0) |\n+\t\t\t LS_64(info->dest_ip_addr[1], IRDMA_UDA_CQPSQ_MAV_ADDR1));\n+\t\tset_64bit_val(wqe, 48,\n+\t\t\t LS_64(info->dest_ip_addr[2], IRDMA_UDA_CQPSQ_MAV_ADDR2) |\n+\t\t\t LS_64(info->dest_ip_addr[3], IRDMA_UDA_CQPSQ_MAV_ADDR3));\n+\t} else {\n+\t\tset_64bit_val(wqe, 48,\n+\t\t\t LS_64(info->dest_ip_addr[0], IRDMA_UDA_CQPSQ_MAV_ADDR3));\n+\t}\n+\n+\tdma_wmb(); /* need write memory block before writing the WQE header. */\n+\n+\tset_64bit_val(wqe, 24,\n+\t\t LS_64(cqp->polarity, IRDMA_UDA_CQPSQ_MG_WQEVALID) |\n+\t\t LS_64(op, IRDMA_UDA_CQPSQ_MG_OPCODE) |\n+\t\t LS_64(info->mg_id, IRDMA_UDA_CQPSQ_MG_MGIDX) |\n+\t\t LS_64(info->vlan_valid, IRDMA_UDA_CQPSQ_MG_VLANVALID) |\n+\t\t LS_64(info->ipv4_valid, IRDMA_UDA_CQPSQ_MG_IPV4VALID));\n+\n+\tirdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, \"MANAGE_MCG WQE\", wqe,\n+\t\t\tIRDMA_CQP_WQE_SIZE * 8);\n+\tirdma_debug_buf(cqp->dev, IRDMA_DEBUG_WQE, \"MCG_HOST CTX WQE\",\n+\t\t\tinfo->dma_mem_mc.va, IRDMA_MAX_MGS_PER_CTX * 8);\n+\tirdma_sc_cqp_post_sq(cqp);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * irdma_sc_create_mcast_grp() - Create mcast group.\n+ * @cqp: Control QP\n+ * @info: multicast group context info\n+ * @scratch: u64 saved to be used during cqp completion\n+ */\n+static enum irdma_status_code\n+irdma_sc_create_mcast_grp(struct irdma_sc_cqp *cqp,\n+\t\t\t struct irdma_mcast_grp_info *info, u64 scratch)\n+{\n+\treturn irdma_access_mcast_grp(cqp, info, IRDMA_CQP_OP_CREATE_MCAST_GRP,\n+\t\t\t\t scratch);\n+}\n+\n+/**\n+ * irdma_sc_modify_mcast_grp() - Modify mcast group\n+ * @cqp: Control QP\n+ * @info: multicast group context info\n+ * @scratch: u64 saved to be used during cqp completion\n+ */\n+static enum irdma_status_code\n+irdma_sc_modify_mcast_grp(struct irdma_sc_cqp *cqp,\n+\t\t\t struct irdma_mcast_grp_info *info, u64 scratch)\n+{\n+\treturn irdma_access_mcast_grp(cqp, info, IRDMA_CQP_OP_MODIFY_MCAST_GRP,\n+\t\t\t\t scratch);\n+}\n+\n+/**\n+ * irdma_sc_destroy_mcast_grp() - Destroys mcast group\n+ * @cqp: Control QP\n+ * @info: multicast group context info\n+ * @scratch: u64 saved to be used during cqp completion\n+ */\n+static enum irdma_status_code\n+irdma_sc_destroy_mcast_grp(struct irdma_sc_cqp *cqp,\n+\t\t\t struct irdma_mcast_grp_info *info, u64 scratch)\n+{\n+\treturn irdma_access_mcast_grp(cqp, info, IRDMA_CQP_OP_DESTROY_MCAST_GRP,\n+\t\t\t\t scratch);\n+}\n+\n+/**\n+ * irdma_compare_mgs - Compares two multicast group structures\n+ * @entry1: Multcast group info\n+ * @entry2: Multcast group info in context\n+ */\n+static bool irdma_compare_mgs(struct irdma_mcast_grp_ctx_entry_info *entry1,\n+\t\t\t struct irdma_mcast_grp_ctx_entry_info *entry2)\n+{\n+\tif (entry1->dest_port == entry2->dest_port &&\n+\t entry1->qp_id == entry2->qp_id)\n+\t\treturn true;\n+\n+\treturn false;\n+}\n+\n+/**\n+ * irdma_sc_add_mcast_grp - Allocates mcast group entry in ctx\n+ * @ctx: Multcast group context\n+ * @mg: Multcast group info\n+ */\n+static enum irdma_status_code\n+irdma_sc_add_mcast_grp(struct irdma_mcast_grp_info *ctx,\n+\t\t struct irdma_mcast_grp_ctx_entry_info *mg)\n+{\n+\tu32 idx;\n+\tbool free_entry_found = false;\n+\tu32 free_entry_idx = 0;\n+\n+\t/* find either an identical or a free entry for a multicast group */\n+\tfor (idx = 0; idx < IRDMA_MAX_MGS_PER_CTX; idx++) {\n+\t\tif (ctx->mg_ctx_info[idx].valid_entry) {\n+\t\t\tif (irdma_compare_mgs(&ctx->mg_ctx_info[idx], mg)) {\n+\t\t\t\tctx->mg_ctx_info[idx].use_cnt++;\n+\t\t\t\treturn 0;\n+\t\t\t}\n+\t\t\tcontinue;\n+\t\t}\n+\t\tif (!free_entry_found) {\n+\t\t\tfree_entry_found = true;\n+\t\t\tfree_entry_idx = idx;\n+\t\t}\n+\t}\n+\n+\tif (free_entry_found) {\n+\t\tctx->mg_ctx_info[free_entry_idx] = *mg;\n+\t\tctx->mg_ctx_info[free_entry_idx].valid_entry = true;\n+\t\tctx->mg_ctx_info[free_entry_idx].use_cnt = 1;\n+\t\tctx->no_of_mgs++;\n+\t\treturn 0;\n+\t}\n+\n+\treturn IRDMA_ERR_NO_MEMORY;\n+}\n+\n+/**\n+ * irdma_sc_del_mcast_grp - Delete mcast group\n+ * @ctx: Multcast group context\n+ * @mg: Multcast group info\n+ *\n+ * Finds and removes a specific mulicast group from context, all\n+ * parameters must match to remove a multicast group.\n+ */\n+static enum irdma_status_code\n+irdma_sc_del_mcast_grp(struct irdma_mcast_grp_info *ctx,\n+\t\t struct irdma_mcast_grp_ctx_entry_info *mg)\n+{\n+\tu32 idx;\n+\n+\t/* find an entry in multicast group context */\n+\tfor (idx = 0; idx < IRDMA_MAX_MGS_PER_CTX; idx++) {\n+\t\tif (!ctx->mg_ctx_info[idx].valid_entry)\n+\t\t\tcontinue;\n+\n+\t\tif (irdma_compare_mgs(mg, &ctx->mg_ctx_info[idx])) {\n+\t\t\tctx->mg_ctx_info[idx].use_cnt--;\n+\n+\t\t\tif (!ctx->mg_ctx_info[idx].use_cnt) {\n+\t\t\t\tctx->mg_ctx_info[idx].valid_entry = false;\n+\t\t\t\tctx->no_of_mgs--;\n+\t\t\t\t/* Remove gap if element was not the last */\n+\t\t\t\tif (idx != ctx->no_of_mgs &&\n+\t\t\t\t ctx->no_of_mgs > 0) {\n+\t\t\t\t\tmemcpy(&ctx->mg_ctx_info[idx],\n+\t\t\t\t\t &ctx->mg_ctx_info[ctx->no_of_mgs - 1],\n+\t\t\t\t\t sizeof(ctx->mg_ctx_info[idx]));\n+\t\t\t\t\tctx->mg_ctx_info[ctx->no_of_mgs - 1].valid_entry = false;\n+\t\t\t\t}\n+\t\t\t}\n+\n+\t\t\treturn 0;\n+\t\t}\n+\t}\n+\n+\treturn IRDMA_ERR_PARAM;\n+}\n+\n+struct irdma_uda_ops irdma_uda_ops = {\n+\t.create_ah = irdma_sc_create_ah,\n+\t.destroy_ah = irdma_sc_destroy_ah,\n+\t.init_ah = irdma_sc_init_ah,\n+\t.mcast_grp_add = irdma_sc_add_mcast_grp,\n+\t.mcast_grp_create = irdma_sc_create_mcast_grp,\n+\t.mcast_grp_del = irdma_sc_del_mcast_grp,\n+\t.mcast_grp_destroy = irdma_sc_destroy_mcast_grp,\n+\t.mcast_grp_modify = irdma_sc_modify_mcast_grp,\n+\t.modify_ah = irdma_sc_modify_ah,\n+};\ndiff --git a/drivers/infiniband/hw/irdma/uda.h b/drivers/infiniband/hw/irdma/uda.h\nnew file mode 100644\nindex 0000000..f51e613\n--- /dev/null\n+++ b/drivers/infiniband/hw/irdma/uda.h\n@@ -0,0 +1,65 @@\n+/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */\n+/* Copyright (c) 2019, Intel Corporation. */\n+\n+#ifndef IRDMA_UDA_H\n+#define IRDMA_UDA_H\n+\n+extern struct irdma_uda_ops irdma_uda_ops;\n+\n+#define IRDMA_UDA_MAX_FSI_MGS\t4096\n+#define IRDMA_UDA_MAX_PFS\t16\n+#define IRDMA_UDA_MAX_VFS\t128\n+\n+struct irdma_sc_cqp;\n+\n+struct irdma_ah_info {\n+\tstruct irdma_sc_ah *ah;\n+\tstruct irdma_sc_vsi *vsi;\n+\tu32 pd_idx;\n+\tu32 dst_arpindex;\n+\tu32 dest_ip_addr[4];\n+\tu32 src_ip_addr[4];\n+\tu32 flow_label;\n+\tu32 ah_idx;\n+\tbool ipv4_valid;\n+\tbool do_lpbk;\n+\tu16 vlan_tag;\n+\tu8 insert_vlan_tag;\n+\tu8 tc_tos;\n+\tu8 hop_ttl;\n+\tu8 mac_addr[ETH_ALEN];\n+\tbool ah_valid;\n+};\n+\n+struct irdma_sc_ah {\n+\tstruct irdma_sc_dev *dev;\n+\tstruct irdma_ah_info ah_info;\n+};\n+\n+struct irdma_uda_ops {\n+\tvoid (*init_ah)(struct irdma_sc_dev *dev, struct irdma_sc_ah *ah);\n+\tenum irdma_status_code (*create_ah)(struct irdma_sc_cqp *cqp,\n+\t\t\t\t\t struct irdma_ah_info *info,\n+\t\t\t\t\t u64 scratch);\n+\tenum irdma_status_code (*modify_ah)(struct irdma_sc_cqp *cqp,\n+\t\t\t\t\t struct irdma_ah_info *info,\n+\t\t\t\t\t u64 scratch);\n+\tenum irdma_status_code (*destroy_ah)(struct irdma_sc_cqp *cqp,\n+\t\t\t\t\t struct irdma_ah_info *info,\n+\t\t\t\t\t u64 scratch);\n+\t/* multicast */\n+\tenum irdma_status_code (*mcast_grp_create)(struct irdma_sc_cqp *cqp,\n+\t\t\t\t\t\t struct irdma_mcast_grp_info *info,\n+\t\t\t\t\t\t u64 scratch);\n+\tenum irdma_status_code (*mcast_grp_modify)(struct irdma_sc_cqp *cqp,\n+\t\t\t\t\t\t struct irdma_mcast_grp_info *info,\n+\t\t\t\t\t\t u64 scratch);\n+\tenum irdma_status_code (*mcast_grp_destroy)(struct irdma_sc_cqp *cqp,\n+\t\t\t\t\t\t struct irdma_mcast_grp_info *info,\n+\t\t\t\t\t\t u64 scratch);\n+\tenum irdma_status_code (*mcast_grp_add)(struct irdma_mcast_grp_info *ctx,\n+\t\t\t\t\t\tstruct irdma_mcast_grp_ctx_entry_info *mg);\n+\tenum irdma_status_code (*mcast_grp_del)(struct irdma_mcast_grp_info *ctx,\n+\t\t\t\t\t\tstruct irdma_mcast_grp_ctx_entry_info *mg);\n+};\n+#endif /* IRDMA_UDA_H */\ndiff --git a/drivers/infiniband/hw/irdma/uda_d.h b/drivers/infiniband/hw/irdma/uda_d.h\nnew file mode 100644\nindex 0000000..6d94270\n--- /dev/null\n+++ b/drivers/infiniband/hw/irdma/uda_d.h\n@@ -0,0 +1,383 @@\n+/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */\n+/* Copyright (c) 2019, Intel Corporation. */\n+\n+#ifndef IRDMA_UDA_D_H\n+#define IRDMA_UDA_D_H\n+\n+/* L4 packet type */\n+#define IRDMA_E_UDA_SQ_L4T_UNKNOWN\t0\n+#define IRDMA_E_UDA_SQ_L4T_TCP\t\t1\n+#define IRDMA_E_UDA_SQ_L4T_SCTP\t\t2\n+#define IRDMA_E_UDA_SQ_L4T_UDP\t\t3\n+\n+/* Inner IP header type */\n+#define IRDMA_E_UDA_SQ_IIPT_UNKNOWN\t\t0\n+#define IRDMA_E_UDA_SQ_IIPT_IPV6\t\t1\n+#define IRDMA_E_UDA_SQ_IIPT_IPV4_NO_CSUM\t2\n+#define IRDMA_E_UDA_SQ_IIPT_IPV4_CSUM\t\t3\n+\n+/* UDA defined fields for transmit descriptors */\n+#define IRDMA_UDA_QPSQ_PUSHWQE_S 56\n+#define IRDMA_UDA_QPSQ_PUSHWQE_M BIT_ULL(IRDMA_UDA_QPSQ_PUSHWQE_S)\n+\n+#define IRDMA_UDA_QPSQ_INLINEDATAFLAG_S 57\n+#define IRDMA_UDA_QPSQ_INLINEDATAFLAG_M \\\n+\tBIT_ULL(IRDMA_UDA_QPSQ_INLINEDATAFLAG_S)\n+\n+#define IRDMA_UDA_QPSQ_INLINEDATALEN_S 48\n+#define IRDMA_UDA_QPSQ_INLINEDATALEN_M \\\n+\t((u64)0xff << IRDMA_UDA_QPSQ_INLINEDATALEN_S)\n+\n+#define IRDMA_UDA_QPSQ_ADDFRAGCNT_S 38\n+#define IRDMA_UDA_QPSQ_ADDFRAGCNT_M \\\n+\t((u64)0x0F << IRDMA_UDA_QPSQ_ADDFRAGCNT_S)\n+\n+#define IRDMA_UDA_QPSQ_IPFRAGFLAGS_S 42\n+#define IRDMA_UDA_QPSQ_IPFRAGFLAGS_M \\\n+\t((u64)0x3 << IRDMA_UDA_QPSQ_IPFRAGFLAGS_S)\n+\n+#define IRDMA_UDA_QPSQ_NOCHECKSUM_S 45\n+#define IRDMA_UDA_QPSQ_NOCHECKSUM_M \\\n+\tBIT_ULL(IRDMA_UDA_QPSQ_NOCHECKSUM_S)\n+\n+#define IRDMA_UDA_QPSQ_AHIDXVALID_S 46\n+#define IRDMA_UDA_QPSQ_AHIDXVALID_M \\\n+\tBIT_ULL(IRDMA_UDA_QPSQ_AHIDXVALID_S)\n+\n+#define IRDMA_UDA_QPSQ_LOCAL_FENCE_S 61\n+#define IRDMA_UDA_QPSQ_LOCAL_FENCE_M \\\n+\tBIT_ULL(IRDMA_UDA_QPSQ_LOCAL_FENCE_S)\n+\n+#define IRDMA_UDA_QPSQ_AHIDX_S 0\n+#define IRDMA_UDA_QPSQ_AHIDX_M ((u64)0x1ffff << IRDMA_UDA_QPSQ_AHIDX_S)\n+\n+#define IRDMA_UDA_QPSQ_PROTOCOL_S 16\n+#define IRDMA_UDA_QPSQ_PROTOCOL_M \\\n+\t((u64)0xff << IRDMA_UDA_QPSQ_PROTOCOL_S)\n+\n+#define IRDMA_UDA_QPSQ_EXTHDRLEN_S 32\n+#define IRDMA_UDA_QPSQ_EXTHDRLEN_M \\\n+\t((u64)0x1ff << IRDMA_UDA_QPSQ_EXTHDRLEN_S)\n+\n+#define IRDMA_UDA_QPSQ_MULTICAST_S 63\n+#define IRDMA_UDA_QPSQ_MULTICAST_M \\\n+\tBIT_ULL(IRDMA_UDA_QPSQ_MULTICAST_S)\n+\n+#define IRDMA_UDA_QPSQ_MACLEN_S 56\n+#define IRDMA_UDA_QPSQ_MACLEN_M \\\n+\t((u64)0x7f << IRDMA_UDA_QPSQ_MACLEN_S)\n+#define IRDMA_UDA_QPSQ_MACLEN_LINE 2\n+\n+#define IRDMA_UDA_QPSQ_IPLEN_S 48\n+#define IRDMA_UDA_QPSQ_IPLEN_M \\\n+\t((u64)0x7f << IRDMA_UDA_QPSQ_IPLEN_S)\n+#define IRDMA_UDA_QPSQ_IPLEN_LINE 2\n+\n+#define IRDMA_UDA_QPSQ_L4T_S 30\n+#define IRDMA_UDA_QPSQ_L4T_M ((u64)0x3 << IRDMA_UDA_QPSQ_L4T_S)\n+#define IRDMA_UDA_QPSQ_L4T_LINE 2\n+\n+#define IRDMA_UDA_QPSQ_IIPT_S 28\n+#define IRDMA_UDA_QPSQ_IIPT_M ((u64)0x3 << IRDMA_UDA_QPSQ_IIPT_S)\n+#define IRDMA_UDA_QPSQ_IIPT_LINE 2\n+\n+#define IRDMA_UDA_QPSQ_DO_LPB_LINE 3\n+\n+#define IRDMA_UDA_QPSQ_FWD_PROG_CONFIRM_S 45\n+#define IRDMA_UDA_QPSQ_FWD_PROG_CONFIRM_M \\\n+\tBIT_ULL(IRDMA_UDA_QPSQ_FWD_PROG_CONFIRM_S)\n+#define IRDMA_UDA_QPSQ_FWD_PROG_CONFIRM_LINE 3\n+\n+#define IRDMA_UDA_QPSQ_IMMDATA_S 0\n+#define IRDMA_UDA_QPSQ_IMMDATA_M \\\n+\t((u64)0xffffffffffffffff << IRDMA_UDA_QPSQ_IMMDATA_S)\n+\n+/* Byte Offset 0 */\n+#define IRDMA_UDAQPC_IPV4_S 3\n+#define IRDMA_UDAQPC_IPV4_M BIT_ULL(IRDMAQPC_IPV4_S)\n+\n+#define IRDMA_UDAQPC_INSERTVLANTAG_S 5\n+#define IRDMA_UDAQPC_INSERTVLANTAG_M BIT_ULL(IRDMA_UDAQPC_INSERTVLANTAG_S)\n+\n+#define IRDMA_UDAQPC_ISQP1_S 6\n+#define IRDMA_UDAQPC_ISQP1_M BIT_ULL(IRDMA_UDAQPC_ISQP1_S)\n+\n+#define IRDMA_UDAQPC_RQWQESIZE_S IRDMAQPC_RQWQESIZE_S\n+#define IRDMA_UDAQPC_RQWQESIZE_M IRDMAQPC_RQWQESIZE_M\n+\n+#define IRDMA_UDAQPC_ECNENABLE_S 14\n+#define IRDMA_UDAQPC_ECNENABLE_M BIT_ULL(IRDMA_UDAQPC_ECNENABLE_S)\n+\n+#define IRDMA_UDAQPC_PDINDEXHI_S 20\n+#define IRDMA_UDAQPC_PDINDEXHI_M ((u64)3 << IRDMA_UDAQPC_PDINDEXHI_S)\n+\n+#define IRDMA_UDAQPC_DCTCPENABLE_S 25\n+#define IRDMA_UDAQPC_DCTCPENABLE_M BIT_ULL(IRDMA_UDAQPC_DCTCPENABLE_S)\n+\n+#define IRDMA_UDAQPC_RCVTPHEN_S IRDMAQPC_RCVTPHEN_S\n+#define IRDMA_UDAQPC_RCVTPHEN_M IRDMAQPC_RCVTPHEN_M\n+\n+#define IRDMA_UDAQPC_XMITTPHEN_S IRDMAQPC_XMITTPHEN_S\n+#define IRDMA_UDAQPC_XMITTPHEN_M IRDMAQPC_XMITTPHEN_M\n+\n+#define IRDMA_UDAQPC_RQTPHEN_S IRDMAQPC_RQTPHEN_S\n+#define IRDMA_UDAQPC_RQTPHEN_M IRDMAQPC_RQTPHEN_M\n+\n+#define IRDMA_UDAQPC_SQTPHEN_S IRDMAQPC_SQTPHEN_S\n+#define IRDMA_UDAQPC_SQTPHEN_M IRDMAQPC_SQTPHEN_M\n+\n+#define IRDMA_UDAQPC_PPIDX_S IRDMAQPC_PPIDX_S\n+#define IRDMA_UDAQPC_PPIDX_M IRDMAQPC_PPIDX_M\n+\n+#define IRDMA_UDAQPC_PMENA_S IRDMAQPC_PMENA_S\n+#define IRDMA_UDAQPC_PMENA_M IRDMAQPC_PMENA_M\n+\n+#define IRDMA_UDAQPC_INSERTTAG2_S 11\n+#define IRDMA_UDAQPC_INSERTTAG2_M BIT_ULL(IRDMA_UDAQPC_INSERTTAG2_S)\n+\n+#define IRDMA_UDAQPC_INSERTTAG3_S 14\n+#define IRDMA_UDAQPC_INSERTTAG3_M BIT_ULL(IRDMA_UDAQPC_INSERTTAG3_S)\n+\n+#define IRDMA_UDAQPC_RQSIZE_S IRDMAQPC_RQSIZE_S\n+#define IRDMA_UDAQPC_RQSIZE_M IRDMAQPC_RQSIZE_M\n+\n+#define IRDMA_UDAQPC_SQSIZE_S IRDMAQPC_SQSIZE_S\n+#define IRDMA_UDAQPC_SQSIZE_M IRDMAQPC_SQSIZE_M\n+\n+#define IRDMA_UDAQPC_TXCQNUM_S IRDMAQPC_TXCQNUM_S\n+#define IRDMA_UDAQPC_TXCQNUM_M IRDMAQPC_TXCQNUM_M\n+\n+#define IRDMA_UDAQPC_RXCQNUM_S IRDMAQPC_RXCQNUM_S\n+#define IRDMA_UDAQPC_RXCQNUM_M IRDMAQPC_RXCQNUM_M\n+\n+#define IRDMA_UDAQPC_QPCOMPCTX_S IRDMAQPC_QPCOMPCTX_S\n+#define IRDMA_UDAQPC_QPCOMPCTX_M IRDMAQPC_QPCOMPCTX_M\n+\n+#define IRDMA_UDAQPC_SQTPHVAL_S IRDMAQPC_SQTPHVAL_S\n+#define IRDMA_UDAQPC_SQTPHVAL_M IRDMAQPC_SQTPHVAL_M\n+\n+#define IRDMA_UDAQPC_RQTPHVAL_S IRDMAQPC_RQTPHVAL_S\n+#define IRDMA_UDAQPC_RQTPHVAL_M IRDMAQPC_RQTPHVAL_M\n+\n+#define IRDMA_UDAQPC_QSHANDLE_S IRDMAQPC_QSHANDLE_S\n+#define IRDMA_UDAQPC_QSHANDLE_M IRDMAQPC_QSHANDLE_M\n+\n+#define IRDMA_UDAQPC_RQHDRRINGBUFSIZE_S 48\n+#define IRDMA_UDAQPC_RQHDRRINGBUFSIZE_M \\\n+\t((u64)0x3 << IRDMA_UDAQPC_RQHDRRINGBUFSIZE_S)\n+\n+#define IRDMA_UDAQPC_SQHDRRINGBUFSIZE_S 32\n+#define IRDMA_UDAQPC_SQHDRRINGBUFSIZE_M \\\n+\t((u64)0x3 << IRDMA_UDAQPC_SQHDRRINGBUFSIZE_S)\n+\n+#define IRDMA_UDAQPC_PRIVILEGEENABLE_S 25\n+#define IRDMA_UDAQPC_PRIVILEGEENABLE_M \\\n+\tBIT_ULL(IRDMA_UDAQPC_PRIVILEGEENABLE_S)\n+\n+#define IRDMA_UDAQPC_USE_STATISTICS_INSTANCE_S 26\n+#define IRDMA_UDAQPC_USE_STATISTICS_INSTANCE_M \\\n+\tBIT_ULL(IRDMA_UDAQPC_USE_STATISTICS_INSTANCE_S)\n+\n+#define IRDMA_UDAQPC_STATISTICS_INSTANCE_INDEX_S 0\n+#define IRDMA_UDAQPC_STATISTICS_INSTANCE_INDEX_M \\\n+\t((u64)0x7F << IRDMA_UDAQPC_STATISTICS_INSTANCE_INDEX_S)\n+\n+#define IRDMA_UDAQPC_PRIVHDRGENENABLE_S 0\n+#define IRDMA_UDAQPC_PRIVHDRGENENABLE_M \\\n+\tBIT_ULL(IRDMA_UDAQPC_PRIVHDRGENENABLE_S)\n+\n+#define IRDMA_UDAQPC_RQHDRSPLITENABLE_S 3\n+#define IRDMA_UDAQPC_RQHDRSPLITENABLE_M \\\n+\tBIT_ULL(IRDMA_UDAQPC_RQHDRSPLITENABLE_S)\n+\n+#define IRDMA_UDAQPC_RQHDRRINGBUFENABLE_S 2\n+#define IRDMA_UDAQPC_RQHDRRINGBUFENABLE_M \\\n+\tBIT_ULL(IRDMA_UDAQPC_RQHDRRINGBUFENABLE_S)\n+\n+#define IRDMA_UDAQPC_SQHDRRINGBUFENABLE_S 1\n+#define IRDMA_UDAQPC_SQHDRRINGBUFENABLE_M \\\n+\tBIT_ULL(IRDMA_UDAQPC_SQHDRRINGBUFENABLE_S)\n+\n+#define IRDMA_UDAQPC_IPID_S 32\n+#define IRDMA_UDAQPC_IPID_M ((u64)0xffff << IRDMA_UDAQPC_IPID_S)\n+\n+#define IRDMA_UDAQPC_SNDMSS_S 16\n+#define IRDMA_UDAQPC_SNDMSS_M ((u64)0x3fff << IRDMA_UDAQPC_SNDMSS_S)\n+\n+#define IRDMA_UDAQPC_VLANTAG_S 0\n+#define IRDMA_UDAQPC_VLANTAG_M ((u64)0xffff << IRDMA_UDAQPC_VLANTAG_S)\n+\n+/* Address Handle */\n+#define IRDMA_UDA_CQPSQ_MAV_PDINDEXHI_S 20\n+#define IRDMA_UDA_CQPSQ_MAV_PDINDEXHI_M \\\n+\t((u64)0x3 << IRDMA_UDA_CQPSQ_MAV_PDINDEXHI_S)\n+\n+#define IRDMA_UDA_CQPSQ_MAV_PDINDEXLO_S 48\n+#define IRDMA_UDA_CQPSQ_MAV_PDINDEXLO_M \\\n+\t((u64)0xffff << IRDMA_UDA_CQPSQ_MAV_PDINDEXLO_S)\n+\n+#define IRDMA_UDA_CQPSQ_MAV_SRCMACADDRINDEX_S 24\n+#define IRDMA_UDA_CQPSQ_MAV_SRCMACADDRINDEX_M \\\n+\t((u64)0x3f << IRDMA_UDA_CQPSQ_MAV_SRCMACADDRINDEX_S)\n+\n+#define IRDMA_UDA_CQPSQ_MAV_ARPINDEX_S 48\n+#define IRDMA_UDA_CQPSQ_MAV_ARPINDEX_M \\\n+\t((u64)0xffff << IRDMA_UDA_CQPSQ_MAV_ARPINDEX_S)\n+\n+#define IRDMA_UDA_CQPSQ_MAV_TC_S 32\n+#define IRDMA_UDA_CQPSQ_MAV_TC_M ((u64)0xff << IRDMA_UDA_CQPSQ_MAV_TC_S)\n+\n+#define IRDMA_UDA_CQPSQ_MAV_HOPLIMIT_S 32\n+#define IRDMA_UDA_CQPSQ_MAV_HOPLIMIT_M \\\n+\t((u64)0xff << IRDMA_UDA_CQPSQ_MAV_HOPLIMIT_S)\n+\n+#define IRDMA_UDA_CQPSQ_MAV_FLOWLABEL_S 0\n+#define IRDMA_UDA_CQPSQ_MAV_FLOWLABEL_M \\\n+\t((u64)0xfffff << IRDMA_UDA_CQPSQ_MAV_FLOWLABEL_S)\n+\n+#define IRDMA_UDA_CQPSQ_MAV_ADDR0_S 32\n+#define IRDMA_UDA_CQPSQ_MAV_ADDR0_M \\\n+\t((u64)0xffffffff << IRDMA_UDA_CQPSQ_MAV_ADDR0_S)\n+\n+#define IRDMA_UDA_CQPSQ_MAV_ADDR1_S 0\n+#define IRDMA_UDA_CQPSQ_MAV_ADDR1_M \\\n+\t((u64)0xffffffff << IRDMA_UDA_CQPSQ_MAV_ADDR1_S)\n+\n+#define IRDMA_UDA_CQPSQ_MAV_ADDR2_S 32\n+#define IRDMA_UDA_CQPSQ_MAV_ADDR2_M \\\n+\t((u64)0xffffffff << IRDMA_UDA_CQPSQ_MAV_ADDR2_S)\n+\n+#define IRDMA_UDA_CQPSQ_MAV_ADDR3_S 0\n+#define IRDMA_UDA_CQPSQ_MAV_ADDR3_M \\\n+\t((u64)0xffffffff << IRDMA_UDA_CQPSQ_MAV_ADDR3_S)\n+\n+#define IRDMA_UDA_CQPSQ_MAV_WQEVALID_S 63\n+#define IRDMA_UDA_CQPSQ_MAV_WQEVALID_M \\\n+\tBIT_ULL(IRDMA_UDA_CQPSQ_MAV_WQEVALID_S)\n+\n+#define IRDMA_UDA_CQPSQ_MAV_OPCODE_S 32\n+#define IRDMA_UDA_CQPSQ_MAV_OPCODE_M \\\n+\t((u64)0x3f << IRDMA_UDA_CQPSQ_MAV_OPCODE_S)\n+\n+#define IRDMA_UDA_CQPSQ_MAV_DOLOOPBACKK_S 62\n+#define IRDMA_UDA_CQPSQ_MAV_DOLOOPBACKK_M \\\n+\tBIT_ULL(IRDMA_UDA_CQPSQ_MAV_DOLOOPBACKK_S)\n+\n+#define IRDMA_UDA_CQPSQ_MAV_IPV4VALID_S 59\n+#define IRDMA_UDA_CQPSQ_MAV_IPV4VALID_M \\\n+\tBIT_ULL(IRDMA_UDA_CQPSQ_MAV_IPV4VALID_S)\n+\n+#define IRDMA_UDA_CQPSQ_MAV_AVIDX_S 0\n+#define IRDMA_UDA_CQPSQ_MAV_AVIDX_M \\\n+\t((u64)0x1ffff << IRDMA_UDA_CQPSQ_MAV_AVIDX_S)\n+\n+#define IRDMA_UDA_CQPSQ_MAV_INSERTVLANTAG_S 60\n+#define IRDMA_UDA_CQPSQ_MAV_INSERTVLANTAG_M BIT_ULL(IRDMA_UDA_CQPSQ_MAV_INSERTVLANTAG_S)\n+\n+/* UDA multicast group */\n+\n+#define IRDMA_UDA_MGCTX_VFFLAG_S 29\n+#define IRDMA_UDA_MGCTX_VFFLAG_M BIT_ULL(IRDMA_UDA_MGCTX_VFFLAG_S)\n+\n+#define IRDMA_UDA_MGCTX_DESTPORT_S 32\n+#define IRDMA_UDA_MGCTX_DESTPORT_M ((u64)0xffff << IRDMA_UDA_MGCTX_DESTPORT_S)\n+\n+#define IRDMA_UDA_MGCTX_VFID_S 22\n+#define IRDMA_UDA_MGCTX_VFID_M ((u64)0x7f << IRDMA_UDA_MGCTX_VFID_S)\n+\n+#define IRDMA_UDA_MGCTX_VALIDENT_S 31\n+#define IRDMA_UDA_MGCTX_VALIDENT_M BIT_ULL(IRDMA_UDA_MGCTX_VALIDENT_S)\n+\n+#define IRDMA_UDA_MGCTX_PFID_S 18\n+#define IRDMA_UDA_MGCTX_PFID_M ((u64)0xf << IRDMA_UDA_MGCTX_PFID_S)\n+\n+#define IRDMA_UDA_MGCTX_FLAGIGNOREDPORT_S 30\n+#define IRDMA_UDA_MGCTX_FLAGIGNOREDPORT_M \\\n+\tBIT_ULL(IRDMA_UDA_MGCTX_FLAGIGNOREDPORT_S)\n+\n+#define IRDMA_UDA_MGCTX_QPID_S 0\n+#define IRDMA_UDA_MGCTX_QPID_M ((u64)0x3ffff << IRDMA_UDA_MGCTX_QPID_S)\n+\n+/* multicast group create CQP command */\n+\n+#define IRDMA_UDA_CQPSQ_MG_WQEVALID_S 63\n+#define IRDMA_UDA_CQPSQ_MG_WQEVALID_M \\\n+\tBIT_ULL(IRDMA_UDA_CQPSQ_MG_WQEVALID_S)\n+\n+#define IRDMA_UDA_CQPSQ_MG_OPCODE_S 32\n+#define IRDMA_UDA_CQPSQ_MG_OPCODE_M ((u64)0x3f << IRDMA_UDA_CQPSQ_MG_OPCODE_S)\n+\n+#define IRDMA_UDA_CQPSQ_MG_MGIDX_S 0\n+#define IRDMA_UDA_CQPSQ_MG_MGIDX_M ((u64)0x1fff << IRDMA_UDA_CQPSQ_MG_MGIDX_S)\n+\n+#define IRDMA_UDA_CQPSQ_MG_IPV4VALID_S 60\n+#define IRDMA_UDA_CQPSQ_MG_IPV4VALID_M BIT_ULL(IRDMA_UDA_CQPSQ_MG_IPV4VALID_S)\n+\n+#define IRDMA_UDA_CQPSQ_MG_VLANVALID_S 59\n+#define IRDMA_UDA_CQPSQ_MG_VLANVALID_M BIT_ULL(IRDMA_UDA_CQPSQ_MG_VLANVALID_S)\n+\n+#define IRDMA_UDA_CQPSQ_MG_HMC_FCN_ID_S 0\n+#define IRDMA_UDA_CQPSQ_MG_HMC_FCN_ID_M ((u64)0x3F << IRDMA_UDA_CQPSQ_MG_HMC_FCN_ID_S)\n+\n+#define IRDMA_UDA_CQPSQ_MG_VLANID_S 32\n+#define IRDMA_UDA_CQPSQ_MG_VLANID_M ((u64)0xFFF << IRDMA_UDA_CQPSQ_MG_VLANID_S)\n+\n+#define IRDMA_UDA_CQPSQ_QS_HANDLE_S 0\n+#define IRDMA_UDA_CQPSQ_QS_HANDLE_M ((u64)0x3FF << IRDMA_UDA_CQPSQ_QS_HANDLE_S)\n+\n+/* Quad hash table */\n+#define IRDMA_UDA_CQPSQ_QHASH_QPN_S 32\n+#define IRDMA_UDA_CQPSQ_QHASH_QPN_M \\\n+\t((u64)0x3ffff << IRDMA_UDA_CQPSQ_QHASH_QPN_S)\n+\n+#define IRDMA_UDA_CQPSQ_QHASH__S 0\n+#define IRDMA_UDA_CQPSQ_QHASH__M BIT_ULL(IRDMA_UDA_CQPSQ_QHASH__S)\n+\n+#define IRDMA_UDA_CQPSQ_QHASH_SRC_PORT_S 16\n+#define IRDMA_UDA_CQPSQ_QHASH_SRC_PORT_M \\\n+\t((u64)0xffff << IRDMA_UDA_CQPSQ_QHASH_SRC_PORT_S)\n+\n+#define IRDMA_UDA_CQPSQ_QHASH_DEST_PORT_S 0\n+#define IRDMA_UDA_CQPSQ_QHASH_DEST_PORT_M \\\n+\t((u64)0xffff << IRDMA_UDA_CQPSQ_QHASH_DEST_PORT_S)\n+\n+#define IRDMA_UDA_CQPSQ_QHASH_ADDR0_S 32\n+#define IRDMA_UDA_CQPSQ_QHASH_ADDR0_M \\\n+\t((u64)0xffffffff << IRDMA_UDA_CQPSQ_QHASH_ADDR0_S)\n+\n+#define IRDMA_UDA_CQPSQ_QHASH_ADDR1_S 0\n+#define IRDMA_UDA_CQPSQ_QHASH_ADDR1_M \\\n+\t((u64)0xffffffff << IRDMA_UDA_CQPSQ_QHASH_ADDR1_S)\n+\n+#define IRDMA_UDA_CQPSQ_QHASH_ADDR2_S 32\n+#define IRDMA_UDA_CQPSQ_QHASH_ADDR2_M \\\n+\t((u64)0xffffffff << IRDMA_UDA_CQPSQ_QHASH_ADDR2_S)\n+\n+#define IRDMA_UDA_CQPSQ_QHASH_ADDR3_S 0\n+#define IRDMA_UDA_CQPSQ_QHASH_ADDR3_M \\\n+\t((u64)0xffffffff << IRDMA_UDA_CQPSQ_QHASH_ADDR3_S)\n+\n+#define IRDMA_UDA_CQPSQ_QHASH_WQEVALID_S 63\n+#define IRDMA_UDA_CQPSQ_QHASH_WQEVALID_M \\\n+\tBIT_ULL(IRDMA_UDA_CQPSQ_QHASH_WQEVALID_S)\n+\n+#define IRDMA_UDA_CQPSQ_QHASH_OPCODE_S 32\n+#define IRDMA_UDA_CQPSQ_QHASH_OPCODE_M \\\n+\t((u64)0x3f << IRDMA_UDA_CQPSQ_QHASH_OPCODE_S)\n+\n+#define IRDMA_UDA_CQPSQ_QHASH_MANAGE_S 61\n+#define IRDMA_UDA_CQPSQ_QHASH_MANAGE_M \\\n+\t((u64)0x3 << IRDMA_UDA_CQPSQ_QHASH_MANAGE_S)\n+\n+#define IRDMA_UDA_CQPSQ_QHASH_IPV4VALID_S 60\n+#define IRDMA_UDA_CQPSQ_QHASH_IPV4VALID_M \\\n+\t((u64)0x1 << IRDMA_UDA_CQPSQ_QHASH_IPV4VALID_S)\n+\n+#define IRDMA_UDA_CQPSQ_QHASH_LANFWD_S 59\n+#define IRDMA_UDA_CQPSQ_QHASH_LANFWD_M \\\n+\t((u64)0x1 << IRDMA_UDA_CQPSQ_QHASH_LANFWD_S)\n+\n+#define IRDMA_UDA_CQPSQ_QHASH_ENTRYTYPE_S 42\n+#define IRDMA_UDA_CQPSQ_QHASH_ENTRYTYPE_M \\\n+\t((u64)0x7 << IRDMA_UDA_CQPSQ_QHASH_ENTRYTYPE_S)\n+#endif /* IRDMA_UDA_D_H */\n", "prefixes": [ "rdma-next", "10/17" ] }