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GET /api/patches/1117703/?format=api
{ "id": 1117703, "url": "http://patchwork.ozlabs.org/api/patches/1117703/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-5-git-send-email-skomatineni@nvidia.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1560843991-24123-5-git-send-email-skomatineni@nvidia.com>", "list_archive_url": null, "date": "2019-06-18T07:46:18", "name": "[V3,04/17] clk: tegra: save and restore divider rate", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "28f768a801ac1c1754c118e41c33dc159de94e01", "submitter": { "id": 75554, "url": "http://patchwork.ozlabs.org/api/people/75554/?format=api", "name": "Sowjanya Komatineni", "email": "skomatineni@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-5-git-send-email-skomatineni@nvidia.com/mbox/", "series": [ { "id": 114436, "url": "http://patchwork.ozlabs.org/api/series/114436/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=114436", "date": "2019-06-18T07:46:16", "name": "SC7 entry and exit support for Tegra210", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/114436/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1117703/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1117703/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=nvidia.com", "ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=nvidia.com header.i=@nvidia.com\n\theader.b=\"Xi2xihYA\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45SgDV6YVZz9s00\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 18 Jun 2019 17:48:10 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1728855AbfFRHqs (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tTue, 18 Jun 2019 03:46:48 -0400", "from hqemgate15.nvidia.com ([216.228.121.64]:19649 \"EHLO\n\thqemgate15.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1728840AbfFRHqq (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Tue, 18 Jun 2019 03:46:46 -0400", "from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)\n\tid <B5d0896e70000>; Tue, 18 Jun 2019 00:46:47 -0700", "from hqmail.nvidia.com ([172.20.161.6])\n\tby hqpgpgate102.nvidia.com (PGP Universal service);\n\tTue, 18 Jun 2019 00:46:46 -0700", "from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL104.nvidia.com\n\t(172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n\tTue, 18 Jun 2019 07:46:45 +0000", "from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com\n\t(172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via\n\tFrontend Transport; Tue, 18 Jun 2019 07:46:45 +0000", "from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by\n\thqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121)\n\tid <B5d0896e30002>; Tue, 18 Jun 2019 00:46:45 -0700" ], "X-PGP-Universal": "processed;\n\tby hqpgpgate102.nvidia.com on Tue, 18 Jun 2019 00:46:46 -0700", "From": "Sowjanya Komatineni <skomatineni@nvidia.com>", "To": "<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<tglx@linutronix.de>, <jason@lakedaemon.net>,\n\t<marc.zyngier@arm.com>, <linus.walleij@linaro.org>,\n\t<stefan@agner.ch>, <mark.rutland@arm.com>", "CC": "<pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>,\n\t<sboyd@kernel.org>, <linux-clk@vger.kernel.org>,\n\t<linux-gpio@vger.kernel.org>, <jckuo@nvidia.com>,\n\t<josephl@nvidia.com>, <talho@nvidia.com>, <skomatineni@nvidia.com>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<mperttunen@nvidia.com>, <spatra@nvidia.com>, <robh+dt@kernel.org>,\n\t<digetx@gmail.com>, <devicetree@vger.kernel.org>", "Subject": "[PATCH V3 04/17] clk: tegra: save and restore divider rate", "Date": "Tue, 18 Jun 2019 00:46:18 -0700", "Message-ID": "<1560843991-24123-5-git-send-email-skomatineni@nvidia.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>", "References": "<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>", "X-NVConfidentiality": "public", "MIME-Version": "1.0", "Content-Type": "text/plain", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;\n\tt=1560844007; bh=MzRi4/U6dTntRT5ieX4O/VlRdfg/Fy9oK6/T3fNDiA8=;\n\th=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:\n\tIn-Reply-To:References:X-NVConfidentiality:MIME-Version:\n\tContent-Type;\n\tb=Xi2xihYAeSEksIwpYYcO1Q1B6z6bQGxuRtbkcYpQYfF57WoLfz9Y8F7lJFF6nwK5n\n\tP0J0erhNcnS+FOtR8CI6YjtKoQMfIHg3WXoQoYB+l+o3Vidu3B5j4tdBbJITJYN6qW\n\tVBrlH+KQ7RhSQG+AUUPMNpEh+el/mtk0OvPWn4ZCKvrYrRKg1pjAjDgcyrLk8hCoUW\n\tTFCUZyKYFRTplnQPY+DPSfbhMrvh2Zvah79ehE4DDkiXI7Lyt3p9DgoEHICA5REl4+\n\taSkchi6R+EMYOIHWAKinlexq1PVbnu3Fg51c4/8qQS8ak7npd6HRPyQbp58TgVOxvD\n\tSUKAqEMwMzLJw==", "Sender": "linux-gpio-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "This patch implements context save and restore for clock divider.\n\nDuring system suspend, core power goes off and looses the settings\nof the Tegra CAR controller registers.\n\nSo during suspend entry the context of clock divider is saved and\non resume context is restored back for normal operation.\n\nSigned-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>\n---\n drivers/clk/tegra/clk-divider.c | 23 +++++++++++++++++++++++\n drivers/clk/tegra/clk.h | 2 ++\n 2 files changed, 25 insertions(+)", "diff": "diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c\nindex e76731fb7d69..ecb7ff9ce97e 100644\n--- a/drivers/clk/tegra/clk-divider.c\n+++ b/drivers/clk/tegra/clk-divider.c\n@@ -109,10 +109,33 @@ static int clk_frac_div_set_rate(struct clk_hw *hw, unsigned long rate,\n \treturn 0;\n }\n \n+static int clk_divider_save_context(struct clk_hw *hw)\n+{\n+\tstruct tegra_clk_frac_div *divider = to_clk_frac_div(hw);\n+\tstruct clk_hw *parent = clk_hw_get_parent(hw);\n+\tunsigned long parent_rate = clk_hw_get_rate(parent);\n+\n+\tdivider->rate = clk_frac_div_recalc_rate(hw, parent_rate);\n+\n+\treturn 0;\n+}\n+\n+static void clk_divider_restore_context(struct clk_hw *hw)\n+{\n+\tstruct tegra_clk_frac_div *divider = to_clk_frac_div(hw);\n+\tstruct clk_hw *parent = clk_hw_get_parent(hw);\n+\tunsigned long parent_rate = clk_hw_get_rate(parent);\n+\n+\tif (clk_frac_div_set_rate(hw, divider->rate, parent_rate) < 0)\n+\t\tWARN_ON(1);\n+}\n+\n const struct clk_ops tegra_clk_frac_div_ops = {\n \t.recalc_rate = clk_frac_div_recalc_rate,\n \t.set_rate = clk_frac_div_set_rate,\n \t.round_rate = clk_frac_div_round_rate,\n+\t.save_context = clk_divider_save_context,\n+\t.restore_context = clk_divider_restore_context,\n };\n \n struct clk *tegra_clk_register_divider(const char *name,\ndiff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h\nindex 905bf1096558..83623f5f55f3 100644\n--- a/drivers/clk/tegra/clk.h\n+++ b/drivers/clk/tegra/clk.h\n@@ -42,6 +42,7 @@ struct clk *tegra_clk_register_sync_source(const char *name,\n * @width:\twidth of the divider bit field\n * @frac_width:\twidth of the fractional bit field\n * @lock:\tregister lock\n+ * @rate:\trate during suspend and resume\n *\n * Flags:\n * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.\n@@ -62,6 +63,7 @@ struct tegra_clk_frac_div {\n \tu8\t\twidth;\n \tu8\t\tfrac_width;\n \tspinlock_t\t*lock;\n+\tunsigned long\trate;\n };\n \n #define to_clk_frac_div(_hw) container_of(_hw, struct tegra_clk_frac_div, hw)\n", "prefixes": [ "V3", "04/17" ] }