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{
    "id": 1117701,
    "url": "http://patchwork.ozlabs.org/api/patches/1117701/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-6-git-send-email-skomatineni@nvidia.com/",
    "project": {
        "id": 42,
        "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api",
        "name": "Linux GPIO development",
        "link_name": "linux-gpio",
        "list_id": "linux-gpio.vger.kernel.org",
        "list_email": "linux-gpio@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<1560843991-24123-6-git-send-email-skomatineni@nvidia.com>",
    "list_archive_url": null,
    "date": "2019-06-18T07:46:19",
    "name": "[V3,05/17] clk: tegra: pllout: save and restore pllout context",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "81df57e715e31411be1f19d06379c3333e48bc38",
    "submitter": {
        "id": 75554,
        "url": "http://patchwork.ozlabs.org/api/people/75554/?format=api",
        "name": "Sowjanya Komatineni",
        "email": "skomatineni@nvidia.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-6-git-send-email-skomatineni@nvidia.com/mbox/",
    "series": [
        {
            "id": 114436,
            "url": "http://patchwork.ozlabs.org/api/series/114436/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=114436",
            "date": "2019-06-18T07:46:16",
            "name": "SC7 entry and exit support for Tegra210",
            "version": 3,
            "mbox": "http://patchwork.ozlabs.org/series/114436/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1117701/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1117701/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<linux-gpio-owner@vger.kernel.org>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org",
        "Authentication-Results": [
            "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)",
            "ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=nvidia.com",
            "ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=nvidia.com header.i=@nvidia.com\n\theader.b=\"nZEdyTYu\"; dkim-atps=neutral"
        ],
        "Received": [
            "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45SgDQ5MYDz9s00\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 18 Jun 2019 17:48:06 +1000 (AEST)",
            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1728927AbfFRHqv (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tTue, 18 Jun 2019 03:46:51 -0400",
            "from hqemgate15.nvidia.com ([216.228.121.64]:19658 \"EHLO\n\thqemgate15.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1728877AbfFRHqu (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Tue, 18 Jun 2019 03:46:50 -0400",
            "from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)\n\tid <B5d0896e90000>; Tue, 18 Jun 2019 00:46:50 -0700",
            "from hqmail.nvidia.com ([172.20.161.6])\n\tby hqpgpgate102.nvidia.com (PGP Universal service);\n\tTue, 18 Jun 2019 00:46:49 -0700",
            "from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL103.nvidia.com\n\t(172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n\tTue, 18 Jun 2019 07:46:48 +0000",
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            "from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com\n\t(172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via\n\tFrontend Transport; Tue, 18 Jun 2019 07:46:48 +0000",
            "from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by\n\thqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121)\n\tid <B5d0896e60001>; Tue, 18 Jun 2019 00:46:48 -0700"
        ],
        "X-PGP-Universal": "processed;\n\tby hqpgpgate102.nvidia.com on Tue, 18 Jun 2019 00:46:49 -0700",
        "From": "Sowjanya Komatineni <skomatineni@nvidia.com>",
        "To": "<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<tglx@linutronix.de>, <jason@lakedaemon.net>,\n\t<marc.zyngier@arm.com>, <linus.walleij@linaro.org>,\n\t<stefan@agner.ch>, <mark.rutland@arm.com>",
        "CC": "<pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>,\n\t<sboyd@kernel.org>, <linux-clk@vger.kernel.org>,\n\t<linux-gpio@vger.kernel.org>, <jckuo@nvidia.com>,\n\t<josephl@nvidia.com>, <talho@nvidia.com>, <skomatineni@nvidia.com>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<mperttunen@nvidia.com>, <spatra@nvidia.com>, <robh+dt@kernel.org>,\n\t<digetx@gmail.com>, <devicetree@vger.kernel.org>",
        "Subject": "[PATCH V3 05/17] clk: tegra: pllout: save and restore pllout context",
        "Date": "Tue, 18 Jun 2019 00:46:19 -0700",
        "Message-ID": "<1560843991-24123-6-git-send-email-skomatineni@nvidia.com>",
        "X-Mailer": "git-send-email 2.7.4",
        "In-Reply-To": "<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>",
        "References": "<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>",
        "X-NVConfidentiality": "public",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;\n\tt=1560844010; bh=Fzu2bnKTENqIS6KXMYVarTHgv0l912Cey6G3jQKOW8c=;\n\th=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:\n\tIn-Reply-To:References:X-NVConfidentiality:MIME-Version:\n\tContent-Type;\n\tb=nZEdyTYucXwLVnD5zK4QnqT+ncZAbxqTqF5uPDpP5MfIbvasiNFCBWs3k75E1BVdo\n\t+34W/kyhru5QrdgiOIbhbKoivkYSQLp5GrXyi8P9Bx2sCqxZzqOG+fRSwNylgNlatX\n\tZFGjLnEqVdOt8RNUa+FSt/iWnjIVkBA1XXflIGVlEwPFWSmRXfEq4M0vlOh6hPIXcg\n\tvaZXvnAq3WrUTeg77NmSsJT/HobtP9KROrHpAv+FcFEIPrJ9RI8GsU/QDcxOBDa0cp\n\tFNsIXUGPZkc5WoQ0/dBR72a/Zcdc40SrIGrYYMfUyNdgUPiqYObcLfJ9SCEBKcQ2ko\n\t8SHYbnn4m0F6Q==",
        "Sender": "linux-gpio-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<linux-gpio.vger.kernel.org>",
        "X-Mailing-List": "linux-gpio@vger.kernel.org"
    },
    "content": "This patch implements save and restore of pllout context.\n\nDuring system suspend, core power goes off and looses the settings\nof the Tegra CAR controller registers.\n\nSo during suspend entry the state of pllout is saved and on resume\nit is restored back to have pllout in same state as before suspend.\n\npllout rate is saved and restore in clock divider so it will be at\nsame rate as before suspend when pllout state is restored.\n\nSigned-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>\n---\n drivers/clk/tegra/clk-pll-out.c | 28 ++++++++++++++++++++++++++++\n drivers/clk/tegra/clk.h         |  3 +++\n 2 files changed, 31 insertions(+)",
    "diff": "diff --git a/drivers/clk/tegra/clk-pll-out.c b/drivers/clk/tegra/clk-pll-out.c\nindex 35f2bf00e1e6..52d140379ce3 100644\n--- a/drivers/clk/tegra/clk-pll-out.c\n+++ b/drivers/clk/tegra/clk-pll-out.c\n@@ -69,10 +69,38 @@ static void clk_pll_out_disable(struct clk_hw *hw)\n \t\tspin_unlock_irqrestore(pll_out->lock, flags);\n }\n \n+static int tegra_clk_pll_out_save_context(struct clk_hw *hw)\n+{\n+\tstruct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);\n+\n+\tif (!strcmp(__clk_get_name(hw->clk), \"pll_re_out1\"))\n+\t\tpll_out->pllout_ctx = readl_relaxed(pll_out->reg);\n+\telse\n+\t\tpll_out->pllout_ctx = clk_hw_get_rate(hw);\n+\n+\treturn 0;\n+}\n+\n+static void tegra_clk_pll_out_restore_context(struct clk_hw *hw)\n+{\n+\tstruct tegra_clk_pll_out *pll_out = to_clk_pll_out(hw);\n+\n+\tif (!strcmp(__clk_get_name(hw->clk), \"pll_re_out1\")) {\n+\t\twritel_relaxed(pll_out->pllout_ctx, pll_out->reg);\n+\t} else {\n+\t\tif (!__clk_get_enable_count(hw->clk))\n+\t\t\tclk_pll_out_disable(hw);\n+\t\telse\n+\t\t\tclk_pll_out_enable(hw);\n+\t}\n+}\n+\n const struct clk_ops tegra_clk_pll_out_ops = {\n \t.is_enabled = clk_pll_out_is_enabled,\n \t.enable = clk_pll_out_enable,\n \t.disable = clk_pll_out_disable,\n+\t.save_context = tegra_clk_pll_out_save_context,\n+\t.restore_context = tegra_clk_pll_out_restore_context,\n };\n \n struct clk *tegra_clk_register_pll_out(const char *name,\ndiff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h\nindex 83623f5f55f3..b47f373c35ad 100644\n--- a/drivers/clk/tegra/clk.h\n+++ b/drivers/clk/tegra/clk.h\n@@ -439,6 +439,8 @@ struct clk *tegra_clk_register_pllu_tegra210(const char *name,\n  * @rst_bit_idx:\tbit to reset PLL divider\n  * @lock:\t\tregister lock\n  * @flags:\t\thardware-specific flags\n+ * @pllout_ctx:\t\tpllout context to save and restore during suspend\n+ *\t\t\tand resume\n  */\n struct tegra_clk_pll_out {\n \tstruct clk_hw\thw;\n@@ -447,6 +449,7 @@ struct tegra_clk_pll_out {\n \tu8\t\trst_bit_idx;\n \tspinlock_t\t*lock;\n \tu8\t\tflags;\n+\tunsigned int\tpllout_ctx;\n };\n \n #define to_clk_pll_out(_hw) container_of(_hw, struct tegra_clk_pll_out, hw)\n",
    "prefixes": [
        "V3",
        "05/17"
    ]
}