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GET /api/patches/1117698/?format=api
{ "id": 1117698, "url": "http://patchwork.ozlabs.org/api/patches/1117698/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-7-git-send-email-skomatineni@nvidia.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1560843991-24123-7-git-send-email-skomatineni@nvidia.com>", "list_archive_url": null, "date": "2019-06-18T07:46:20", "name": "[V3,06/17] clk: tegra: pll: save and restore pll context", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5bbcf22c5f1455a0e83ac494ea469416652fdbea", "submitter": { "id": 75554, "url": "http://patchwork.ozlabs.org/api/people/75554/?format=api", "name": "Sowjanya Komatineni", "email": "skomatineni@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-7-git-send-email-skomatineni@nvidia.com/mbox/", "series": [ { "id": 114436, "url": "http://patchwork.ozlabs.org/api/series/114436/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=114436", "date": "2019-06-18T07:46:16", "name": "SC7 entry and exit support for Tegra210", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/114436/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1117698/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1117698/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=nvidia.com", "ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=nvidia.com header.i=@nvidia.com\n\theader.b=\"MItmjHHN\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45SgDN5jk4z9s00\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 18 Jun 2019 17:48:04 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1728877AbfFRHqz (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tTue, 18 Jun 2019 03:46:55 -0400", "from hqemgate14.nvidia.com ([216.228.121.143]:9704 \"EHLO\n\thqemgate14.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1728840AbfFRHqx (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Tue, 18 Jun 2019 03:46:53 -0400", "from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)\n\tid <B5d0896eb0000>; Tue, 18 Jun 2019 00:46:51 -0700", "from hqmail.nvidia.com ([172.20.161.6])\n\tby hqpgpgate101.nvidia.com (PGP Universal service);\n\tTue, 18 Jun 2019 00:46:51 -0700", "from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL101.nvidia.com\n\t(172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n\tTue, 18 Jun 2019 07:46:51 +0000", "from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL109.nvidia.com\n\t(172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n\tTue, 18 Jun 2019 07:46:51 +0000", "from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com\n\t(172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via\n\tFrontend Transport; Tue, 18 Jun 2019 07:46:51 +0000", "from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by\n\thqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121)\n\tid <B5d0896e80002>; Tue, 18 Jun 2019 00:46:51 -0700" ], "X-PGP-Universal": "processed;\n\tby hqpgpgate101.nvidia.com on Tue, 18 Jun 2019 00:46:51 -0700", "From": "Sowjanya Komatineni <skomatineni@nvidia.com>", "To": "<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<tglx@linutronix.de>, <jason@lakedaemon.net>,\n\t<marc.zyngier@arm.com>, <linus.walleij@linaro.org>,\n\t<stefan@agner.ch>, <mark.rutland@arm.com>", "CC": "<pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>,\n\t<sboyd@kernel.org>, <linux-clk@vger.kernel.org>,\n\t<linux-gpio@vger.kernel.org>, <jckuo@nvidia.com>,\n\t<josephl@nvidia.com>, <talho@nvidia.com>, <skomatineni@nvidia.com>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<mperttunen@nvidia.com>, <spatra@nvidia.com>, <robh+dt@kernel.org>,\n\t<digetx@gmail.com>, <devicetree@vger.kernel.org>", "Subject": "[PATCH V3 06/17] clk: tegra: pll: save and restore pll context", "Date": "Tue, 18 Jun 2019 00:46:20 -0700", "Message-ID": "<1560843991-24123-7-git-send-email-skomatineni@nvidia.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>", "References": "<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>", "X-NVConfidentiality": "public", "MIME-Version": "1.0", "Content-Type": "text/plain", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;\n\tt=1560844011; bh=rv36G1StpVw38zPplJcIr82dyfD5o7fnQYcI5YUInQk=;\n\th=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:\n\tIn-Reply-To:References:X-NVConfidentiality:MIME-Version:\n\tContent-Type;\n\tb=MItmjHHNwWANMr7tsbOe/PKtUMY7Mq3EAtnd7lKg+AgoM3SDmtg8NUU32kfo4UICU\n\tXBdJnnQICRAIYqFWu1il2PpBjF3wF1inReHmwIJCudPMuKDUO2c/sy63M1y1W2FnEE\n\t/npS+gQ+VqTBu1/ooy5UjFQ12ZacXt8o5Q/LJNfm/ThUAFTpKIseWLwmIPN+zUySNH\n\t6mDK55arv7A0XE8tsQuq2hCVDeGVLyuS+0j0KiapAgXjehn6fUBxiZKpvP99nOtd3K\n\t0JFwwTzyqK2xd9aH4sdi7tUBNEemH0+UBgqGMnDRV8qb8E+fI2MSOxPybBntmQv2e0\n\teQ1ZW4/RRc0yw==", "Sender": "linux-gpio-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "This patch implements save and restore of pll context.\n\nDuring system suspend, core power goes off and looses the settings\nof the Tegra CAR controller registers.\n\nSo during suspend entry pll rate is stored and on resume it is\nrestored back along with its state.\n\nSigned-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>\n---\n drivers/clk/tegra/clk-pll.c | 115 ++++++++++++++++++++++++++++++++------------\n drivers/clk/tegra/clk.h | 6 ++-\n 2 files changed, 88 insertions(+), 33 deletions(-)", "diff": "diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c\nindex 1583f5fc992f..4b0ed8fc6268 100644\n--- a/drivers/clk/tegra/clk-pll.c\n+++ b/drivers/clk/tegra/clk-pll.c\n@@ -1008,6 +1008,54 @@ static unsigned long clk_plle_recalc_rate(struct clk_hw *hw,\n \treturn rate;\n }\n \n+void tegra_clk_sync_state_pll(struct clk_hw *hw)\n+{\n+\tif (!__clk_get_enable_count(hw->clk))\n+\t\tclk_pll_disable(hw);\n+\telse\n+\t\tclk_pll_enable(hw);\n+}\n+\n+static int tegra_clk_pll_save_context(struct clk_hw *hw)\n+{\n+\tstruct tegra_clk_pll *pll = to_clk_pll(hw);\n+\n+\tpll->rate = clk_hw_get_rate(hw);\n+\n+\tif (!strcmp(__clk_get_name(hw->clk), \"pll_mb\"))\n+\t\tpll->pllbase_ctx = pll_readl_base(pll);\n+\telse if (!strcmp(__clk_get_name(hw->clk), \"pll_re_vco\"))\n+\t\tpll->pllbase_ctx = pll_readl_base(pll) & (0xf << 16);\n+\n+\treturn 0;\n+}\n+\n+static void tegra_clk_pll_restore_context(struct clk_hw *hw)\n+{\n+\tstruct tegra_clk_pll *pll = to_clk_pll(hw);\n+\tu32 val;\n+\n+\tif (clk_pll_is_enabled(hw))\n+\t\treturn;\n+\n+\tif (!strcmp(__clk_get_name(hw->clk), \"pll_mb\")) {\n+\t\tpll_writel_base(pll->pllbase_ctx, pll);\n+\t} else if (!strcmp(__clk_get_name(hw->clk), \"pll_re_vco\")) {\n+\t\tval = pll_readl_base(pll);\n+\t\tval &= ~(0xf << 16);\n+\t\tpll_writel_base(pll->pllbase_ctx | val, pll);\n+\t}\n+\n+\tif (pll->params->set_defaults)\n+\t\tpll->params->set_defaults(pll);\n+\n+\tclk_set_rate(hw->clk, pll->rate);\n+\n+\t/* do not sync pllx state here. pllx is sync'd after dfll resume */\n+\tif (strcmp(__clk_get_name(hw->clk), \"pll_x\"))\n+\t\ttegra_clk_sync_state_pll(hw);\n+}\n+\n const struct clk_ops tegra_clk_pll_ops = {\n \t.is_enabled = clk_pll_is_enabled,\n \t.enable = clk_pll_enable,\n@@ -1015,6 +1063,8 @@ const struct clk_ops tegra_clk_pll_ops = {\n \t.recalc_rate = clk_pll_recalc_rate,\n \t.round_rate = clk_pll_round_rate,\n \t.set_rate = clk_pll_set_rate,\n+\t.save_context = tegra_clk_pll_save_context,\n+\t.restore_context = tegra_clk_pll_restore_context,\n };\n \n const struct clk_ops tegra_clk_plle_ops = {\n@@ -1802,6 +1852,27 @@ static int clk_pllu_tegra114_enable(struct clk_hw *hw)\n \n \treturn ret;\n }\n+\n+static void _clk_plle_tegra_init_parent(struct tegra_clk_pll *pll)\n+{\n+\tu32 val, val_aux;\n+\n+\t/* ensure parent is set to pll_ref */\n+\tval = pll_readl_base(pll);\n+\tval_aux = pll_readl(pll->params->aux_reg, pll);\n+\n+\tif (val & PLL_BASE_ENABLE) {\n+\t\tif ((val_aux & PLLE_AUX_PLLRE_SEL) ||\n+\t\t (val_aux & PLLE_AUX_PLLP_SEL))\n+\t\t\tWARN(1, \"pll_e enabled with unsupported parent %s\\n\",\n+\t\t\t (val_aux & PLLE_AUX_PLLP_SEL) ? \"pllp_out0\" :\n+\t\t\t \"pll_re_vco\");\n+\t} else {\n+\t\tval_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);\n+\t\tpll_writel(val_aux, pll->params->aux_reg, pll);\n+\t\tfence_udelay(1, pll->clk_base);\n+\t}\n+}\n #endif\n \n static struct tegra_clk_pll *_tegra_init_pll(void __iomem *clk_base,\n@@ -2214,27 +2285,12 @@ struct clk *tegra_clk_register_plle_tegra114(const char *name,\n {\n \tstruct tegra_clk_pll *pll;\n \tstruct clk *clk;\n-\tu32 val, val_aux;\n \n \tpll = _tegra_init_pll(clk_base, NULL, pll_params, lock);\n \tif (IS_ERR(pll))\n \t\treturn ERR_CAST(pll);\n \n-\t/* ensure parent is set to pll_re_vco */\n-\n-\tval = pll_readl_base(pll);\n-\tval_aux = pll_readl(pll_params->aux_reg, pll);\n-\n-\tif (val & PLL_BASE_ENABLE) {\n-\t\tif ((val_aux & PLLE_AUX_PLLRE_SEL) ||\n-\t\t\t(val_aux & PLLE_AUX_PLLP_SEL))\n-\t\t\tWARN(1, \"pll_e enabled with unsupported parent %s\\n\",\n-\t\t\t (val_aux & PLLE_AUX_PLLP_SEL) ? \"pllp_out0\" :\n-\t\t\t\t\t\"pll_re_vco\");\n-\t} else {\n-\t\tval_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);\n-\t\tpll_writel(val_aux, pll_params->aux_reg, pll);\n-\t}\n+\t_clk_plle_tegra_init_parent(pll);\n \n \tclk = _tegra_clk_register_pll(pll, name, parent_name, flags,\n \t\t\t\t &tegra_clk_plle_tegra114_ops);\n@@ -2276,6 +2332,8 @@ static const struct clk_ops tegra_clk_pllss_ops = {\n \t.recalc_rate = clk_pll_recalc_rate,\n \t.round_rate = clk_pll_ramp_round_rate,\n \t.set_rate = clk_pllxc_set_rate,\n+\t.save_context = tegra_clk_pll_save_context,\n+\t.restore_context = tegra_clk_pll_restore_context,\n };\n \n struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name,\n@@ -2520,11 +2578,19 @@ static void clk_plle_tegra210_disable(struct clk_hw *hw)\n \t\tspin_unlock_irqrestore(pll->lock, flags);\n }\n \n+static void tegra_clk_plle_t210_restore_context(struct clk_hw *hw)\n+{\n+\tstruct tegra_clk_pll *pll = to_clk_pll(hw);\n+\n+\t_clk_plle_tegra_init_parent(pll);\n+}\n+\n static const struct clk_ops tegra_clk_plle_tegra210_ops = {\n \t.is_enabled = clk_plle_tegra210_is_enabled,\n \t.enable = clk_plle_tegra210_enable,\n \t.disable = clk_plle_tegra210_disable,\n \t.recalc_rate = clk_pll_recalc_rate,\n+\t.restore_context = tegra_clk_plle_t210_restore_context,\n };\n \n struct clk *tegra_clk_register_plle_tegra210(const char *name,\n@@ -2535,27 +2601,12 @@ struct clk *tegra_clk_register_plle_tegra210(const char *name,\n {\n \tstruct tegra_clk_pll *pll;\n \tstruct clk *clk;\n-\tu32 val, val_aux;\n \n \tpll = _tegra_init_pll(clk_base, NULL, pll_params, lock);\n \tif (IS_ERR(pll))\n \t\treturn ERR_CAST(pll);\n \n-\t/* ensure parent is set to pll_re_vco */\n-\n-\tval = pll_readl_base(pll);\n-\tval_aux = pll_readl(pll_params->aux_reg, pll);\n-\n-\tif (val & PLLE_BASE_ENABLE) {\n-\t\tif ((val_aux & PLLE_AUX_PLLRE_SEL) ||\n-\t\t\t(val_aux & PLLE_AUX_PLLP_SEL))\n-\t\t\tWARN(1, \"pll_e enabled with unsupported parent %s\\n\",\n-\t\t\t (val_aux & PLLE_AUX_PLLP_SEL) ? \"pllp_out0\" :\n-\t\t\t\t\t\"pll_re_vco\");\n-\t} else {\n-\t\tval_aux &= ~(PLLE_AUX_PLLRE_SEL | PLLE_AUX_PLLP_SEL);\n-\t\tpll_writel(val_aux, pll_params->aux_reg, pll);\n-\t}\n+\t_clk_plle_tegra_init_parent(pll);\n \n \tclk = _tegra_clk_register_pll(pll, name, parent_name, flags,\n \t\t\t\t &tegra_clk_plle_tegra210_ops);\ndiff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h\nindex b47f373c35ad..581deb4f3ac0 100644\n--- a/drivers/clk/tegra/clk.h\n+++ b/drivers/clk/tegra/clk.h\n@@ -310,6 +310,8 @@ struct tegra_clk_pll_params {\n * @pmc:\taddress of PMC, required to read override bits\n * @lock:\tregister lock\n * @params:\tPLL parameters\n+ * @rate:\trate during system suspend and resume\n+ * @pllbase_ctx: pll base register value during suspend and resume\n */\n struct tegra_clk_pll {\n \tstruct clk_hw\thw;\n@@ -317,6 +319,8 @@ struct tegra_clk_pll {\n \tvoid __iomem\t*pmc;\n \tspinlock_t\t*lock;\n \tstruct tegra_clk_pll_params\t*params;\n+\tunsigned long\trate;\n+\tunsigned int\tpllbase_ctx;\n };\n \n #define to_clk_pll(_hw) container_of(_hw, struct tegra_clk_pll, hw)\n@@ -834,7 +838,7 @@ u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);\n int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);\n int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,\n \t\t u8 frac_width, u8 flags);\n-\n+void tegra_clk_sync_state_pll(struct clk_hw *hw);\n \n /* Combined read fence with delay */\n #define fence_udelay(delay, reg)\t\\\n", "prefixes": [ "V3", "06/17" ] }