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GET /api/patches/1117697/?format=api
{ "id": 1117697, "url": "http://patchwork.ozlabs.org/api/patches/1117697/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-9-git-send-email-skomatineni@nvidia.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1560843991-24123-9-git-send-email-skomatineni@nvidia.com>", "list_archive_url": null, "date": "2019-06-18T07:46:22", "name": "[V3,08/17] clk: tegra: add support for peripheral clock suspend and resume", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d6682ef9a3ec254531c97395fd0b17727f4dd77f", "submitter": { "id": 75554, "url": "http://patchwork.ozlabs.org/api/people/75554/?format=api", "name": "Sowjanya Komatineni", "email": "skomatineni@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-9-git-send-email-skomatineni@nvidia.com/mbox/", "series": [ { "id": 114436, "url": "http://patchwork.ozlabs.org/api/series/114436/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=114436", "date": "2019-06-18T07:46:16", "name": "SC7 entry and exit support for Tegra210", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/114436/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1117697/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1117697/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=nvidia.com", "ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=nvidia.com header.i=@nvidia.com\n\theader.b=\"G/Ns6yra\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45SgDM5JJFz9s9y\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 18 Jun 2019 17:48:03 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1729045AbfFRHq7 (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tTue, 18 Jun 2019 03:46:59 -0400", "from hqemgate15.nvidia.com ([216.228.121.64]:19673 \"EHLO\n\thqemgate15.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1728840AbfFRHq6 (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Tue, 18 Jun 2019 03:46:58 -0400", "from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)\n\tid <B5d0896f10000>; Tue, 18 Jun 2019 00:46:57 -0700", "from hqmail.nvidia.com ([172.20.161.6])\n\tby hqpgpgate101.nvidia.com (PGP Universal service);\n\tTue, 18 Jun 2019 00:46:56 -0700", "from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL108.nvidia.com\n\t(172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n\tTue, 18 Jun 2019 07:46:55 +0000", "from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com\n\t(172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via\n\tFrontend Transport; Tue, 18 Jun 2019 07:46:56 +0000", "from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by\n\thqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121)\n\tid <B5d0896ee0000>; Tue, 18 Jun 2019 00:46:56 -0700" ], "X-PGP-Universal": "processed;\n\tby hqpgpgate101.nvidia.com on Tue, 18 Jun 2019 00:46:56 -0700", "From": "Sowjanya Komatineni <skomatineni@nvidia.com>", "To": "<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<tglx@linutronix.de>, <jason@lakedaemon.net>,\n\t<marc.zyngier@arm.com>, <linus.walleij@linaro.org>,\n\t<stefan@agner.ch>, <mark.rutland@arm.com>", "CC": "<pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>,\n\t<sboyd@kernel.org>, <linux-clk@vger.kernel.org>,\n\t<linux-gpio@vger.kernel.org>, <jckuo@nvidia.com>,\n\t<josephl@nvidia.com>, <talho@nvidia.com>, <skomatineni@nvidia.com>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<mperttunen@nvidia.com>, <spatra@nvidia.com>, <robh+dt@kernel.org>,\n\t<digetx@gmail.com>, <devicetree@vger.kernel.org>", "Subject": "[PATCH V3 08/17] clk: tegra: add support for peripheral clock\n\tsuspend and resume", "Date": "Tue, 18 Jun 2019 00:46:22 -0700", "Message-ID": "<1560843991-24123-9-git-send-email-skomatineni@nvidia.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>", "References": "<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>", "X-NVConfidentiality": "public", "MIME-Version": "1.0", "Content-Type": "text/plain", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;\n\tt=1560844017; bh=XxXnlq+TujPWngS562UXjtW8HdavZKOUpZld3hJwekQ=;\n\th=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:\n\tIn-Reply-To:References:X-NVConfidentiality:MIME-Version:\n\tContent-Type;\n\tb=G/Ns6yraA5bwBGu3XnArGzWXpybmCZGgv068rhuLenhsEg1bjiqV65EtkBqA2W3qq\n\taxgjbAM7GxSzFulkX++U9u5Q7O3l25GRvuvYwnZ/J2sjndSDogh88w/twGTjUgt8aU\n\tT7H+HI0yyD1hiQVGh17DM7QXcEuWGgFUr9MoAwtO3cj7vYvFfeqNnqT/47+9CaxnAm\n\tOCKxoWlhpQ0XnSSMDZSIzLNz9NYP2Ol+YZSeEsc6XbPXGJLhc1NZywH/TqysO1h8D6\n\txuNY9mHttpr31Y+EDONXyVMflVThS8/Ugw737KqXfnICHrfg++/EVE4SJx4u8BmAo8\n\tj5ci3QiqVVkTg==", "Sender": "linux-gpio-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "This patch creates APIs to save and restore the state of all\nperipheral clocks reset and enables.\n\nThese APIs are invoked by Tegra210 clock driver during suspend and\nresume to save the peripheral clocks state before suspend and to\nrestore them on resume.\n\nSigned-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>\n---\n drivers/clk/tegra/clk.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++++-\n drivers/clk/tegra/clk.h | 3 +++\n 2 files changed, 72 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c\nindex 26690663157a..bd3b46c5f941 100644\n--- a/drivers/clk/tegra/clk.c\n+++ b/drivers/clk/tegra/clk.c\n@@ -70,6 +70,7 @@ static struct clk **clks;\n static int clk_num;\n static struct clk_onecell_data clk_data;\n \n+static u32 *periph_ctx;\n static u32 cclkg_burst_policy_ctx[2];\n static u32 cclklp_burst_policy_ctx[2];\n static u32 sclk_burst_policy_ctx[2];\n@@ -279,6 +280,63 @@ void tegra_sclk_cpulp_burst_policy_restore_context(void)\n \twritel_relaxed(clk_arm_ctx, clk_base + CLK_MASK_ARM);\n }\n \n+void tegra_clk_periph_suspend(void __iomem *clk_base)\n+{\n+\tint i, idx;\n+\n+\tidx = 0;\n+\tfor (i = 0; i < periph_banks; i++, idx++)\n+\t\tperiph_ctx[idx] =\n+\t\t\treadl_relaxed(clk_base + periph_regs[i].rst_reg);\n+\n+\tfor (i = 0; i < periph_banks; i++, idx++)\n+\t\tperiph_ctx[idx] =\n+\t\t\treadl_relaxed(clk_base + periph_regs[i].enb_reg);\n+}\n+\n+void tegra_clk_periph_force_on(u32 *clks_on, int count, void __iomem *clk_base)\n+{\n+\tint i;\n+\n+\tWARN_ON(count != periph_banks);\n+\n+\tfor (i = 0; i < count; i++)\n+\t\twritel_relaxed(clks_on[i], clk_base + periph_regs[i].enb_reg);\n+}\n+\n+void tegra_clk_periph_resume(void __iomem *clk_base)\n+{\n+\tint i, idx;\n+\n+\tidx = 0;\n+\tfor (i = 0; i < periph_banks; i++, idx++)\n+\t\twritel_relaxed(periph_ctx[idx],\n+\t\t\t clk_base + periph_regs[i].rst_reg);\n+\n+\t/* ensure all resets have propagated */\n+\tfence_udelay(2, clk_base);\n+\ttegra_read_chipid();\n+\n+\tfor (i = 0; i < periph_banks; i++, idx++)\n+\t\twritel_relaxed(periph_ctx[idx],\n+\t\t\t clk_base + periph_regs[i].enb_reg);\n+\n+\t/* ensure all enables have propagated */\n+\tfence_udelay(2, clk_base);\n+\ttegra_read_chipid();\n+}\n+\n+static int tegra_clk_suspend_ctx_init(int banks)\n+{\n+\tint err = 0;\n+\n+\tperiph_ctx = kcalloc(2 * banks, sizeof(*periph_ctx), GFP_KERNEL);\n+\tif (!periph_ctx)\n+\t\terr = -ENOMEM;\n+\n+\treturn err;\n+}\n+\n struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks)\n {\n \tclk_base = regs;\n@@ -295,11 +353,21 @@ struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks)\n \tperiph_banks = banks;\n \n \tclks = kcalloc(num, sizeof(struct clk *), GFP_KERNEL);\n-\tif (!clks)\n+\tif (!clks) {\n \t\tkfree(periph_clk_enb_refcnt);\n+\t\treturn NULL;\n+\t}\n \n \tclk_num = num;\n \n+\tif (IS_ENABLED(CONFIG_PM_SLEEP)) {\n+\t\tif (tegra_clk_suspend_ctx_init(banks)) {\n+\t\t\tkfree(periph_clk_enb_refcnt);\n+\t\t\tkfree(clks);\n+\t\t\treturn NULL;\n+\t\t}\n+\t}\n+\n \treturn clks;\n }\n \ndiff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h\nindex c8f8a23096e2..a354cacae5a6 100644\n--- a/drivers/clk/tegra/clk.h\n+++ b/drivers/clk/tegra/clk.h\n@@ -853,6 +853,9 @@ void tegra_cclkg_burst_policy_save_context(void);\n void tegra_cclkg_burst_policy_restore_context(void);\n void tegra_sclk_cclklp_burst_policy_save_context(void);\n void tegra_sclk_cpulp_burst_policy_restore_context(void);\n+void tegra_clk_periph_suspend(void __iomem *clk_base);\n+void tegra_clk_periph_resume(void __iomem *clk_base);\n+void tegra_clk_periph_force_on(u32 *clks_on, int count, void __iomem *clk_base);\n \n /* Combined read fence with delay */\n #define fence_udelay(delay, reg)\t\\\n", "prefixes": [ "V3", "08/17" ] }