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GET /api/patches/1117695/?format=api
{ "id": 1117695, "url": "http://patchwork.ozlabs.org/api/patches/1117695/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-8-git-send-email-skomatineni@nvidia.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1560843991-24123-8-git-send-email-skomatineni@nvidia.com>", "list_archive_url": null, "date": "2019-06-18T07:46:21", "name": "[V3,07/17] clk: tegra: save and restore CPU and System clocks context", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3c8d7dadd44de2395ed4ed663e0f55c1a953a43b", "submitter": { "id": 75554, "url": "http://patchwork.ozlabs.org/api/people/75554/?format=api", "name": "Sowjanya Komatineni", "email": "skomatineni@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-8-git-send-email-skomatineni@nvidia.com/mbox/", "series": [ { "id": 114436, "url": "http://patchwork.ozlabs.org/api/series/114436/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=114436", "date": "2019-06-18T07:46:16", "name": "SC7 entry and exit support for Tegra210", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/114436/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1117695/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1117695/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=nvidia.com", "ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=nvidia.com header.i=@nvidia.com\n\theader.b=\"hmtsUmsB\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45SgDK3WPCz9s9y\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 18 Jun 2019 17:48:01 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1729065AbfFRHrA (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tTue, 18 Jun 2019 03:47:00 -0400", "from hqemgate14.nvidia.com ([216.228.121.143]:9715 \"EHLO\n\thqemgate14.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1726047AbfFRHq4 (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Tue, 18 Jun 2019 03:46:56 -0400", "from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)\n\tid <B5d0896ed0000>; Tue, 18 Jun 2019 00:46:54 -0700", "from hqmail.nvidia.com ([172.20.161.6])\n\tby hqpgpgate102.nvidia.com (PGP Universal service);\n\tTue, 18 Jun 2019 00:46:54 -0700", "from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL104.nvidia.com\n\t(172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n\tTue, 18 Jun 2019 07:46:53 +0000", "from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com\n\t(172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via\n\tFrontend Transport; Tue, 18 Jun 2019 07:46:53 +0000", "from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by\n\thqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121)\n\tid <B5d0896eb0003>; Tue, 18 Jun 2019 00:46:53 -0700" ], "X-PGP-Universal": "processed;\n\tby hqpgpgate102.nvidia.com on Tue, 18 Jun 2019 00:46:54 -0700", "From": "Sowjanya Komatineni <skomatineni@nvidia.com>", "To": "<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<tglx@linutronix.de>, <jason@lakedaemon.net>,\n\t<marc.zyngier@arm.com>, <linus.walleij@linaro.org>,\n\t<stefan@agner.ch>, <mark.rutland@arm.com>", "CC": "<pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>,\n\t<sboyd@kernel.org>, <linux-clk@vger.kernel.org>,\n\t<linux-gpio@vger.kernel.org>, <jckuo@nvidia.com>,\n\t<josephl@nvidia.com>, <talho@nvidia.com>, <skomatineni@nvidia.com>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<mperttunen@nvidia.com>, <spatra@nvidia.com>, <robh+dt@kernel.org>,\n\t<digetx@gmail.com>, <devicetree@vger.kernel.org>", "Subject": "[PATCH V3 07/17] clk: tegra: save and restore CPU and System clocks\n\tcontext", "Date": "Tue, 18 Jun 2019 00:46:21 -0700", "Message-ID": "<1560843991-24123-8-git-send-email-skomatineni@nvidia.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>", "References": "<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>", "X-NVConfidentiality": "public", "MIME-Version": "1.0", "Content-Type": "text/plain", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;\n\tt=1560844014; bh=rX5C6TLRq6S7JDWcvC7pebJyWsbcNEJPnKOIpc/oRDQ=;\n\th=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:\n\tIn-Reply-To:References:X-NVConfidentiality:MIME-Version:\n\tContent-Type;\n\tb=hmtsUmsBcnfkalFaVr5lFf0cnBssKBVcJ8SMd+T64qsDe+rXwauY26LHtvRXFYBU1\n\tID5Y1Acjw8v2KEdAk31OzrvHcOpymFQVGcTyj7nOJZLvko4BTh7f+KYioyCQndZLRt\n\t/+iKvcSGCnYl93hv2IX3v0Q2pj9XRpsgwlkKzx862Bxih2h3+CHvzmvUaqmAoQLD3r\n\taUMPAPB8WI7qQOTl2WXSDY+0wWDnI1itTuSD650GQJ32Ms0gr/ESgVhEuLd+cwZNyq\n\tTjACd0JGQ9iaSIZg2CZhMjuH/Q2/KCXDEmZ3kkVKKjJp4MK5y5f0f9hRIosuQSlXCO\n\t+DuFqEMaPI+7Q==", "Sender": "linux-gpio-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "During system suspend state, core power goes off and looses all the\nCAR controller register settings.\n\nThis patch creates APIs for saving and restoring the context of Tegra\nCPUG, CPULP and SCLK.\n\nCPU and System clock context includes\n- CPUG, CPULP, and SCLK burst policy settings for clock sourcea of all\n their normal states.\n- SCLK divisor and System clock rate for restoring SCLK, AHB and APB\n rates on resume.\n- OSC_DIV settings which are used as reference clock input to some PLLs.\n- SPARE_REG and CLK_MASK settings.\n\nThese APIs are used in Tegra210 clock driver during suspend and resume\noperation.\n\nSigned-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>\n---\n drivers/clk/tegra/clk-tegra-super-gen4.c | 4 --\n drivers/clk/tegra/clk.c | 80 ++++++++++++++++++++++++++++++++\n drivers/clk/tegra/clk.h | 14 ++++++\n 3 files changed, 94 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/clk/tegra/clk-tegra-super-gen4.c b/drivers/clk/tegra/clk-tegra-super-gen4.c\nindex cdfe7c9697e1..ed69ec4d883e 100644\n--- a/drivers/clk/tegra/clk-tegra-super-gen4.c\n+++ b/drivers/clk/tegra/clk-tegra-super-gen4.c\n@@ -19,10 +19,6 @@\n #define PLLX_MISC2 0x514\n #define PLLX_MISC3 0x518\n \n-#define CCLKG_BURST_POLICY 0x368\n-#define CCLKLP_BURST_POLICY 0x370\n-#define SCLK_BURST_POLICY 0x028\n-#define SYSTEM_CLK_RATE 0x030\n #define SCLK_DIVIDER 0x2c\n \n static DEFINE_SPINLOCK(sysrate_lock);\ndiff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c\nindex 573e3c967ae1..26690663157a 100644\n--- a/drivers/clk/tegra/clk.c\n+++ b/drivers/clk/tegra/clk.c\n@@ -70,6 +70,12 @@ static struct clk **clks;\n static int clk_num;\n static struct clk_onecell_data clk_data;\n \n+static u32 cclkg_burst_policy_ctx[2];\n+static u32 cclklp_burst_policy_ctx[2];\n+static u32 sclk_burst_policy_ctx[2];\n+static u32 sys_clk_divisor_ctx, system_rate_ctx;\n+static u32 spare_ctx, misc_clk_enb_ctx, clk_arm_ctx;\n+\n /* Handlers for SoC-specific reset lines */\n static int (*special_reset_assert)(unsigned long);\n static int (*special_reset_deassert)(unsigned long);\n@@ -199,6 +205,80 @@ const struct tegra_clk_periph_regs *get_reg_bank(int clkid)\n \t}\n }\n \n+void tegra_cclkg_burst_policy_save_context(void)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < BURST_POLICY_REG_SIZE; i++)\n+\t\tcclkg_burst_policy_ctx[i] = readl_relaxed(clk_base +\n+\t\t\t\t\t\t\t CCLKG_BURST_POLICY +\n+\t\t\t\t\t\t\t (i * 4));\n+}\n+\n+void tegra_cclkg_burst_policy_restore_context(void)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < BURST_POLICY_REG_SIZE; i++)\n+\t\twritel_relaxed(cclkg_burst_policy_ctx[i],\n+\t\t\t clk_base + CCLKG_BURST_POLICY + (i * 4));\n+\n+\tfence_udelay(2, clk_base);\n+}\n+\n+void tegra_sclk_cclklp_burst_policy_save_context(void)\n+{\n+\tint i;\n+\n+\tfor (i = 0; i < BURST_POLICY_REG_SIZE; i++) {\n+\t\tcclklp_burst_policy_ctx[i] = readl_relaxed(clk_base +\n+\t\t\t\t\t\t\t CCLKLP_BURST_POLICY +\n+\t\t\t\t\t\t\t (i * 4));\n+\n+\t\tsclk_burst_policy_ctx[i] = readl_relaxed(clk_base +\n+\t\t\t\t\t\t\t SCLK_BURST_POLICY +\n+\t\t\t\t\t\t\t (i * 4));\n+\t}\n+\n+\tsys_clk_divisor_ctx = readl_relaxed(clk_base + SYS_CLK_DIV);\n+\tsystem_rate_ctx = readl_relaxed(clk_base + SYSTEM_CLK_RATE);\n+\tspare_ctx = readl_relaxed(clk_base + SPARE_REG0);\n+\tmisc_clk_enb_ctx = readl_relaxed(clk_base + MISC_CLK_ENB);\n+\tclk_arm_ctx = readl_relaxed(clk_base + CLK_MASK_ARM);\n+}\n+\n+void tegra_sclk_cpulp_burst_policy_restore_context(void)\n+{\n+\tint i;\n+\tu32 val;\n+\n+\t/*\n+\t * resume SCLK and CPULP clocks\n+\t * for SCLk, set safe dividers values first and then restore source\n+\t * and dividers\n+\t */\n+\n+\twritel_relaxed(0x1, clk_base + SYSTEM_CLK_RATE);\n+\tval = readl_relaxed(clk_base + SYS_CLK_DIV);\n+\tif (val < sys_clk_divisor_ctx)\n+\t\twritel_relaxed(sys_clk_divisor_ctx, clk_base + SYS_CLK_DIV);\n+\n+\tfence_udelay(2, clk_base);\n+\n+\tfor (i = 0; i < BURST_POLICY_REG_SIZE; i++) {\n+\t\twritel_relaxed(cclklp_burst_policy_ctx[i],\n+\t\t\t clk_base + CCLKLP_BURST_POLICY + (i * 4));\n+\t\twritel_relaxed(sclk_burst_policy_ctx[i],\n+\t\t\t clk_base + SCLK_BURST_POLICY + (i * 4));\n+\t}\n+\n+\twritel_relaxed(sys_clk_divisor_ctx, clk_base + SYS_CLK_DIV);\n+\twritel_relaxed(system_rate_ctx, clk_base + SYSTEM_CLK_RATE);\n+\twritel_relaxed(spare_ctx, clk_base + SPARE_REG0);\n+\twritel_relaxed(misc_clk_enb_ctx, clk_base + MISC_CLK_ENB);\n+\twritel_relaxed(clk_arm_ctx, clk_base + CLK_MASK_ARM);\n+}\n+\n struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks)\n {\n \tclk_base = regs;\ndiff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h\nindex 581deb4f3ac0..c8f8a23096e2 100644\n--- a/drivers/clk/tegra/clk.h\n+++ b/drivers/clk/tegra/clk.h\n@@ -10,6 +10,16 @@\n #include <linux/clkdev.h>\n #include <linux/delay.h>\n \n+#define SCLK_BURST_POLICY\t0x28\n+#define SYSTEM_CLK_RATE\t\t0x30\n+#define CLK_MASK_ARM\t\t0x44\n+#define MISC_CLK_ENB\t\t0x48\n+#define CCLKG_BURST_POLICY\t0x368\n+#define CCLKLP_BURST_POLICY\t0x370\n+#define SYS_CLK_DIV\t\t0x400\n+#define SPARE_REG0 \t\t0x55c\n+#define BURST_POLICY_REG_SIZE\t2\n+\n /**\n * struct tegra_clk_sync_source - external clock source from codec\n *\n@@ -839,6 +849,10 @@ int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);\n int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,\n \t\t u8 frac_width, u8 flags);\n void tegra_clk_sync_state_pll(struct clk_hw *hw);\n+void tegra_cclkg_burst_policy_save_context(void);\n+void tegra_cclkg_burst_policy_restore_context(void);\n+void tegra_sclk_cclklp_burst_policy_save_context(void);\n+void tegra_sclk_cpulp_burst_policy_restore_context(void);\n \n /* Combined read fence with delay */\n #define fence_udelay(delay, reg)\t\\\n", "prefixes": [ "V3", "07/17" ] }