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{
    "id": 1117693,
    "url": "http://patchwork.ozlabs.org/api/patches/1117693/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-10-git-send-email-skomatineni@nvidia.com/",
    "project": {
        "id": 42,
        "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api",
        "name": "Linux GPIO development",
        "link_name": "linux-gpio",
        "list_id": "linux-gpio.vger.kernel.org",
        "list_email": "linux-gpio@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<1560843991-24123-10-git-send-email-skomatineni@nvidia.com>",
    "list_archive_url": null,
    "date": "2019-06-18T07:46:23",
    "name": "[V3,09/17] clk: tegra: support for saving and restoring OSC clock context",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "b5153126c4f7e885713ca719863b8a50133638a3",
    "submitter": {
        "id": 75554,
        "url": "http://patchwork.ozlabs.org/api/people/75554/?format=api",
        "name": "Sowjanya Komatineni",
        "email": "skomatineni@nvidia.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-10-git-send-email-skomatineni@nvidia.com/mbox/",
    "series": [
        {
            "id": 114436,
            "url": "http://patchwork.ozlabs.org/api/series/114436/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=114436",
            "date": "2019-06-18T07:46:16",
            "name": "SC7 entry and exit support for Tegra210",
            "version": 3,
            "mbox": "http://patchwork.ozlabs.org/series/114436/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1117693/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1117693/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<linux-gpio-owner@vger.kernel.org>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org",
        "Authentication-Results": [
            "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)",
            "ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=nvidia.com",
            "ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=nvidia.com header.i=@nvidia.com\n\theader.b=\"bbiwUL/p\"; dkim-atps=neutral"
        ],
        "Received": [
            "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45SgDC38CGz9sDX\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 18 Jun 2019 17:47:55 +1000 (AEST)",
            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1726543AbfFRHry (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tTue, 18 Jun 2019 03:47:54 -0400",
            "from hqemgate16.nvidia.com ([216.228.121.65]:14127 \"EHLO\n\thqemgate16.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1729042AbfFRHrA (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Tue, 18 Jun 2019 03:47:00 -0400",
            "from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)\n\tid <B5d0896f30002>; Tue, 18 Jun 2019 00:46:59 -0700",
            "from hqmail.nvidia.com ([172.20.161.6])\n\tby hqpgpgate101.nvidia.com (PGP Universal service);\n\tTue, 18 Jun 2019 00:46:59 -0700",
            "from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL101.nvidia.com\n\t(172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n\tTue, 18 Jun 2019 07:46:59 +0000",
            "from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL112.nvidia.com\n\t(172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n\tTue, 18 Jun 2019 07:46:59 +0000",
            "from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com\n\t(172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via\n\tFrontend Transport; Tue, 18 Jun 2019 07:46:59 +0000",
            "from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by\n\thqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121)\n\tid <B5d0896f00004>; Tue, 18 Jun 2019 00:46:58 -0700"
        ],
        "X-PGP-Universal": "processed;\n\tby hqpgpgate101.nvidia.com on Tue, 18 Jun 2019 00:46:59 -0700",
        "From": "Sowjanya Komatineni <skomatineni@nvidia.com>",
        "To": "<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<tglx@linutronix.de>, <jason@lakedaemon.net>,\n\t<marc.zyngier@arm.com>, <linus.walleij@linaro.org>,\n\t<stefan@agner.ch>, <mark.rutland@arm.com>",
        "CC": "<pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>,\n\t<sboyd@kernel.org>, <linux-clk@vger.kernel.org>,\n\t<linux-gpio@vger.kernel.org>, <jckuo@nvidia.com>,\n\t<josephl@nvidia.com>, <talho@nvidia.com>, <skomatineni@nvidia.com>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<mperttunen@nvidia.com>, <spatra@nvidia.com>, <robh+dt@kernel.org>,\n\t<digetx@gmail.com>, <devicetree@vger.kernel.org>",
        "Subject": "[PATCH V3 09/17] clk: tegra: support for saving and restoring OSC\n\tclock context",
        "Date": "Tue, 18 Jun 2019 00:46:23 -0700",
        "Message-ID": "<1560843991-24123-10-git-send-email-skomatineni@nvidia.com>",
        "X-Mailer": "git-send-email 2.7.4",
        "In-Reply-To": "<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>",
        "References": "<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>",
        "X-NVConfidentiality": "public",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;\n\tt=1560844019; bh=LIyfL7frpgJGlYXzyqay8F1a5dljw6dG3mcUcqh5Ovo=;\n\th=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:\n\tIn-Reply-To:References:X-NVConfidentiality:MIME-Version:\n\tContent-Type;\n\tb=bbiwUL/pLBrXnaYtjuKw11ptbgg6r6S8BMjNb5ojl5E4hLJA7zy95NqQ1N9xYhsTZ\n\tv07nxMPAUHiCBf9lZgNWiP3i08+w1Teh97MN70tEmmsfdpJ1S37ZD3JBzXM0vx/uHD\n\tYvsjgVNWls2igACcipyiPRIxMqUcw014rcwLQ8MOvpiyRAaxwhuULHrApSndPEFXIa\n\tSxmHlpwTnLy+B/Lqwar1arYm5iGZDuS+YtqX6IZYs906m0f26kDZT2WOYYxHF8Apq5\n\t1x1R4irTJ54KjCmea1CkRR9xnrxKxz22e578wk7f8kGcwH3b/2vjFz3BYtN5b2/KHR\n\tQG7pQ5QXa46Yg==",
        "Sender": "linux-gpio-owner@vger.kernel.org",
        "Precedence": "bulk",
        "List-ID": "<linux-gpio.vger.kernel.org>",
        "X-Mailing-List": "linux-gpio@vger.kernel.org"
    },
    "content": "This patch adds support for storing OSC clock frequency and the\ndrive-strength during OSC clock init and creates an API to restore\nOSC control register value from the saved context.\n\nThis API is invoked by Tegra210 clock driver during system resume\nto restore the  OSC clock settings.\n\nSigned-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>\n---\n drivers/clk/tegra/clk-tegra-fixed.c | 14 ++++++++++++++\n drivers/clk/tegra/clk.h             |  1 +\n 2 files changed, 15 insertions(+)",
    "diff": "diff --git a/drivers/clk/tegra/clk-tegra-fixed.c b/drivers/clk/tegra/clk-tegra-fixed.c\nindex 8d91b2b191cf..e8df0ccbffd0 100644\n--- a/drivers/clk/tegra/clk-tegra-fixed.c\n+++ b/drivers/clk/tegra/clk-tegra-fixed.c\n@@ -17,7 +17,10 @@\n #define OSC_CTRL\t\t\t0x50\n #define OSC_CTRL_OSC_FREQ_SHIFT\t\t28\n #define OSC_CTRL_PLL_REF_DIV_SHIFT\t26\n+#define OSC_CTRL_MASK\t\t\t(0x3f2 |\t\\\n+\t\t\t\t\t(0xf << OSC_CTRL_OSC_FREQ_SHIFT))\n \n+static u32 osc_ctrl_ctx;\n int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,\n \t\t\t      unsigned long *input_freqs, unsigned int num,\n \t\t\t      unsigned int clk_m_div, unsigned long *osc_freq,\n@@ -29,6 +32,7 @@ int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,\n \tunsigned osc_idx;\n \n \tval = readl_relaxed(clk_base + OSC_CTRL);\n+\tosc_ctrl_ctx = val & OSC_CTRL_MASK;\n \tosc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT;\n \n \tif (osc_idx < num)\n@@ -96,3 +100,13 @@ void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks)\n \t\t*dt_clk = clk;\n \t}\n }\n+\n+void tegra_clk_osc_resume(void __iomem *clk_base)\n+{\n+\tu32 val;\n+\n+\tval = readl_relaxed(clk_base + OSC_CTRL) & ~OSC_CTRL_MASK;\n+\tval |= osc_ctrl_ctx;\n+\twritel_relaxed(val, clk_base + OSC_CTRL);\n+\tfence_udelay(2, clk_base);\n+}\ndiff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h\nindex a354cacae5a6..bb34a19aaf26 100644\n--- a/drivers/clk/tegra/clk.h\n+++ b/drivers/clk/tegra/clk.h\n@@ -856,6 +856,7 @@ void tegra_sclk_cpulp_burst_policy_restore_context(void);\n void tegra_clk_periph_suspend(void __iomem *clk_base);\n void tegra_clk_periph_resume(void __iomem *clk_base);\n void tegra_clk_periph_force_on(u32 *clks_on, int count, void __iomem *clk_base);\n+void tegra_clk_osc_resume(void __iomem *clk_base);\n \n /* Combined read fence with delay */\n #define fence_udelay(delay, reg)\t\\\n",
    "prefixes": [
        "V3",
        "09/17"
    ]
}