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GET /api/patches/1117691/?format=api
{ "id": 1117691, "url": "http://patchwork.ozlabs.org/api/patches/1117691/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-11-git-send-email-skomatineni@nvidia.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1560843991-24123-11-git-send-email-skomatineni@nvidia.com>", "list_archive_url": null, "date": "2019-06-18T07:46:24", "name": "[V3,10/17] clk: tegra: add suspend resume support for DFLL", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "699f366b1a14e0100e0c0907823127474d52550f", "submitter": { "id": 75554, "url": "http://patchwork.ozlabs.org/api/people/75554/?format=api", "name": "Sowjanya Komatineni", "email": "skomatineni@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-11-git-send-email-skomatineni@nvidia.com/mbox/", "series": [ { "id": 114436, "url": "http://patchwork.ozlabs.org/api/series/114436/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=114436", "date": "2019-06-18T07:46:16", "name": "SC7 entry and exit support for Tegra210", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/114436/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1117691/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1117691/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=nvidia.com", "ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=nvidia.com header.i=@nvidia.com\n\theader.b=\"IR6FHF69\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45SgD85QTwz9sN6\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 18 Jun 2019 17:47:52 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1729122AbfFRHrE (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tTue, 18 Jun 2019 03:47:04 -0400", "from hqemgate16.nvidia.com ([216.228.121.65]:14145 \"EHLO\n\thqemgate16.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1729110AbfFRHrD (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Tue, 18 Jun 2019 03:47:03 -0400", "from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)\n\tid <B5d0896f60000>; Tue, 18 Jun 2019 00:47:02 -0700", "from hqmail.nvidia.com ([172.20.161.6])\n\tby hqpgpgate101.nvidia.com (PGP Universal service);\n\tTue, 18 Jun 2019 00:47:02 -0700", "from HQMAIL112.nvidia.com (172.18.146.18) by HQMAIL107.nvidia.com\n\t(172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n\tTue, 18 Jun 2019 07:47:02 +0000", "from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL112.nvidia.com\n\t(172.18.146.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n\tTue, 18 Jun 2019 07:47:01 +0000", "from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com\n\t(172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via\n\tFrontend Transport; Tue, 18 Jun 2019 07:47:01 +0000", "from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by\n\thqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121)\n\tid <B5d0896f30002>; Tue, 18 Jun 2019 00:47:01 -0700" ], "X-PGP-Universal": "processed;\n\tby hqpgpgate101.nvidia.com on Tue, 18 Jun 2019 00:47:02 -0700", "From": "Sowjanya Komatineni <skomatineni@nvidia.com>", "To": "<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<tglx@linutronix.de>, <jason@lakedaemon.net>,\n\t<marc.zyngier@arm.com>, <linus.walleij@linaro.org>,\n\t<stefan@agner.ch>, <mark.rutland@arm.com>", "CC": "<pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>,\n\t<sboyd@kernel.org>, <linux-clk@vger.kernel.org>,\n\t<linux-gpio@vger.kernel.org>, <jckuo@nvidia.com>,\n\t<josephl@nvidia.com>, <talho@nvidia.com>, <skomatineni@nvidia.com>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<mperttunen@nvidia.com>, <spatra@nvidia.com>, <robh+dt@kernel.org>,\n\t<digetx@gmail.com>, <devicetree@vger.kernel.org>", "Subject": "[PATCH V3 10/17] clk: tegra: add suspend resume support for DFLL", "Date": "Tue, 18 Jun 2019 00:46:24 -0700", "Message-ID": "<1560843991-24123-11-git-send-email-skomatineni@nvidia.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>", "References": "<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>", "X-NVConfidentiality": "public", "MIME-Version": "1.0", "Content-Type": "text/plain", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;\n\tt=1560844022; bh=qGPf8GeJzYp5l1LLIt//TFC/PvM/mcxGGf78pbIwi5s=;\n\th=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:\n\tIn-Reply-To:References:X-NVConfidentiality:MIME-Version:\n\tContent-Type;\n\tb=IR6FHF692X/4x2AJEoqn/f6pleTP9fwnEp5824cbV7rxFrPGCg6y0CyMKp+MmV8Fr\n\tWVp5wM99/LvkHNw6cdo1+DpGiTR2lLhTBzMZ5+BF6DCToXAz1ot4cIUSW8mKTqZSCv\n\tQ8pR4oZHDaD1sKN9X9DG7aT+IRZJQ8RMR0+4o6PDSgCwnH9m2a3Wgn6Tyr9V4nojdm\n\tGzsZQGW62CxGYzAIz0FJVTwl01DgHpfpydPtkdVbimcbVdcZBcQQikKVtDetx1Ffl6\n\tMZ30jgx67vqwxZYPlVAD/7lCGpYb2H4EBsdMpB8XDjprBHFMjRfJ0Prca9kSjcD/Gl\n\tUsj0xr0jKTNSQ==", "Sender": "linux-gpio-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "This patch creates APIs for supporting Tegra210 clock driver to\nperform DFLL suspend and resume operation.\n\nDuring suspend, DFLL mode is saved and on resume Tegra210 clock driver\ninvokes DFLL resume API to re-initialize DFLL to enable target device\nclock in open loop mode or closed loop mode.\n\nSigned-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>\n---\n drivers/clk/tegra/clk-dfll.c | 78 ++++++++++++++++++++++++++++++++++++++++++++\n drivers/clk/tegra/clk-dfll.h | 2 ++\n 2 files changed, 80 insertions(+)", "diff": "diff --git a/drivers/clk/tegra/clk-dfll.c b/drivers/clk/tegra/clk-dfll.c\nindex f8688c2ddf1a..a1f37cf99b00 100644\n--- a/drivers/clk/tegra/clk-dfll.c\n+++ b/drivers/clk/tegra/clk-dfll.c\n@@ -277,6 +277,7 @@ struct tegra_dfll {\n \tunsigned long\t\t\tdvco_rate_min;\n \n \tenum dfll_ctrl_mode\t\tmode;\n+\tenum dfll_ctrl_mode\t\tresume_mode;\n \tenum dfll_tune_range\t\ttune_range;\n \tstruct dentry\t\t\t*debugfs_dir;\n \tstruct clk_hw\t\t\tdfll_clk_hw;\n@@ -1864,6 +1865,83 @@ static int dfll_fetch_common_params(struct tegra_dfll *td)\n }\n \n /*\n+ * tegra_dfll_suspend\n+ * @pdev: DFLL instance\n+ *\n+ * dfll controls clock/voltage to other devices, including CPU. Therefore,\n+ * dfll driver pm suspend callback does not stop cl-dvfs operations.\n+ */\n+void tegra_dfll_suspend(struct platform_device *pdev)\n+{\n+\tstruct tegra_dfll *td = dev_get_drvdata(&pdev->dev);\n+\n+\tif (!td)\n+\t\treturn;\n+\n+\tif (td->mode <= DFLL_DISABLED)\n+\t\treturn;\n+\n+\ttd->resume_mode = td->mode;\n+\tswitch (td->mode) {\n+\tcase DFLL_CLOSED_LOOP:\n+\t\tdfll_set_mode(td, DFLL_CLOSED_LOOP);\n+\t\tdfll_set_frequency_request(td, &td->last_req);\n+\n+\t\tdfll_unlock(td);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n+\n+/**\n+ * tegra_dfll_resume - reprogram the DFLL after context-loss\n+ * @pdev: DFLL instance\n+ *\n+ * Re-initialize and enable target device clock in open loop mode. Called\n+ * directly from SoC clock resume syscore operation. Closed loop will be\n+ * re-entered in platform syscore ops as well after CPU clock source is\n+ * switched to DFLL in open loop.\n+ */\n+void tegra_dfll_resume(struct platform_device *pdev, bool on_dfll)\n+{\n+\tstruct tegra_dfll *td = dev_get_drvdata(&pdev->dev);\n+\n+\tif (!td)\n+\t\treturn;\n+\n+\tif (on_dfll) {\n+\t\tif (td->resume_mode == DFLL_CLOSED_LOOP)\n+\t\t\tdfll_lock(td);\n+\t\ttd->resume_mode = DFLL_DISABLED;\n+\t\treturn;\n+\t}\n+\n+\treset_control_deassert(td->dvco_rst);\n+\n+\tpm_runtime_get(td->dev);\n+\n+\t/* Re-init DFLL */\n+\tdfll_init_out_if(td);\n+\tdfll_set_default_params(td);\n+\tdfll_set_open_loop_config(td);\n+\n+\tpm_runtime_put(td->dev);\n+\n+\t/* Restore last request and mode up to open loop */\n+\tswitch (td->resume_mode) {\n+\tcase DFLL_CLOSED_LOOP:\n+\tcase DFLL_OPEN_LOOP:\n+\t\tdfll_set_mode(td, DFLL_OPEN_LOOP);\n+\t\tif (td->pmu_if == TEGRA_DFLL_PMU_I2C)\n+\t\t\tdfll_i2c_set_output_enabled(td, false);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n+\n+/*\n * API exported to per-SoC platform drivers\n */\n \ndiff --git a/drivers/clk/tegra/clk-dfll.h b/drivers/clk/tegra/clk-dfll.h\nindex 1b14ebe7268b..c21fc2061a20 100644\n--- a/drivers/clk/tegra/clk-dfll.h\n+++ b/drivers/clk/tegra/clk-dfll.h\n@@ -40,6 +40,8 @@ struct tegra_dfll_soc_data {\n int tegra_dfll_register(struct platform_device *pdev,\n \t\t\tstruct tegra_dfll_soc_data *soc);\n struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev);\n+void tegra_dfll_suspend(struct platform_device *pdev);\n+void tegra_dfll_resume(struct platform_device *pdev, bool on_dfll);\n int tegra_dfll_runtime_suspend(struct device *dev);\n int tegra_dfll_runtime_resume(struct device *dev);\n \n", "prefixes": [ "V3", "10/17" ] }