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GET /api/patches/1117690/?format=api
{ "id": 1117690, "url": "http://patchwork.ozlabs.org/api/patches/1117690/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-13-git-send-email-skomatineni@nvidia.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1560843991-24123-13-git-send-email-skomatineni@nvidia.com>", "list_archive_url": null, "date": "2019-06-18T07:46:26", "name": "[V3,12/17] soc/tegra: pmc: allow support for more tegra wake", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "04c70d44e367c5ee5fdbad629fa9425dfa414094", "submitter": { "id": 75554, "url": "http://patchwork.ozlabs.org/api/people/75554/?format=api", "name": "Sowjanya Komatineni", "email": "skomatineni@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-13-git-send-email-skomatineni@nvidia.com/mbox/", "series": [ { "id": 114436, "url": "http://patchwork.ozlabs.org/api/series/114436/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=114436", "date": "2019-06-18T07:46:16", "name": "SC7 entry and exit support for Tegra210", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/114436/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1117690/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1117690/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=nvidia.com", "ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=nvidia.com header.i=@nvidia.com\n\theader.b=\"ZgEA02B3\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45SgD50QJvz9sBp\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 18 Jun 2019 17:47:49 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1729055AbfFRHrj (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tTue, 18 Jun 2019 03:47:39 -0400", "from hqemgate16.nvidia.com ([216.228.121.65]:14169 \"EHLO\n\thqemgate16.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1726359AbfFRHrI (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Tue, 18 Jun 2019 03:47:08 -0400", "from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)\n\tid <B5d0896fb0000>; Tue, 18 Jun 2019 00:47:07 -0700", "from hqmail.nvidia.com ([172.20.161.6])\n\tby hqpgpgate101.nvidia.com (PGP Universal service);\n\tTue, 18 Jun 2019 00:47:07 -0700", "from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL104.nvidia.com\n\t(172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n\tTue, 18 Jun 2019 07:47:06 +0000", "from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL108.nvidia.com\n\t(172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via\n\tFrontend Transport; Tue, 18 Jun 2019 07:47:06 +0000", "from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by\n\thqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121)\n\tid <B5d0896f80007>; Tue, 18 Jun 2019 00:47:06 -0700" ], "X-PGP-Universal": "processed;\n\tby hqpgpgate101.nvidia.com on Tue, 18 Jun 2019 00:47:07 -0700", "From": "Sowjanya Komatineni <skomatineni@nvidia.com>", "To": "<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<tglx@linutronix.de>, <jason@lakedaemon.net>,\n\t<marc.zyngier@arm.com>, <linus.walleij@linaro.org>,\n\t<stefan@agner.ch>, <mark.rutland@arm.com>", "CC": "<pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>,\n\t<sboyd@kernel.org>, <linux-clk@vger.kernel.org>,\n\t<linux-gpio@vger.kernel.org>, <jckuo@nvidia.com>,\n\t<josephl@nvidia.com>, <talho@nvidia.com>, <skomatineni@nvidia.com>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<mperttunen@nvidia.com>, <spatra@nvidia.com>, <robh+dt@kernel.org>,\n\t<digetx@gmail.com>, <devicetree@vger.kernel.org>", "Subject": "[PATCH V3 12/17] soc/tegra: pmc: allow support for more tegra wake", "Date": "Tue, 18 Jun 2019 00:46:26 -0700", "Message-ID": "<1560843991-24123-13-git-send-email-skomatineni@nvidia.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>", "References": "<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>", "X-NVConfidentiality": "public", "MIME-Version": "1.0", "Content-Type": "text/plain", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;\n\tt=1560844027; bh=4EGQI++zj4lUDjQs0M1vegh7zzNvu5bAdmZ5kricB/0=;\n\th=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:\n\tIn-Reply-To:References:X-NVConfidentiality:MIME-Version:\n\tContent-Type;\n\tb=ZgEA02B306QGuVA6EM5wD1pKUQMNg5hcs5pnmYOGM8L2pnTzCaunYb15iOriCsRuo\n\t28sxZirK2rUfhr9AWRyttvVKg0k6/rhl5wtR/WonT80yHeYDikeIx4PeemZEfrUT4M\n\tGjiwJHkLJ5PBnzn4zOcDmNFi1iRpLKfClU68SedyH7d3OTiQuKjqZ9uByQYhlJ1SqZ\n\t+neCV99leG2sHOSQkzNkdk2CRUYJrn+uMQ6+7K9UjBxyZ7cpuW1z7bOPzCo8rZG9sk\n\t010Hj3R3r6h8sRYyNHeiX5xamg037SKpEg6O28zJ0e3LmNY9RV9MLoiLODug7jzLm7\n\tQDwR/CeQicFjw==", "Sender": "linux-gpio-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "This patch allows to create separate irq_set_wake and irq_set_type\nimplementations for different tegra designs PMC that has different\nwake models which require difference wake registers and different\nprogramming sequence.\n\nAOWAKE model support is available for Tegra186 and Tegra194 only\nand it resides within PMC and supports tiered wake architecture.\n\nTegra210 and prior tegra designs uses PMC directly to receive wake\nevents and coordinate the wake sequence.\n\nSigned-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>\n---\n drivers/soc/tegra/pmc.c | 14 ++++++++++----\n 1 file changed, 10 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c\nindex edd4fe06810f..e87f29a35fcf 100644\n--- a/drivers/soc/tegra/pmc.c\n+++ b/drivers/soc/tegra/pmc.c\n@@ -226,6 +226,8 @@ struct tegra_pmc_soc {\n \tvoid (*setup_irq_polarity)(struct tegra_pmc *pmc,\n \t\t\t\t struct device_node *np,\n \t\t\t\t bool invert);\n+\tint (*irq_set_wake)(struct irq_data *data, unsigned int on);\n+\tint (*irq_set_type)(struct irq_data *data, unsigned int type);\n \n \tconst char * const *reset_sources;\n \tunsigned int num_reset_sources;\n@@ -1919,7 +1921,7 @@ static const struct irq_domain_ops tegra_pmc_irq_domain_ops = {\n \t.alloc = tegra_pmc_irq_alloc,\n };\n \n-static int tegra_pmc_irq_set_wake(struct irq_data *data, unsigned int on)\n+static int tegra186_pmc_irq_set_wake(struct irq_data *data, unsigned int on)\n {\n \tstruct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);\n \tunsigned int offset, bit;\n@@ -1951,7 +1953,7 @@ static int tegra_pmc_irq_set_wake(struct irq_data *data, unsigned int on)\n \treturn 0;\n }\n \n-static int tegra_pmc_irq_set_type(struct irq_data *data, unsigned int type)\n+static int tegra186_pmc_irq_set_type(struct irq_data *data, unsigned int type)\n {\n \tstruct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);\n \tu32 value;\n@@ -2005,8 +2007,10 @@ static int tegra_pmc_irq_init(struct tegra_pmc *pmc)\n \tpmc->irq.irq_unmask = irq_chip_unmask_parent;\n \tpmc->irq.irq_eoi = irq_chip_eoi_parent;\n \tpmc->irq.irq_set_affinity = irq_chip_set_affinity_parent;\n-\tpmc->irq.irq_set_type = tegra_pmc_irq_set_type;\n-\tpmc->irq.irq_set_wake = tegra_pmc_irq_set_wake;\n+\tif (pmc->soc->irq_set_type)\n+\t\tpmc->irq.irq_set_type = pmc->soc->irq_set_type;\n+\tif (pmc->soc->irq_set_wake)\n+\t\tpmc->irq.irq_set_wake = pmc->soc->irq_set_wake;\n \n \tpmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node,\n \t\t\t\t\t &tegra_pmc_irq_domain_ops, pmc);\n@@ -2679,6 +2683,8 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = {\n \t.regs = &tegra186_pmc_regs,\n \t.init = NULL,\n \t.setup_irq_polarity = tegra186_pmc_setup_irq_polarity,\n+\t.irq_set_wake = tegra186_pmc_irq_set_wake,\n+\t.irq_set_type = tegra186_pmc_irq_set_type,\n \t.reset_sources = tegra186_reset_sources,\n \t.num_reset_sources = ARRAY_SIZE(tegra186_reset_sources),\n \t.reset_levels = tegra186_reset_levels,\n", "prefixes": [ "V3", "12/17" ] }