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GET /api/patches/1117681/?format=api
{ "id": 1117681, "url": "http://patchwork.ozlabs.org/api/patches/1117681/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-16-git-send-email-skomatineni@nvidia.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1560843991-24123-16-git-send-email-skomatineni@nvidia.com>", "list_archive_url": null, "date": "2019-06-18T07:46:29", "name": "[V3,15/17] soc/tegra: pmc: configure core power request polarity", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fecbd5c5850e03c2b843eca8fe4542210e3dda82", "submitter": { "id": 75554, "url": "http://patchwork.ozlabs.org/api/people/75554/?format=api", "name": "Sowjanya Komatineni", "email": "skomatineni@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-16-git-send-email-skomatineni@nvidia.com/mbox/", "series": [ { "id": 114436, "url": "http://patchwork.ozlabs.org/api/series/114436/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=114436", "date": "2019-06-18T07:46:16", "name": "SC7 entry and exit support for Tegra210", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/114436/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1117681/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1117681/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=nvidia.com", "ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=nvidia.com header.i=@nvidia.com\n\theader.b=\"Wkp4Qxu1\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45SgCl47Fpz9s4V\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 18 Jun 2019 17:47:31 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1729215AbfFRHrR (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tTue, 18 Jun 2019 03:47:17 -0400", "from hqemgate16.nvidia.com ([216.228.121.65]:14193 \"EHLO\n\thqemgate16.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1726238AbfFRHrQ (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Tue, 18 Jun 2019 03:47:16 -0400", "from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)\n\tid <B5d0897030000>; Tue, 18 Jun 2019 00:47:15 -0700", "from hqmail.nvidia.com ([172.20.161.6])\n\tby hqpgpgate101.nvidia.com (PGP Universal service);\n\tTue, 18 Jun 2019 00:47:15 -0700", "from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL101.nvidia.com\n\t(172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n\tTue, 18 Jun 2019 07:47:15 +0000", "from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL102.nvidia.com\n\t(172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n\tTue, 18 Jun 2019 07:47:15 +0000", "from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com\n\t(172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via\n\tFrontend Transport; Tue, 18 Jun 2019 07:47:15 +0000", "from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by\n\thqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121)\n\tid <B5d0897000006>; Tue, 18 Jun 2019 00:47:15 -0700" ], "X-PGP-Universal": "processed;\n\tby hqpgpgate101.nvidia.com on Tue, 18 Jun 2019 00:47:15 -0700", "From": "Sowjanya Komatineni <skomatineni@nvidia.com>", "To": "<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<tglx@linutronix.de>, <jason@lakedaemon.net>,\n\t<marc.zyngier@arm.com>, <linus.walleij@linaro.org>,\n\t<stefan@agner.ch>, <mark.rutland@arm.com>", "CC": "<pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>,\n\t<sboyd@kernel.org>, <linux-clk@vger.kernel.org>,\n\t<linux-gpio@vger.kernel.org>, <jckuo@nvidia.com>,\n\t<josephl@nvidia.com>, <talho@nvidia.com>, <skomatineni@nvidia.com>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<mperttunen@nvidia.com>, <spatra@nvidia.com>, <robh+dt@kernel.org>,\n\t<digetx@gmail.com>, <devicetree@vger.kernel.org>", "Subject": "[PATCH V3 15/17] soc/tegra: pmc: configure core power request\n\tpolarity", "Date": "Tue, 18 Jun 2019 00:46:29 -0700", "Message-ID": "<1560843991-24123-16-git-send-email-skomatineni@nvidia.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>", "References": "<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>", "X-NVConfidentiality": "public", "MIME-Version": "1.0", "Content-Type": "text/plain", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;\n\tt=1560844035; bh=ZIM1lgKmGOLI8vjBUZA7Djdy5mObSNe1HI0kza+VS88=;\n\th=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:\n\tIn-Reply-To:References:X-NVConfidentiality:MIME-Version:\n\tContent-Type;\n\tb=Wkp4Qxu1JqsaH8jdLmvAIkoRC95+Ax2jKrePMPbf+rOcKLuTcrM9b9uJQyWNi8E7V\n\tBCX2c8EhvV06SxEXy4k98Gw3gWjzK3zFXdarlfVBEANy8yIyR45GV5a8HF47Bpx7TQ\n\tF8szrzHmPD0mZYmcCVm7FLCq6dYFaDjOH728DNWqXu5YfsKRcVDMGFBVkzmnHBHMqC\n\tgkfbXglYAP1LDpOd6SOBkIET/b+YmHq2poXiI1k9Y9yJZOQ1JWaoBo+SIDL/Iiinlv\n\tN0TmSvRWUM1pr44OxVOLhFnqUVBPXmjatk/w1TEmfPrHDylCV9kS7KlbgsGZdvxAzQ\n\thnxLNiPFjE7KA==", "Sender": "linux-gpio-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "This patch configures polarity of the core power request signal\nin PMC control register based on the device tree property.\n\nPMC asserts and de-asserts power request signal based on it polarity\nwhen it need to power-up and power-down the core rail during SC7.\n\nSigned-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>\n---\n drivers/soc/tegra/pmc.c | 6 ++++++\n 1 file changed, 6 insertions(+)", "diff": "diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c\nindex 603fc3bd73f5..c9eea5ef008a 100644\n--- a/drivers/soc/tegra/pmc.c\n+++ b/drivers/soc/tegra/pmc.c\n@@ -56,6 +56,7 @@\n #define PMC_CNTRL_SIDE_EFFECT_LP0\tBIT(14) /* LP0 when CPU pwr gated */\n #define PMC_CNTRL_SYSCLK_OE\t\tBIT(11) /* system clock enable */\n #define PMC_CNTRL_SYSCLK_POLARITY\tBIT(10) /* sys clk polarity */\n+#define PMC_CNTRL_PWRREQ_POLARITY\tBIT(8)\n #define PMC_CNTRL_MAIN_RST\t\tBIT(4)\n #define PMC_CNTRL_LATCH_WAKEUPS\tBIT(5)\n \n@@ -2304,6 +2305,11 @@ static void tegra20_pmc_init(struct tegra_pmc *pmc)\n \telse\n \t\tvalue |= PMC_CNTRL_SYSCLK_POLARITY;\n \n+\tif (pmc->corereq_high)\n+\t\tvalue &= ~PMC_CNTRL_PWRREQ_POLARITY;\n+\telse\n+\t\tvalue |= PMC_CNTRL_PWRREQ_POLARITY;\n+\n \t/* configure the output polarity while the request is tristated */\n \ttegra_pmc_writel(pmc, value, PMC_CNTRL);\n \n", "prefixes": [ "V3", "15/17" ] }