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GET /api/patches/1117677/?format=api
{ "id": 1117677, "url": "http://patchwork.ozlabs.org/api/patches/1117677/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-17-git-send-email-skomatineni@nvidia.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1560843991-24123-17-git-send-email-skomatineni@nvidia.com>", "list_archive_url": null, "date": "2019-06-18T07:46:30", "name": "[V3,16/17] soc/tegra: pmc: configure deep sleep control settings", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "19b9ea9a915edeb2deafbb42d4b2444bf389b5e7", "submitter": { "id": 75554, "url": "http://patchwork.ozlabs.org/api/people/75554/?format=api", "name": "Sowjanya Komatineni", "email": "skomatineni@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-17-git-send-email-skomatineni@nvidia.com/mbox/", "series": [ { "id": 114436, "url": "http://patchwork.ozlabs.org/api/series/114436/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=114436", "date": "2019-06-18T07:46:16", "name": "SC7 entry and exit support for Tegra210", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/114436/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1117677/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1117677/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=nvidia.com", "ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=nvidia.com header.i=@nvidia.com\n\theader.b=\"OB9/UxJy\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45SgCY1Xmvz9s4V\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 18 Jun 2019 17:47:21 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1729238AbfFRHrT (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tTue, 18 Jun 2019 03:47:19 -0400", "from hqemgate15.nvidia.com ([216.228.121.64]:19691 \"EHLO\n\thqemgate15.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1729226AbfFRHrT (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Tue, 18 Jun 2019 03:47:19 -0400", "from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)\n\tid <B5d0897070000>; Tue, 18 Jun 2019 00:47:19 -0700", "from hqmail.nvidia.com ([172.20.161.6])\n\tby hqpgpgate101.nvidia.com (PGP Universal service);\n\tTue, 18 Jun 2019 00:47:18 -0700", "from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL107.nvidia.com\n\t(172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n\tTue, 18 Jun 2019 07:47:18 +0000", "from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com\n\t(172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via\n\tFrontend Transport; Tue, 18 Jun 2019 07:47:17 +0000", "from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by\n\thqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121)\n\tid <B5d0897030001>; Tue, 18 Jun 2019 00:47:17 -0700" ], "X-PGP-Universal": "processed;\n\tby hqpgpgate101.nvidia.com on Tue, 18 Jun 2019 00:47:18 -0700", "From": "Sowjanya Komatineni <skomatineni@nvidia.com>", "To": "<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<tglx@linutronix.de>, <jason@lakedaemon.net>,\n\t<marc.zyngier@arm.com>, <linus.walleij@linaro.org>,\n\t<stefan@agner.ch>, <mark.rutland@arm.com>", "CC": "<pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>,\n\t<sboyd@kernel.org>, <linux-clk@vger.kernel.org>,\n\t<linux-gpio@vger.kernel.org>, <jckuo@nvidia.com>,\n\t<josephl@nvidia.com>, <talho@nvidia.com>, <skomatineni@nvidia.com>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<mperttunen@nvidia.com>, <spatra@nvidia.com>, <robh+dt@kernel.org>,\n\t<digetx@gmail.com>, <devicetree@vger.kernel.org>", "Subject": "[PATCH V3 16/17] soc/tegra: pmc: configure deep sleep control\n\tsettings", "Date": "Tue, 18 Jun 2019 00:46:30 -0700", "Message-ID": "<1560843991-24123-17-git-send-email-skomatineni@nvidia.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>", "References": "<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>", "X-NVConfidentiality": "public", "MIME-Version": "1.0", "Content-Type": "text/plain", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;\n\tt=1560844039; bh=nQJmjDHX/yyz71fC5Ramf2lDdXrwkLYirADexX5oFCU=;\n\th=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:\n\tIn-Reply-To:References:X-NVConfidentiality:MIME-Version:\n\tContent-Type;\n\tb=OB9/UxJyZ+AG0aOpRR1NfNDxjMOzFg6yaSD0RkvrR/nkxWcSxlrQIhNyp08qu4bqF\n\tmc3bSzjBRkcKi+/QmOsuqURXHxkL5HmEbwP9fUtQElV7IP6ue/UFHbYWH4reGbeNFH\n\tGQHEVzXK4shiMQgFqBKYGmQryX9RpdPUvodtlBBPXWdfFoGxGETUiTNFR7wQhaRFos\n\tYBpmbb/V79N7A9CI+Y3uoyvQ+Jwl9zpovqBiRVY9p4NknXrVPq+l5SNIfEdTCdxATc\n\tzEhDU8C59HI3GImfFXPi2s8JK6PiVFxau46UrEbM3dhoBFsaH1zsJfbYDaX/3Okxn7\n\t/XfU5qxT3W6dQ==", "Sender": "linux-gpio-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "Tegra210 and prior Tegra chips have deep sleep entry and wakeup related\ntimings which are platform specific that should be configured before\nentering into deep sleep.\n\nBelow are the timing specific configurations for deep sleep entry and\nwakeup.\n- Core rail power-on stabilization timer\n- OSC clock stabilization timer after SOC rail power is stabilized.\n- Core power off time is the minimum wake delay to keep the system\n in deep sleep state irrespective of any quick wake event.\n\nThese values depends on the discharge time of regulators and turn OFF\ntime of the PMIC to allow the complete system to finish entering into\ndeep sleep state.\n\nThese values vary based on the platform design and are specified\nthrough the device tree.\n\nThis patch has implementation to configure these timings which are must\nto have for proper deep sleep and wakeup operations.\n\nSigned-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>\n---\n drivers/soc/tegra/pmc.c | 12 ++++++++++++\n 1 file changed, 12 insertions(+)", "diff": "diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c\nindex c9eea5ef008a..1b2ecda88a26 100644\n--- a/drivers/soc/tegra/pmc.c\n+++ b/drivers/soc/tegra/pmc.c\n@@ -89,6 +89,8 @@\n \n #define PMC_CPUPWRGOOD_TIMER\t\t0xc8\n #define PMC_CPUPWROFF_TIMER\t\t0xcc\n+#define PMC_COREPWRGOOD_TIMER\t\t0x3c\n+#define PMC_COREPWROFF_TIMER\t\t0xe0\n \n #define PMC_PWR_DET_VALUE\t\t0xe4\n \n@@ -2292,6 +2294,7 @@ static const struct tegra_pmc_regs tegra20_pmc_regs = {\n static void tegra20_pmc_init(struct tegra_pmc *pmc)\n {\n \tu32 value;\n+\tunsigned long osc, pmu, off;\n \n \t/* Always enable CPU power request */\n \tvalue = tegra_pmc_readl(pmc, PMC_CNTRL);\n@@ -2317,6 +2320,15 @@ static void tegra20_pmc_init(struct tegra_pmc *pmc)\n \tvalue = tegra_pmc_readl(pmc, PMC_CNTRL);\n \tvalue |= PMC_CNTRL_SYSCLK_OE;\n \ttegra_pmc_writel(pmc, value, PMC_CNTRL);\n+\n+\tosc = DIV_ROUND_UP_ULL(pmc->core_osc_time * 8192, 1000000);\n+\tpmu = DIV_ROUND_UP_ULL(pmc->core_pmu_time * 32768, 1000000);\n+\toff = DIV_ROUND_UP_ULL(pmc->core_off_time * 32768, 1000000);\n+\tif (osc && pmu)\n+\t\ttegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),\n+\t\t\t\t PMC_COREPWRGOOD_TIMER);\n+\tif (off)\n+\t\ttegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);\n }\n \n static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,\n", "prefixes": [ "V3", "16/17" ] }