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GET /api/patches/1117675/?format=api
{ "id": 1117675, "url": "http://patchwork.ozlabs.org/api/patches/1117675/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-3-git-send-email-skomatineni@nvidia.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1560843991-24123-3-git-send-email-skomatineni@nvidia.com>", "list_archive_url": null, "date": "2019-06-18T07:46:16", "name": "[V3,02/17] pinctrl: tegra: add suspend and resume support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3931a6b4478a062ab239ac89a9ecb49577d01667", "submitter": { "id": 75554, "url": "http://patchwork.ozlabs.org/api/people/75554/?format=api", "name": "Sowjanya Komatineni", "email": "skomatineni@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1560843991-24123-3-git-send-email-skomatineni@nvidia.com/mbox/", "series": [ { "id": 114436, "url": "http://patchwork.ozlabs.org/api/series/114436/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=114436", "date": "2019-06-18T07:46:16", "name": "SC7 entry and exit support for Tegra210", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/114436/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1117675/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1117675/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=pass (p=none dis=none) header.from=nvidia.com", "ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=nvidia.com header.i=@nvidia.com\n\theader.b=\"j6VfsFP+\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 45SgBv1Dpqz9s5c\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 18 Jun 2019 17:46:47 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1728792AbfFRHqp (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tTue, 18 Jun 2019 03:46:45 -0400", "from hqemgate14.nvidia.com ([216.228.121.143]:9678 \"EHLO\n\thqemgate14.nvidia.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1728705AbfFRHqo (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Tue, 18 Jun 2019 03:46:44 -0400", "from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by\n\thqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)\n\tid <B5d0896e00000>; Tue, 18 Jun 2019 00:46:40 -0700", "from hqmail.nvidia.com ([172.20.161.6])\n\tby hqpgpgate101.nvidia.com (PGP Universal service);\n\tTue, 18 Jun 2019 00:46:41 -0700", "from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL104.nvidia.com\n\t(172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n\tTue, 18 Jun 2019 07:46:40 +0000", "from HQMAIL104.nvidia.com (172.18.146.11) by HQMAIL109.nvidia.com\n\t(172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3;\n\tTue, 18 Jun 2019 07:46:40 +0000", "from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL104.nvidia.com\n\t(172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via\n\tFrontend Transport; Tue, 18 Jun 2019 07:46:40 +0000", "from skomatineni-linux.nvidia.com (Not Verified[10.2.168.217]) by\n\thqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121)\n\tid <B5d0896de0002>; Tue, 18 Jun 2019 00:46:40 -0700" ], "X-PGP-Universal": "processed;\n\tby hqpgpgate101.nvidia.com on Tue, 18 Jun 2019 00:46:41 -0700", "From": "Sowjanya Komatineni <skomatineni@nvidia.com>", "To": "<thierry.reding@gmail.com>, <jonathanh@nvidia.com>,\n\t<tglx@linutronix.de>, <jason@lakedaemon.net>,\n\t<marc.zyngier@arm.com>, <linus.walleij@linaro.org>,\n\t<stefan@agner.ch>, <mark.rutland@arm.com>", "CC": "<pdeschrijver@nvidia.com>, <pgaikwad@nvidia.com>,\n\t<sboyd@kernel.org>, <linux-clk@vger.kernel.org>,\n\t<linux-gpio@vger.kernel.org>, <jckuo@nvidia.com>,\n\t<josephl@nvidia.com>, <talho@nvidia.com>, <skomatineni@nvidia.com>,\n\t<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<mperttunen@nvidia.com>, <spatra@nvidia.com>, <robh+dt@kernel.org>,\n\t<digetx@gmail.com>, <devicetree@vger.kernel.org>", "Subject": "[PATCH V3 02/17] pinctrl: tegra: add suspend and resume support", "Date": "Tue, 18 Jun 2019 00:46:16 -0700", "Message-ID": "<1560843991-24123-3-git-send-email-skomatineni@nvidia.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>", "References": "<1560843991-24123-1-git-send-email-skomatineni@nvidia.com>", "X-NVConfidentiality": "public", "MIME-Version": "1.0", "Content-Type": "text/plain", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;\n\tt=1560844001; bh=We6H6QZmq3ulWraKmNFRrGEHqkAGeKtjqQtDHViMyOg=;\n\th=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:\n\tIn-Reply-To:References:X-NVConfidentiality:MIME-Version:\n\tContent-Type;\n\tb=j6VfsFP+B5u1nHhsq13nAS0XmBO+zzY/4I6MCwQSgAYNSnqVuw8vcYKPzhK/NKsYD\n\tYLY3UrGD3y7KfRc0eLbFruN3yj9JLY2RJf5184K48DSqy8EuX0QsImFOJe4VBea9mw\n\tIn3ELIosMCHaI/7BnQadpOl0EZrAE4N7SYFNaFhHFd3ehHhWDPlYzKfMX4YWb7R6lx\n\tLf63DwqavQA9boLuOv0eG1jmlV8XgAOUeK5HL/T8JsDGfqzpkXkNOALneXtPsydIjn\n\t5dtf6n0b8tLt0SSuZS63sMOkzLcjkEDF/rLWtil2tPX2zI1WL5vrwBTlhjqWCdj6TG\n\tr9QheNo0H0YyA==", "Sender": "linux-gpio-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "This patch adds suspend and resume support for Tegra pinctrl driver\nand registers them to syscore so the pinmux settings are restored\nbefore the devices resume.\n\nSigned-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>\n---\n drivers/pinctrl/tegra/pinctrl-tegra.c | 62 ++++++++++++++++++++++++++++++++\n drivers/pinctrl/tegra/pinctrl-tegra.h | 5 +++\n drivers/pinctrl/tegra/pinctrl-tegra114.c | 1 +\n drivers/pinctrl/tegra/pinctrl-tegra124.c | 1 +\n drivers/pinctrl/tegra/pinctrl-tegra20.c | 1 +\n drivers/pinctrl/tegra/pinctrl-tegra210.c | 13 +++++++\n drivers/pinctrl/tegra/pinctrl-tegra30.c | 1 +\n 7 files changed, 84 insertions(+)", "diff": "diff --git a/drivers/pinctrl/tegra/pinctrl-tegra.c b/drivers/pinctrl/tegra/pinctrl-tegra.c\nindex 34596b246578..ceced30d8bd1 100644\n--- a/drivers/pinctrl/tegra/pinctrl-tegra.c\n+++ b/drivers/pinctrl/tegra/pinctrl-tegra.c\n@@ -20,11 +20,16 @@\n #include <linux/pinctrl/pinmux.h>\n #include <linux/pinctrl/pinconf.h>\n #include <linux/slab.h>\n+#include <linux/syscore_ops.h>\n \n #include \"../core.h\"\n #include \"../pinctrl-utils.h\"\n #include \"pinctrl-tegra.h\"\n \n+#define EMMC2_PAD_CFGPADCTRL_0\t\t\t0x1c8\n+#define EMMC4_PAD_CFGPADCTRL_0\t\t\t0x1e0\n+#define EMMC_DPD_PARKING\t\t\t(0x1fff << 14)\n+\n static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)\n {\n \treturn readl(pmx->regs[bank] + reg);\n@@ -619,6 +624,48 @@ static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)\n \t\t\tpmx_writel(pmx, val, g->mux_bank, g->mux_reg);\n \t\t}\n \t}\n+\n+\tif (pmx->soc->has_park_padcfg) {\n+\t\tval = pmx_readl(pmx, 0, EMMC2_PAD_CFGPADCTRL_0);\n+\t\tval &= ~EMMC_DPD_PARKING;\n+\t\tpmx_writel(pmx, val, 0, EMMC2_PAD_CFGPADCTRL_0);\n+\n+\t\tval = pmx_readl(pmx, 0, EMMC4_PAD_CFGPADCTRL_0);\n+\t\tval &= ~EMMC_DPD_PARKING;\n+\t\tpmx_writel(pmx, val, 0, EMMC4_PAD_CFGPADCTRL_0);\n+\t}\n+}\n+\n+int __maybe_unused tegra_pinctrl_suspend(struct device *dev)\n+{\n+\tstruct tegra_pmx *pmx = dev_get_drvdata(dev);\n+\tu32 *backup_regs = pmx->backup_regs;\n+\tu32 *regs;\n+\tint i, j;\n+\n+\tfor (i = 0; i < pmx->nbanks; i++) {\n+\t\tregs = pmx->regs[i];\n+\t\tfor (j = 0; j < pmx->reg_bank_size[i] / 4; j++)\n+\t\t\t*backup_regs++ = readl(regs++);\n+\t}\n+\n+\treturn pinctrl_force_sleep(pmx->pctl);\n+}\n+\n+int __maybe_unused tegra_pinctrl_resume(struct device *dev)\n+{\n+\tstruct tegra_pmx *pmx = dev_get_drvdata(dev);\n+\tu32 *backup_regs = pmx->backup_regs;\n+\tu32 *regs;\n+\tint i, j;\n+\n+\tfor (i = 0; i < pmx->nbanks; i++) {\n+\t\tregs = pmx->regs[i];\n+\t\tfor (j = 0; j < pmx->reg_bank_size[i] / 4; j++)\n+\t\t\twritel(*backup_regs++, regs++);\n+\t}\n+\n+\treturn 0;\n }\n \n static bool gpio_node_has_range(const char *compatible)\n@@ -645,6 +692,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev,\n \tint i;\n \tconst char **group_pins;\n \tint fn, gn, gfn;\n+\tunsigned long backup_regs_size = 0;\n \n \tpmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);\n \tif (!pmx)\n@@ -697,6 +745,7 @@ int tegra_pinctrl_probe(struct platform_device *pdev,\n \t\tres = platform_get_resource(pdev, IORESOURCE_MEM, i);\n \t\tif (!res)\n \t\t\tbreak;\n+\t\tbackup_regs_size += resource_size(res);\n \t}\n \tpmx->nbanks = i;\n \n@@ -705,11 +754,24 @@ int tegra_pinctrl_probe(struct platform_device *pdev,\n \tif (!pmx->regs)\n \t\treturn -ENOMEM;\n \n+\tpmx->reg_bank_size = devm_kcalloc(&pdev->dev, pmx->nbanks,\n+\t\t\t\t\t sizeof(*pmx->reg_bank_size),\n+\t\t\t\t\t GFP_KERNEL);\n+\tif (!pmx->reg_bank_size)\n+\t\treturn -ENOMEM;\n+\n+\tpmx->backup_regs = devm_kzalloc(&pdev->dev, backup_regs_size,\n+\t\t\t\t\tGFP_KERNEL);\n+\tif (!pmx->backup_regs)\n+\t\treturn -ENOMEM;\n+\n \tfor (i = 0; i < pmx->nbanks; i++) {\n \t\tres = platform_get_resource(pdev, IORESOURCE_MEM, i);\n \t\tpmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);\n \t\tif (IS_ERR(pmx->regs[i]))\n \t\t\treturn PTR_ERR(pmx->regs[i]);\n+\n+\t\tpmx->reg_bank_size[i] = resource_size(res);\n \t}\n \n \tpmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx);\ndiff --git a/drivers/pinctrl/tegra/pinctrl-tegra.h b/drivers/pinctrl/tegra/pinctrl-tegra.h\nindex 287702660783..d63e472ee0e1 100644\n--- a/drivers/pinctrl/tegra/pinctrl-tegra.h\n+++ b/drivers/pinctrl/tegra/pinctrl-tegra.h\n@@ -17,6 +17,8 @@ struct tegra_pmx {\n \n \tint nbanks;\n \tvoid __iomem **regs;\n+\tsize_t *reg_bank_size;\n+\tu32 *backup_regs;\n };\n \n enum tegra_pinconf_param {\n@@ -191,8 +193,11 @@ struct tegra_pinctrl_soc_data {\n \tbool hsm_in_mux;\n \tbool schmitt_in_mux;\n \tbool drvtype_in_mux;\n+\tbool has_park_padcfg;\n };\n \n int tegra_pinctrl_probe(struct platform_device *pdev,\n \t\t\tconst struct tegra_pinctrl_soc_data *soc_data);\n+int __maybe_unused tegra_pinctrl_suspend(struct device *dev);\n+int __maybe_unused tegra_pinctrl_resume(struct device *dev);\n #endif\ndiff --git a/drivers/pinctrl/tegra/pinctrl-tegra114.c b/drivers/pinctrl/tegra/pinctrl-tegra114.c\nindex 762151f17a88..06ea8164df9d 100644\n--- a/drivers/pinctrl/tegra/pinctrl-tegra114.c\n+++ b/drivers/pinctrl/tegra/pinctrl-tegra114.c\n@@ -1841,6 +1841,7 @@ static const struct tegra_pinctrl_soc_data tegra114_pinctrl = {\n \t.hsm_in_mux = false,\n \t.schmitt_in_mux = false,\n \t.drvtype_in_mux = false,\n+\t.has_park_padcfg = false,\n };\n \n static int tegra114_pinctrl_probe(struct platform_device *pdev)\ndiff --git a/drivers/pinctrl/tegra/pinctrl-tegra124.c b/drivers/pinctrl/tegra/pinctrl-tegra124.c\nindex 930c43758c92..abc8fe92d154 100644\n--- a/drivers/pinctrl/tegra/pinctrl-tegra124.c\n+++ b/drivers/pinctrl/tegra/pinctrl-tegra124.c\n@@ -2053,6 +2053,7 @@ static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {\n \t.hsm_in_mux = false,\n \t.schmitt_in_mux = false,\n \t.drvtype_in_mux = false,\n+\t.has_park_padcfg = false,\n };\n \n static int tegra124_pinctrl_probe(struct platform_device *pdev)\ndiff --git a/drivers/pinctrl/tegra/pinctrl-tegra20.c b/drivers/pinctrl/tegra/pinctrl-tegra20.c\nindex 4b7837e38fb5..993b82cbfba7 100644\n--- a/drivers/pinctrl/tegra/pinctrl-tegra20.c\n+++ b/drivers/pinctrl/tegra/pinctrl-tegra20.c\n@@ -2223,6 +2223,7 @@ static const struct tegra_pinctrl_soc_data tegra20_pinctrl = {\n \t.hsm_in_mux = false,\n \t.schmitt_in_mux = false,\n \t.drvtype_in_mux = false,\n+\t.has_park_padcfg = false,\n };\n \n static const char *cdev1_parents[] = {\ndiff --git a/drivers/pinctrl/tegra/pinctrl-tegra210.c b/drivers/pinctrl/tegra/pinctrl-tegra210.c\nindex 0b56ad5c9c1c..10e8a2ec8094 100644\n--- a/drivers/pinctrl/tegra/pinctrl-tegra210.c\n+++ b/drivers/pinctrl/tegra/pinctrl-tegra210.c\n@@ -1555,6 +1555,7 @@ static const struct tegra_pinctrl_soc_data tegra210_pinctrl = {\n \t.hsm_in_mux = true,\n \t.schmitt_in_mux = true,\n \t.drvtype_in_mux = true,\n+\t.has_park_padcfg = true,\n };\n \n static int tegra210_pinctrl_probe(struct platform_device *pdev)\n@@ -1562,6 +1563,17 @@ static int tegra210_pinctrl_probe(struct platform_device *pdev)\n \treturn tegra_pinctrl_probe(pdev, &tegra210_pinctrl);\n }\n \n+#ifdef CONFIG_PM_SLEEP\n+static const struct dev_pm_ops tegra_pinctrl_pm = {\n+\t.suspend = &tegra_pinctrl_suspend,\n+\t.resume = &tegra_pinctrl_resume\n+};\n+\n+#define TEGRA_PINCTRL_PM\t(&tegra_pinctrl_pm)\n+#else\n+#define TEGRA_PINCTRL_PM\tNULL\n+#endif\n+\n static const struct of_device_id tegra210_pinctrl_of_match[] = {\n \t{ .compatible = \"nvidia,tegra210-pinmux\", },\n \t{ },\n@@ -1571,6 +1583,7 @@ static struct platform_driver tegra210_pinctrl_driver = {\n \t.driver = {\n \t\t.name = \"tegra210-pinctrl\",\n \t\t.of_match_table = tegra210_pinctrl_of_match,\n+\t\t.pm = TEGRA_PINCTRL_PM,\n \t},\n \t.probe = tegra210_pinctrl_probe,\n };\ndiff --git a/drivers/pinctrl/tegra/pinctrl-tegra30.c b/drivers/pinctrl/tegra/pinctrl-tegra30.c\nindex 610124c3d192..779ee40e5f21 100644\n--- a/drivers/pinctrl/tegra/pinctrl-tegra30.c\n+++ b/drivers/pinctrl/tegra/pinctrl-tegra30.c\n@@ -2476,6 +2476,7 @@ static const struct tegra_pinctrl_soc_data tegra30_pinctrl = {\n \t.hsm_in_mux = false,\n \t.schmitt_in_mux = false,\n \t.drvtype_in_mux = false,\n+\t.has_park_padcfg = false,\n };\n \n static int tegra30_pinctrl_probe(struct platform_device *pdev)\n", "prefixes": [ "V3", "02/17" ] }