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GET /api/patches/1112163/?format=api
{ "id": 1112163, "url": "http://patchwork.ozlabs.org/api/patches/1112163/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190607181920.23339-1-colin.king@canonical.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190607181920.23339-1-colin.king@canonical.com>", "list_archive_url": null, "date": "2019-06-07T18:19:20", "name": "[next,V2] ixgbe: fix potential u32 overflow on shift", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "a0e7231d8cb67cd9fd857268037993bf9fb1d05a", "submitter": { "id": 2900, "url": "http://patchwork.ozlabs.org/api/people/2900/?format=api", "name": "Colin Ian King", "email": "colin.king@canonical.com" }, "delegate": { "id": 68, "url": "http://patchwork.ozlabs.org/api/users/68/?format=api", "username": "jtkirshe", "first_name": "Jeff", "last_name": "Kirsher", "email": "jeffrey.t.kirsher@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20190607181920.23339-1-colin.king@canonical.com/mbox/", "series": [ { "id": 112516, "url": "http://patchwork.ozlabs.org/api/series/112516/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=112516", "date": "2019-06-07T18:19:20", "name": "[next,V2] ixgbe: fix potential u32 overflow on shift", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/112516/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1112163/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1112163/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=osuosl.org\n\t(client-ip=140.211.166.137; helo=fraxinus.osuosl.org;\n\tenvelope-from=intel-wired-lan-bounces@osuosl.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=fail (p=none dis=none)\n\theader.from=canonical.com" ], "Received": [ "from fraxinus.osuosl.org (smtp4.osuosl.org [140.211.166.137])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 45L9m52GGTz9sDB\n\tfor <incoming@patchwork.ozlabs.org>;\n\tSat, 8 Jun 2019 04:19:30 +1000 (AEST)", "from localhost (localhost [127.0.0.1])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 4B5FC86934;\n\tFri, 7 Jun 2019 18:19:28 +0000 (UTC)", "from fraxinus.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id Z82cqwTUjXfQ; Fri, 7 Jun 2019 18:19:27 +0000 (UTC)", "from ash.osuosl.org (ash.osuosl.org [140.211.166.34])\n\tby fraxinus.osuosl.org (Postfix) with ESMTP id 72C9C86928;\n\tFri, 7 Jun 2019 18:19:27 +0000 (UTC)", "from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136])\n\tby ash.osuosl.org (Postfix) with ESMTP id 7C4A11BF31C\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 7 Jun 2019 18:19:26 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n\tby silver.osuosl.org (Postfix) with ESMTP id 782D620764\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 7 Jun 2019 18:19:26 +0000 (UTC)", "from silver.osuosl.org ([127.0.0.1])\n\tby localhost (.osuosl.org [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id axFcwMXKAK9z for <intel-wired-lan@lists.osuosl.org>;\n\tFri, 7 Jun 2019 18:19:25 +0000 (UTC)", "from youngberry.canonical.com (youngberry.canonical.com\n\t[91.189.89.112])\n\tby silver.osuosl.org (Postfix) with ESMTPS id 9E4BE203F1\n\tfor <intel-wired-lan@lists.osuosl.org>;\n\tFri, 7 Jun 2019 18:19:25 +0000 (UTC)", "from 1.general.cking.uk.vpn ([10.172.193.212] helo=localhost)\n\tby youngberry.canonical.com with esmtpsa\n\t(TLS1.0:RSA_AES_256_CBC_SHA1:32)\n\t(Exim 4.76) (envelope-from <colin.king@canonical.com>)\n\tid 1hZJSS-0007zx-Mn; Fri, 07 Jun 2019 18:19:20 +0000" ], "X-Virus-Scanned": [ "amavisd-new at osuosl.org", "amavisd-new at osuosl.org" ], "X-Greylist": "domain auto-whitelisted by SQLgrey-1.7.6", "From": "Colin King <colin.king@canonical.com>", "To": "Jacob Keller <jacob.e.keller@intel.com>,\n\tJeff Kirsher <jeffrey.t.kirsher@intel.com>,\n\t\"David S . Miller\" <davem@davemloft.net>,\n\tintel-wired-lan@lists.osuosl.org, netdev@vger.kernel.org", "Date": "Fri, 7 Jun 2019 19:19:20 +0100", "Message-Id": "<20190607181920.23339-1-colin.king@canonical.com>", "X-Mailer": "git-send-email 2.20.1", "MIME-Version": "1.0", "Subject": "[Intel-wired-lan] [PATCH][next][V2] ixgbe: fix potential u32\n\toverflow on shift", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n\t<intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>, \n\t<mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Cc": "kernel-janitors@vger.kernel.org, linux-kernel@vger.kernel.org", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Colin Ian King <colin.king@canonical.com>\n\nThe u32 variable rem is being shifted using u32 arithmetic however\nit is being passed to div_u64 that expects the expression to be a u64.\nThe 32 bit shift may potentially overflow, so cast rem to a u64 before\nshifting to avoid this. Also remove comment about overflow.\n\nAddresses-Coverity: (\"Unintentional integer overflow\")\nFixes: cd4583206990 (\"ixgbe: implement support for SDP/PPS output on X550 hardware\")\nFixes: 68d9676fc04e (\"ixgbe: fix PTP SDP pin setup on X540 hardware\")\nSigned-off-by: Colin Ian King <colin.king@canonical.com>\n---\n\nV2: update comment\n\n---\n drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c | 14 ++++----------\n 1 file changed, 4 insertions(+), 10 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c\nindex 2c4d327fcc2e..0be13a90ff79 100644\n--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c\n+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c\n@@ -205,11 +205,8 @@ static void ixgbe_ptp_setup_sdp_X540(struct ixgbe_adapter *adapter)\n \t */\n \trem = (NS_PER_SEC - rem);\n \n-\t/* Adjust the clock edge to align with the next full second. This\n-\t * assumes that the cycle counter shift is small enough to avoid\n-\t * overflowing when shifting the remainder.\n-\t */\n-\tclock_edge += div_u64((rem << cc->shift), cc->mult);\n+\t/* Adjust the clock edge to align with the next full second. */\n+\tclock_edge += div_u64(((u64)rem << cc->shift), cc->mult);\n \ttrgttiml = (u32)clock_edge;\n \ttrgttimh = (u32)(clock_edge >> 32);\n \n@@ -291,11 +288,8 @@ static void ixgbe_ptp_setup_sdp_X550(struct ixgbe_adapter *adapter)\n \t */\n \trem = (NS_PER_SEC - rem);\n \n-\t/* Adjust the clock edge to align with the next full second. This\n-\t * assumes that the cycle counter shift is small enough to avoid\n-\t * overflowing when shifting the remainder.\n-\t */\n-\tclock_edge += div_u64((rem << cc->shift), cc->mult);\n+\t/* Adjust the clock edge to align with the next full second. */\n+\tclock_edge += div_u64(((u64)rem << cc->shift), cc->mult);\n \n \t/* X550 hardware stores the time in 32bits of 'billions of cycles' and\n \t * 32bits of 'cycles'. There's no guarantee that cycles represents\n", "prefixes": [ "next", "V2" ] }