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GET /api/patches/1111105/?format=api
{ "id": 1111105, "url": "http://patchwork.ozlabs.org/api/patches/1111105/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1559824507-25766-1-git-send-email-vabhav.sharma@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1559824507-25766-1-git-send-email-vabhav.sharma@nxp.com>", "list_archive_url": null, "date": "2019-06-06T12:35:28", "name": "[U-Boot,v2] armv8: ls1046afrwy: Add support for LS1046AFRWY platform", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "e8195595808e2531d3fecd4f8673acee582f0ada", "submitter": { "id": 74765, "url": "http://patchwork.ozlabs.org/api/people/74765/?format=api", "name": "Vabhav Sharma", "email": "vabhav.sharma@nxp.com" }, "delegate": { "id": 2467, "url": "http://patchwork.ozlabs.org/api/users/2467/?format=api", "username": "prabhu_kush", "first_name": "Prabhakar", "last_name": "Kushwaha", "email": "prabhakar@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1559824507-25766-1-git-send-email-vabhav.sharma@nxp.com/mbox/", "series": [ { "id": 112196, "url": "http://patchwork.ozlabs.org/api/series/112196/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=112196", "date": "2019-06-06T12:35:28", "name": "[U-Boot,v2] armv8: ls1046afrwy: Add support for LS1046AFRWY platform", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/112196/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1111105/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1111105/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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Thu, 6 Jun 2019 12:35:30 +0000 (UTC)", "from VI1PR04MB4800.eurprd04.prod.outlook.com (20.177.48.221) by\n\tVI1PR04MB4206.eurprd04.prod.outlook.com (52.134.30.159) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n\t15.20.1965.12; Thu, 6 Jun 2019 12:35:28 +0000", "from VI1PR04MB4800.eurprd04.prod.outlook.com\n\t([fe80::2891:4e93:da53:30de]) by\n\tVI1PR04MB4800.eurprd04.prod.outlook.com\n\t([fe80::2891:4e93:da53:30de%6]) with mapi id 15.20.1965.011;\n\tThu, 6 Jun 2019 12:35:28 +0000" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=SPF_HELO_PASS, T_DKIM_INVALID\n\tautolearn=unavailable autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n\tbh=RwAzn0/gGhVaeYiSj1ri4COCz4CsYia+G2lmtmJ6Kno=;\n\tb=Z6nsltSF9DFofK7WX/fVU3f6Ruct6kW7n82AEeDh1EcZzVwkkI8mZTLeTGfWwdGBxpta8cWwlUWkPpSomGgTkI2GQqojfs174xie7xRYSMXfVeZJqHhPChVEu6MYRDpS6Zxh+tOoEyDOS1wPmhz7d4s4zLCK7xEIiU+QoUGv9Ts=", "From": "Vabhav Sharma <vabhav.sharma@nxp.com>", "To": "\"u-boot@lists.denx.de\" <u-boot@lists.denx.de>", "Thread-Topic": "[PATCH v2] armv8: ls1046afrwy: Add support for LS1046AFRWY\n\tplatform", "Thread-Index": "AQHVHGRSaaS6WB34V06jpbR7Pu4CTw==", "Date": "Thu, 6 Jun 2019 12:35:28 +0000", "Message-ID": "<1559824507-25766-1-git-send-email-vabhav.sharma@nxp.com>", "Accept-Language": "en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "x-clientproxiedby": "BM1PR01CA0144.INDPRD01.PROD.OUTLOOK.COM\n\t(2603:1096:b00:68::14) To VI1PR04MB4800.eurprd04.prod.outlook.com\n\t(2603:10a6:803:53::29)", "authentication-results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; 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SFP:1101; SCL:1; SRVR:VI1PR04MB4206;\n\tH:VI1PR04MB4800.eurprd04.prod.outlook.com; FPR:; SPF:None; LANG:en;\n\tPTR:InfoNoRecords; MX:1; A:1; ", "received-spf": "None (protection.outlook.com: nxp.com does not designate\n\tpermitted sender hosts)", "x-ms-exchange-senderadcheck": "1", "x-microsoft-antispam-message-info": "SrKajaWoPShR+XKB0mglKVS7H/KbTXoDzlxC++41P8CqPhHAWOaBmjigAsfaPe9XDSdvPruuV52V1eEP8ykkbG0bESGh2BmJA2zZht/4Gb6ZLezs9b0KZ/b2LgAhgDsQM+b670r5qjdaA9jLOMP3ZpqfdBuOFH8+ZFGoDnIH4Gt5Yu5urkEkdskaKRbBRsyJ0sm5dcqS6XsBpFf6a3VG84j2A7o+fcNqRYg40StE5cwCYN0ggidPxtc9zkS19yQT/hMeCYJP0G3s6espXFJLqrcqrpXJEVkaRrbKcGacDNi5X1fwFQcX7fHesHnwBWg8NKl6EtpS7azEs41tCJG7S6N7MGGtZcDuUGVDwaFDCETdMhfQsVmWJq57gM+OJZuh2nw8p47HrNL3HZkOtfvjoMa+bRDBUM4lbEfvLV189pM=", "MIME-Version": "1.0", "X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "6f923448-87b3-464d-0fd2-08d6ea7b74f3", "X-MS-Exchange-CrossTenant-originalarrivaltime": "06 Jun 2019 12:35:28.7115\n\t(UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "vabhav.sharma@nxp.com", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "VI1PR04MB4206", "Cc": "Pramod Kumar <pramod.kumar_1@nxp.com>, Pankit Garg <pankit.garg@nxp.com>,\n\tVarun Sethi <V.Sethi@nxp.com>,\n\tCamelia Alexandra Groza <camelia.groza@nxp.com>", "Subject": "[U-Boot] [PATCH v2] armv8: ls1046afrwy: Add support for LS1046AFRWY\n\tplatform", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "LS1046AFRWY board supports LS1046A family SoCs. This patch\nadd base support for this board.\nBoard support's 4GB ddr memory, i2c, micro-click module,microSD card,\nserial console,qspi nor flash,ifc nand flash,qsgmii network interface,\nusb 3.0 and serdes interface to support two x1gen3 pcie interface.\n\nSigned-off-by: Camelia Groza <camelia.groza@nxp.com>\nSigned-off-by: Madalin Bucur <madalin.bucur@nxp.com>\nSigned-off-by: Pankit Garg <pankit.garg@nxp.com>\nSigned-off-by: Pramod Kumar <pramod.kumar_1@nxp.com>\nSigned-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>\nSigned-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>\n---\nChanges in v2:\n- Incorporated review comments from Prabhakar Kushwaha\n- Removed non tfa boot support changes\n- Removed PMIC and DEEP sleep config\n- Unset CONFIG_SPI_FLASH_BAR in defconfig\n- Updated mtd-id for QSPI nor in mtdparts variable \n\n arch/arm/Kconfig | 15 ++\n arch/arm/cpu/armv8/Kconfig | 1 +\n arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c | 2 +\n arch/arm/dts/Makefile | 1 +\n arch/arm/dts/fsl-ls1046a-frwy.dts | 34 ++++\n board/freescale/ls1046afrwy/Kconfig | 17 ++\n board/freescale/ls1046afrwy/MAINTAINERS | 7 +\n board/freescale/ls1046afrwy/Makefile | 7 +\n board/freescale/ls1046afrwy/README | 76 +++++++\n board/freescale/ls1046afrwy/ddr.c | 19 ++\n board/freescale/ls1046afrwy/eth.c | 114 +++++++++++\n board/freescale/ls1046afrwy/ls1046afrwy.c | 223 +++++++++++++++++++++\n configs/ls1046afrwy_tfa_defconfig | 59 ++++++\n include/configs/ls1046a_common.h | 13 +-\n include/configs/ls1046afrwy.h | 136 +++++++++++++\n include/fm_eth.h | 12 ++\n 16 files changed, 734 insertions(+), 2 deletions(-)\n create mode 100644 arch/arm/dts/fsl-ls1046a-frwy.dts\n create mode 100644 board/freescale/ls1046afrwy/Kconfig\n create mode 100644 board/freescale/ls1046afrwy/MAINTAINERS\n create mode 100644 board/freescale/ls1046afrwy/Makefile\n create mode 100644 board/freescale/ls1046afrwy/README\n create mode 100644 board/freescale/ls1046afrwy/ddr.c\n create mode 100644 board/freescale/ls1046afrwy/eth.c\n create mode 100644 board/freescale/ls1046afrwy/ls1046afrwy.c\n create mode 100644 configs/ls1046afrwy_tfa_defconfig\n create mode 100644 include/configs/ls1046afrwy.h", "diff": "diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\r\nindex 01ff57c..d9ad32c 100644\r\n--- a/arch/arm/Kconfig\r\n+++ b/arch/arm/Kconfig\r\n@@ -1406,6 +1406,20 @@ config TARGET_LS1046ARDB\r\n \t development platform that supports the QorIQ LS1046A\r\n \t Layerscape Architecture processor.\r\n \r\n+config TARGET_LS1046AFRWY\r\n+\tbool \"Support ls1046afrwy\"\r\n+\tselect ARCH_LS1046A\r\n+\tselect ARM64\r\n+\tselect ARMV8_MULTIENTRY\r\n+\tselect BOARD_EARLY_INIT_F\r\n+\tselect BOARD_LATE_INIT\r\n+\tselect DM_SPI_FLASH if DM_SPI\r\n+\timply SCSI\r\n+\thelp\r\n+\t Support for Freescale LS1046AFRWY platform.\r\n+\t The LS1046A Freeway Board (FRWY) is a high-performance\r\n+\t development platform that supports the QorIQ LS1046A\r\n+\t Layerscape Architecture processor.\r\n config TARGET_H2200\r\n \tbool \"Support h2200\"\r\n \tselect CPU_PXA\r\n@@ -1697,6 +1711,7 @@ source \"board/freescale/ls1021aiot/Kconfig\"\r\n source \"board/freescale/ls1046aqds/Kconfig\"\r\n source \"board/freescale/ls1043ardb/Kconfig\"\r\n source \"board/freescale/ls1046ardb/Kconfig\"\r\n+source \"board/freescale/ls1046afrwy/Kconfig\"\r\n source \"board/freescale/ls1012aqds/Kconfig\"\r\n source \"board/freescale/ls1012ardb/Kconfig\"\r\n source \"board/freescale/ls1012afrdm/Kconfig\"\r\ndiff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig\r\nindex 8a97d5b..92a2b58 100644\r\n--- a/arch/arm/cpu/armv8/Kconfig\r\n+++ b/arch/arm/cpu/armv8/Kconfig\r\n@@ -107,6 +107,7 @@ config PSCI_RESET\r\n \t\t !TARGET_LS1028ARDB && !TARGET_LS1028AQDS && \\\r\n \t\t !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \\\r\n \t\t !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \\\r\n+\t\t !TARGET_LS1046AFRWY && \\\r\n \t\t !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \\\r\n \t\t !TARGET_LX2160AQDS && \\\r\n \t\t !ARCH_UNIPHIER && !TARGET_S32V234EVB\r\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c\r\nindex f8310f2..caa4862 100644\r\n--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c\r\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046a_serdes.c\r\n@@ -1,6 +1,7 @@\r\n // SPDX-License-Identifier: GPL-2.0+\r\n /*\r\n * Copyright 2016 Freescale Semiconductor, Inc.\r\n+ * Copyright 2019 NXP\r\n */\r\n \r\n #include <common.h>\r\n@@ -33,6 +34,7 @@ static struct serdes_config serdes1_cfg_tbl[] = {\r\n \t\t SGMII_FM1_DTSEC6} },\r\n \t{0x2223, {SGMII_2500_FM1_DTSEC9, SGMII_2500_FM1_DTSEC10,\r\n \t\t SGMII_2500_FM1_DTSEC5, SGMII_FM1_DTSEC6} },\r\n+\t{0x3040, {NONE, NONE, QSGMII_FM1_A, NONE} },\r\n \t{}\r\n };\r\n \r\ndiff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\r\nindex e0c54bf..fd14b3a 100644\r\n--- a/arch/arm/dts/Makefile\r\n+++ b/arch/arm/dts/Makefile\r\n@@ -342,6 +342,7 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \\\r\n \tfsl-ls1046a-qds-duart.dtb \\\r\n \tfsl-ls1046a-qds-lpuart.dtb \\\r\n \tfsl-ls1046a-rdb.dtb \\\r\n+\tfsl-ls1046a-frwy.dtb \\\r\n \tfsl-ls1012a-qds.dtb \\\r\n \tfsl-ls1012a-rdb.dtb \\\r\n \tfsl-ls1012a-2g5rdb.dtb \\\r\ndiff --git a/arch/arm/dts/fsl-ls1046a-frwy.dts b/arch/arm/dts/fsl-ls1046a-frwy.dts\r\nnew file mode 100644\r\nindex 0000000..3d41e3b\r\n--- /dev/null\r\n+++ b/arch/arm/dts/fsl-ls1046a-frwy.dts\r\n@@ -0,0 +1,34 @@\r\n+// SPDX-License-Identifier: GPL-2.0+ OR X11\r\n+/*\r\n+ * Device Tree Include file for NXP Layerscape-1046A family SoC.\r\n+ *\r\n+ * Copyright 2019 NXP\r\n+ *\r\n+ */\r\n+\r\n+/dts-v1/;\r\n+/include/ \"fsl-ls1046a.dtsi\"\r\n+\r\n+/ {\r\n+\tmodel = \"LS1046A FRWY Board\";\r\n+\r\n+\taliases {\r\n+\t\tspi0 = &qspi;\r\n+\t};\r\n+\r\n+};\r\n+\r\n+&qspi {\r\n+\tbus-num = <0>;\r\n+\tstatus = \"okay\";\r\n+\r\n+\tqflash0: mt25qu512abb8esf@0 {\r\n+\t\t#address-cells = <1>;\r\n+\t\t#size-cells = <1>;\r\n+\t\tcompatible = \"spi-flash\";\r\n+\t\tspi-max-frequency = <50000000>;\r\n+\t\treg = <0>;\r\n+\t};\r\n+\r\n+};\r\n+\r\ndiff --git a/board/freescale/ls1046afrwy/Kconfig b/board/freescale/ls1046afrwy/Kconfig\r\nnew file mode 100644\r\nindex 0000000..6a4c3e9\r\n--- /dev/null\r\n+++ b/board/freescale/ls1046afrwy/Kconfig\r\n@@ -0,0 +1,17 @@\r\n+\r\n+if TARGET_LS1046AFRWY\r\n+\r\n+config SYS_BOARD\r\n+\tdefault \"ls1046afrwy\"\r\n+\r\n+config SYS_VENDOR\r\n+\tdefault \"freescale\"\r\n+\r\n+config SYS_SOC\r\n+\tdefault \"fsl-layerscape\"\r\n+\r\n+config SYS_CONFIG_NAME\r\n+\tdefault \"ls1046afrwy\"\r\n+\r\n+source \"board/freescale/common/Kconfig\"\r\n+endif\r\ndiff --git a/board/freescale/ls1046afrwy/MAINTAINERS b/board/freescale/ls1046afrwy/MAINTAINERS\r\nnew file mode 100644\r\nindex 0000000..357d23e\r\n--- /dev/null\r\n+++ b/board/freescale/ls1046afrwy/MAINTAINERS\r\n@@ -0,0 +1,7 @@\r\n+LS1046AFRWY BOARD\r\n+M:\tPramod Kumar <pramod.kumar_1@nxp.com>\r\n+S:\tMaintained\r\n+F:\tboard/freescale/ls1046afrwy/\r\n+F:\tboard/freescale/ls1046afrwy/ls1046afrwy.c\r\n+F:\tinclude/configs/ls1046afrwy.h\r\n+F:\tconfigs/ls1046afrwy_tfa_defconfig\r\ndiff --git a/board/freescale/ls1046afrwy/Makefile b/board/freescale/ls1046afrwy/Makefile\r\nnew file mode 100644\r\nindex 0000000..c70f5cd\r\n--- /dev/null\r\n+++ b/board/freescale/ls1046afrwy/Makefile\r\n@@ -0,0 +1,7 @@\r\n+# SPDX-License-Identifier: GPL-2.0+\r\n+#\r\n+# Copyright 2019 NXP\r\n+\r\n+obj-y += ddr.o\r\n+obj-y += ls1046afrwy.o\r\n+obj-$(CONFIG_NET) += eth.o\r\ndiff --git a/board/freescale/ls1046afrwy/README b/board/freescale/ls1046afrwy/README\r\nnew file mode 100644\r\nindex 0000000..d7b5a77\r\n--- /dev/null\r\n+++ b/board/freescale/ls1046afrwy/README\r\n@@ -0,0 +1,76 @@\r\n+Overview\r\n+--------\r\n+The LS1046A Freeway Board (iFRWY) is a high-performance computing,\r\n+evaluation, and development platform that supports the QorIQ LS1046A\r\n+LayerScape Architecture processor. The FRWY-LS1046A provides SW development\r\n+platform for the Freescale LS1046A processor series, with a complete\r\n+debugging environment. The FRWY-LS1046A is lead-free and RoHS-compliant.\r\n+\r\n+LS1046A SoC Overview\r\n+--------------------\r\n+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A\r\n+SoC overview.\r\n+\r\n+ FRWY-LS1046A board Overview\r\n+ -----------------------\r\n+ - SERDES1 Connections, 4 lanes supporting:\r\n+ - Lane0: Unused\r\n+ - Lane1: Unused\r\n+ - Lane2: QSGMII\r\n+ - Lane3: Unused\r\n+ - SERDES2 Connections, 4 lanes supporting:\r\n+ - Lane0: Unused\r\n+ - Lane1: PCIe3 with PCIe x1 slot\r\n+ - Lane2: Unused\r\n+ - Lane3: PCIe3 with PCIe x1 slot\r\n+ - DDR Controller\r\n+ - 8GB 64bits DDR4 SDRAM. Support rates of up to 2133MT/s\r\n+ -IFC/Local Bus\r\n+ - One 512 MB NAND flash with ECC support\r\n+ - USB 3.0\r\n+ - Two Type A port\r\n+ - SDHC: connects directly to a full microSD slot\r\n+ - QSPI: 64 MB high-speed flash Memory for boot code and storage\r\n+ - 4 I2C controllers\r\n+ - UART\r\n+ - Two 4-pin serial ports at up to 115.2 Kbit/s\r\n+ - Two DB9 D-Type connectors supporting one Serial port each\r\n+ - ARM JTAG support\r\n+\r\n+Memory map from core's view\r\n+----------------------------\r\n+Start Address\t End Address\t Description\t\tSize\r\n+0x00_0000_0000 - 0x00_000F_FFFF Secure Boot ROM\t1MB\r\n+0x00_0100_0000 - 0x00_0FFF_FFFF CCSRBAR\t\t240MB\r\n+0x00_1000_0000 - 0x00_1000_FFFF OCRAM0 \t\t64KB\r\n+0x00_1001_0000 - 0x00_1001_FFFF OCRAM1 \t\t64KB\r\n+0x00_2000_0000 - 0x00_20FF_FFFF DCSR\t\t\t16MB\r\n+0x00_7E80_0000 - 0x00_7E80_FFFF IFC - NAND Flash\t64KB\r\n+0x00_7FB0_0000 - 0x00_7FB0_0FFF IFC - CPLD\t\t4KB\r\n+0x00_8000_0000 - 0x00_FFFF_FFFF DRAM1\t\t\t2GB\r\n+0x05_0000_0000 - 0x05_07FF_FFFF QMAN S/W Portal\t128M\r\n+0x05_0800_0000 - 0x05_0FFF_FFFF BMAN S/W Portal\t128M\r\n+0x08_8000_0000 - 0x09_FFFF_FFFF DRAM2\t\t\t6GB\r\n+0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1\t\t32G\r\n+0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2\t\t32G\r\n+0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3\t\t32G\r\n+\r\n+QSPI flash map:\r\n+Start Address End Address Description\t\tSize\r\n+0x00_4000_0000 - 0x00_400F_FFFF RCW + PBI + BL2\t1MB\r\n+0x00_4010_0000 - 0x00_404F_FFFF FIP Image\r\n+\t\t\t\t (Bl31 + BL32(optee.\r\n+\t\t\t\t bin) + Bl33(uboot)\r\n+\t\t\t\t + headers for secure\r\n+\t\t\t\t boot)\t\t\t4MB\r\n+0x00_4050_0000 - 0x00_405F_FFFF Boot Firmware Env\t1MB\r\n+0x00_4060_0000 - 0x00_408F_FFFF Secure boot headers\t3MB\r\n+0x00_4090_0000 - 0x00_4093_FFFF FMan ucode\t\t256KB\r\n+0x00_4094_0000 - 0x00_4097_FFFF QE/uQE firmware\t256KB\r\n+0x00_409C_0000 - 0x00_409F_FFFF Reserved\t\t256KB\r\n+0x00_4100_0000 - 0x00_43FF_FFFF FIT Image\t\t48MB\r\n+\r\n+Booting Options\r\n+---------------\r\n+a) QSPI boot\r\n+b) microSD boot\r\ndiff --git a/board/freescale/ls1046afrwy/ddr.c b/board/freescale/ls1046afrwy/ddr.c\r\nnew file mode 100644\r\nindex 0000000..daf17e0\r\n--- /dev/null\r\n+++ b/board/freescale/ls1046afrwy/ddr.c\r\n@@ -0,0 +1,19 @@\r\n+// SPDX-License-Identifier: GPL-2.0+\r\n+/*\r\n+ * Copyright 2019 NXP\r\n+ */\r\n+\r\n+#include <common.h>\r\n+#include <fsl_ddr_sdram.h>\r\n+\r\n+DECLARE_GLOBAL_DATA_PTR;\r\n+\r\n+int fsl_initdram(void)\r\n+{\r\n+\tgd->ram_size = tfa_get_dram_size();\r\n+\r\n+\tif (!gd->ram_size)\r\n+\t\tgd->ram_size = fsl_ddr_sdram_size();\r\n+\r\n+\treturn 0;\r\n+}\r\ndiff --git a/board/freescale/ls1046afrwy/eth.c b/board/freescale/ls1046afrwy/eth.c\r\nnew file mode 100644\r\nindex 0000000..9f8bd92\r\n--- /dev/null\r\n+++ b/board/freescale/ls1046afrwy/eth.c\r\n@@ -0,0 +1,114 @@\r\n+// SPDX-License-Identifier: GPL-2.0+\r\n+/*\r\n+ * Copyright 2019 NXP\r\n+ */\r\n+#include <common.h>\r\n+#include <asm/io.h>\r\n+#include <netdev.h>\r\n+#include <fm_eth.h>\r\n+#include <fsl_dtsec.h>\r\n+#include <fsl_mdio.h>\r\n+#include <malloc.h>\r\n+\r\n+#include \"../common/fman.h\"\r\n+\r\n+int board_eth_init(bd_t *bis)\r\n+{\r\n+#ifdef CONFIG_FMAN_ENET\r\n+\tstruct memac_mdio_info dtsec_mdio_info;\r\n+\tstruct mii_dev *dev;\r\n+\tu32 srds_s1;\r\n+\tstruct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);\r\n+\r\n+\tsrds_s1 = in_be32(&gur->rcwsr[4]) &\r\n+\t\t\tFSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;\r\n+\tsrds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;\r\n+\r\n+\tdtsec_mdio_info.regs =\r\n+\t\t(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;\r\n+\r\n+\tdtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;\r\n+\r\n+\t/* Register the 1G MDIO bus */\r\n+\tfm_memac_mdio_init(bis, &dtsec_mdio_info);\r\n+\r\n+\t/* QSGMII on lane B, MAC 6/5/10/1 */\r\n+\tfm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT1_PHY_ADDR);\r\n+\tfm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT2_PHY_ADDR);\r\n+\tfm_info_set_phy_address(FM1_DTSEC10, QSGMII_PORT3_PHY_ADDR);\r\n+\tfm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT4_PHY_ADDR);\r\n+\r\n+\tswitch (srds_s1) {\r\n+\tcase 0x3040:\r\n+\t\tbreak;\r\n+\tdefault:\r\n+\t\tprintf(\"Invalid SerDes protocol 0x%x for LS1046AFRWY\\n\",\r\n+\t\t srds_s1);\r\n+\t\tbreak;\r\n+\t}\r\n+\r\n+\tdev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);\r\n+\tfm_info_set_mdio(FM1_DTSEC6, dev);\r\n+\tfm_info_set_mdio(FM1_DTSEC5, dev);\r\n+\tfm_info_set_mdio(FM1_DTSEC10, dev);\r\n+\tfm_info_set_mdio(FM1_DTSEC1, dev);\r\n+\r\n+\tcpu_eth_init(bis);\r\n+#endif\r\n+\r\n+\treturn pci_eth_init(bis);\r\n+}\r\n+\r\n+#ifdef CONFIG_FMAN_ENET\r\n+int fdt_update_ethernet_dt(void *blob)\r\n+{\r\n+\tu32 srds_s1;\r\n+\tint i, prop;\r\n+\tint offset, nodeoff;\r\n+\tconst char *path;\r\n+\tstruct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);\r\n+\r\n+\tsrds_s1 = in_be32(&gur->rcwsr[4]) &\r\n+\t\t\tFSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;\r\n+\tsrds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;\r\n+\r\n+\t/* Cycle through all aliases */\r\n+\tfor (prop = 0; ; prop++) {\r\n+\t\tconst char *name;\r\n+\r\n+\t\t/* FDT might have been edited, recompute the offset */\r\n+\t\toffset = fdt_first_property_offset(blob,\r\n+\t\t\t\t\t\t fdt_path_offset(blob,\r\n+\t\t\t\t\t\t\t\t \"/aliases\")\r\n+\t\t\t\t\t\t );\r\n+\t\t/* Select property number 'prop' */\r\n+\t\tfor (i = 0; i < prop; i++)\r\n+\t\t\toffset = fdt_next_property_offset(blob, offset);\r\n+\r\n+\t\tif (offset < 0)\r\n+\t\t\tbreak;\r\n+\r\n+\t\tpath = fdt_getprop_by_offset(blob, offset, &name, NULL);\r\n+\t\tnodeoff = fdt_path_offset(blob, path);\r\n+\r\n+\t\tswitch (srds_s1) {\r\n+\t\tcase 0x3040:\r\n+\t\t\tif (!strcmp(name, \"ethernet1\"))\r\n+\t\t\t\tfdt_status_disabled(blob, nodeoff);\r\n+\t\t\tif (!strcmp(name, \"ethernet2\"))\r\n+\t\t\t\tfdt_status_disabled(blob, nodeoff);\r\n+\t\t\tif (!strcmp(name, \"ethernet3\"))\r\n+\t\t\t\tfdt_status_disabled(blob, nodeoff);\r\n+\t\t\tif (!strcmp(name, \"ethernet6\"))\r\n+\t\t\t\tfdt_status_disabled(blob, nodeoff);\r\n+\t\tbreak;\r\n+\t\tdefault:\r\n+\t\t\tprintf(\"%s:Invalid SerDes prtcl 0x%x for LS1046AFRWY\\n\",\r\n+\t\t\t __func__, srds_s1);\r\n+\t\tbreak;\r\n+\t\t}\r\n+\t}\r\n+\r\n+\treturn 0;\r\n+}\r\n+#endif\r\ndiff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c\r\nnew file mode 100644\r\nindex 0000000..41412a7\r\n--- /dev/null\r\n+++ b/board/freescale/ls1046afrwy/ls1046afrwy.c\r\n@@ -0,0 +1,223 @@\r\n+// SPDX-License-Identifier: GPL-2.0+\r\n+/*\r\n+ * Copyright 2019 NXP\r\n+ */\r\n+\r\n+#include <common.h>\r\n+#include <i2c.h>\r\n+#include <fdt_support.h>\r\n+#include <asm/io.h>\r\n+#include <asm/arch/clock.h>\r\n+#include <asm/arch/fsl_serdes.h>\r\n+#include <asm/arch/soc.h>\r\n+#include <asm/arch-fsl-layerscape/fsl_icid.h>\r\n+#include <hwconfig.h>\r\n+#include <ahci.h>\r\n+#include <mmc.h>\r\n+#include <scsi.h>\r\n+#include <fm_eth.h>\r\n+#include <fsl_csu.h>\r\n+#include <fsl_esdhc.h>\r\n+#include <fsl_sec.h>\r\n+#include <fsl_dspi.h>\r\n+\r\n+#define LS1046A_PORSR1_REG 0x1EE0000\r\n+#define BOOT_SRC_SD 0x20000000\r\n+#define BOOT_SRC_MASK\t 0xFF800000\r\n+#define BOARD_REV_GPIO\t\t13\r\n+#define USB2_SEL_MASK\t 0x00000100\r\n+\r\n+#define BYTE_SWAP_32(word) ((((word) & 0xff000000) >> 24) | \\\r\n+(((word) & 0x00ff0000) >> 8) | \\\r\n+(((word) & 0x0000ff00) << 8) | \\\r\n+(((word) & 0x000000ff) << 24))\r\n+#define SPI_MCR_REG\t0x2100000\r\n+\r\n+DECLARE_GLOBAL_DATA_PTR;\r\n+\r\n+int select_i2c_ch_pca9547(u8 ch)\r\n+{\r\n+\tint ret;\r\n+\r\n+\tret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);\r\n+\tif (ret) {\r\n+\t\tputs(\"PCA: failed to select proper channel\\n\");\r\n+\t\treturn ret;\r\n+\t}\r\n+\r\n+\treturn 0;\r\n+}\r\n+\r\n+static inline void demux_select_usb2(void)\r\n+{\r\n+\tu32 val;\r\n+\tstruct ccsr_gpio *pgpio = (void *)(GPIO3_BASE_ADDR);\r\n+\r\n+\tval = in_be32(&pgpio->gpdir);\r\n+\tval |= USB2_SEL_MASK;\r\n+\tout_be32(&pgpio->gpdir, val);\r\n+\r\n+\tval = in_be32(&pgpio->gpdat);\r\n+\tval |= USB2_SEL_MASK;\r\n+\tout_be32(&pgpio->gpdat, val);\r\n+}\r\n+\r\n+static inline void set_spi_cs_signal_inactive(void)\r\n+{\r\n+\t/* default: all CS signals inactive state is high */\r\n+\tuint mcr_val;\r\n+\tuint mcr_cfg_val = DSPI_MCR_MSTR | DSPI_MCR_PCSIS_MASK |\r\n+\t\t\t\tDSPI_MCR_CRXF | DSPI_MCR_CTXF;\r\n+\r\n+\tmcr_val = in_be32(SPI_MCR_REG);\r\n+\tmcr_val |= DSPI_MCR_HALT;\r\n+\tout_be32(SPI_MCR_REG, mcr_val);\r\n+\tout_be32(SPI_MCR_REG, mcr_cfg_val);\r\n+\tmcr_val = in_be32(SPI_MCR_REG);\r\n+\tmcr_val &= ~DSPI_MCR_HALT;\r\n+\tout_be32(SPI_MCR_REG, mcr_val);\r\n+}\r\n+\r\n+int board_early_init_f(void)\r\n+{\r\n+\tfsl_lsch2_early_init_f();\r\n+\r\n+\treturn 0;\r\n+}\r\n+\r\n+static inline uint8_t get_board_version(void)\r\n+{\r\n+\tu8 val;\r\n+\tstruct ccsr_gpio *pgpio = (void *)(GPIO2_BASE_ADDR);\r\n+\r\n+\tval = (in_le32(&pgpio->gpdat) >> BOARD_REV_GPIO) & 0x03;\r\n+\r\n+\treturn val;\r\n+}\r\n+\r\n+int checkboard(void)\r\n+{\r\n+\tstatic const char *freq[2] = {\"100.00MHZ\", \"100.00MHZ\"};\r\n+\tu32 boot_src;\r\n+\tu8 rev;\r\n+\r\n+\trev = get_board_version();\r\n+\tswitch (rev) {\r\n+\tcase 0x00:\r\n+\t\tputs(\"Board: LS1046AFRWY, Rev: A, boot from \");\r\n+\t\tbreak;\r\n+\tcase 0x01:\r\n+\t\tputs(\"Board: LS1046AFRWY, Rev: B, boot from \");\r\n+\t\tbreak;\r\n+\tdefault:\r\n+\t\tputs(\"Board: LS1046AFRWY, Rev: Unknown, boot from \");\r\n+\t\tbreak;\r\n+\t}\r\n+\tboot_src = BYTE_SWAP_32(readl(LS1046A_PORSR1_REG));\r\n+\r\n+\tif ((boot_src & BOOT_SRC_MASK) == BOOT_SRC_SD)\r\n+\t\tputs(\"SD\\n\");\r\n+\telse\r\n+\t\tputs(\"QSPI\\n\");\r\n+\tprintf(\"SD1_CLK1 = %s, SD1_CLK2 = %s\\n\", freq[0], freq[1]);\r\n+\r\n+\treturn 0;\r\n+}\r\n+\r\n+int board_init(void)\r\n+{\r\n+#ifdef CONFIG_SECURE_BOOT\r\n+\t/*\r\n+\t * In case of Secure Boot, the IBR configures the SMMU\r\n+\t * to allow only Secure transactions.\r\n+\t * SMMU must be reset in bypass mode.\r\n+\t * Set the ClientPD bit and Clear the USFCFG Bit\r\n+\t */\r\n+\tu32 val;\r\n+val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);\r\n+\tout_le32(SMMU_SCR0, val);\r\n+\tval = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);\r\n+\tout_le32(SMMU_NSCR0, val);\r\n+#endif\r\n+\r\n+#ifdef CONFIG_FSL_CAAM\r\n+\tsec_init();\r\n+#endif\r\n+\r\n+\tselect_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);\r\n+\treturn 0;\r\n+}\r\n+\r\n+int board_setup_core_volt(u32 vdd)\r\n+{\r\n+\treturn 0;\r\n+}\r\n+\r\n+void config_board_mux(void)\r\n+{\r\n+#ifdef CONFIG_HAS_FSL_XHCI_USB\r\n+\tstruct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;\r\n+\tu32 usb_pwrfault;\r\n+\t/*\r\n+\t * USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT\r\n+\t * USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA\r\n+\t */\r\n+\tout_be32(&scfg->rcwpmuxcr0, 0x3300);\r\n+#ifdef CONFIG_HAS_FSL_IIC3\r\n+\t/* IIC3 is used, configure mux to use IIC3_SCL/IIC3/SDA */\r\n+\tout_be32(&scfg->rcwpmuxcr0, 0x0000);\r\n+#endif\r\n+\tout_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);\r\n+\tusb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<\r\n+\t\t\tSCFG_USBPWRFAULT_USB3_SHIFT) |\r\n+\t\t\t(SCFG_USBPWRFAULT_DEDICATED <<\r\n+\t\t\tSCFG_USBPWRFAULT_USB2_SHIFT) |\r\n+\t\t\t(SCFG_USBPWRFAULT_SHARED <<\r\n+\t\t\tSCFG_USBPWRFAULT_USB1_SHIFT);\r\n+\tout_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);\r\n+#ifndef CONFIG_HAS_FSL_IIC3\r\n+\t/*\r\n+\t * LS1046A FRWY board has demultiplexer NX3DV42GU with GPIO3_23 as input\r\n+\t * to select I2C3_USB2_SEL_IO\r\n+\t * I2C3_USB2_SEL = 0: I2C3_SCL/SDA signals are routed to\r\n+\t * I2C3 header (default)\r\n+\t * I2C3_USB2_SEL = 1: USB2_DRVVBUS/PWRFAULT signals are routed to\r\n+\t * USB2 port\r\n+\t * programmed to select USB2 by setting GPIO3_23 output to one\r\n+\t */\r\n+\tdemux_select_usb2();\r\n+#endif\r\n+#endif\r\n+\tset_spi_cs_signal_inactive();\r\n+}\r\n+\r\n+#ifdef CONFIG_MISC_INIT_R\r\n+int misc_init_r(void)\r\n+{\r\n+\tconfig_board_mux();\r\n+\treturn 0;\r\n+}\r\n+#endif\r\n+\r\n+int ft_board_setup(void *blob, bd_t *bd)\r\n+{\r\n+\tu64 base[CONFIG_NR_DRAM_BANKS];\r\n+\tu64 size[CONFIG_NR_DRAM_BANKS];\r\n+\r\n+\t/* fixup DT for the two DDR banks */\r\n+\tbase[0] = gd->bd->bi_dram[0].start;\r\n+\tsize[0] = gd->bd->bi_dram[0].size;\r\n+\tbase[1] = gd->bd->bi_dram[1].start;\r\n+\tsize[1] = gd->bd->bi_dram[1].size;\r\n+\r\n+\tfdt_fixup_memory_banks(blob, base, size, 2);\r\n+\tft_cpu_setup(blob, bd);\r\n+\r\n+#ifdef CONFIG_SYS_DPAA_FMAN\r\n+\tfdt_fixup_fman_ethernet(blob);\r\n+#endif\r\n+\r\n+\tfdt_fixup_icid(blob);\r\n+\r\n+\treturn 0;\r\n+}\r\ndiff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig\r\nnew file mode 100644\r\nindex 0000000..32cd778\r\n--- /dev/null\r\n+++ b/configs/ls1046afrwy_tfa_defconfig\r\n@@ -0,0 +1,59 @@\r\n+CONFIG_ARM=y\r\n+CONFIG_TARGET_LS1046AFRWY=y\r\n+CONFIG_SYS_TEXT_BASE=0x82000000\r\n+CONFIG_QSPI_AHB_INIT=y\r\n+CONFIG_TFABOOT=y\r\n+CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y\r\n+CONFIG_SEC_FIRMWARE_ARMV8_PSCI=y\r\n+CONFIG_DISTRO_DEFAULTS=y\r\n+CONFIG_NR_DRAM_BANKS=2\r\n+CONFIG_FIT_VERBOSE=y\r\n+CONFIG_OF_BOARD_SETUP=y\r\n+CONFIG_BOOTDELAY=10\r\n+CONFIG_USE_BOOTARGS=y\r\n+CONFIG_BOOTARGS=\"console=ttyS0,115200 root=/dev/ram0 earlycon=uart8250,mmio,0x21c0500 mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)\"\r\n+CONFIG_MISC_INIT_R=y\r\n+CONFIG_CMD_GPT=y\r\n+CONFIG_CMD_I2C=y\r\n+CONFIG_CMD_MMC=y\r\n+CONFIG_CMD_NAND=y\r\n+CONFIG_CMD_PCI=y\r\n+CONFIG_CMD_SF=y\r\n+CONFIG_CMD_USB=y\r\n+CONFIG_CMD_CACHE=y\r\n+CONFIG_MP=y\r\n+CONFIG_MTDPARTS_DEFAULT=\"mtdparts=1550000.spi:1m(rcw),15m(u-boot),48m(kernel.itb);7e800000.flash:16m(nand_uboot),48m(nand_kernel),448m(nand_free)\"\r\n+CONFIG_OF_CONTROL=y\r\n+CONFIG_DEFAULT_DEVICE_TREE=\"fsl-ls1046a-frwy\"\r\n+CONFIG_ENV_IS_IN_MMC=y\r\n+CONFIG_ENV_IS_IN_SPI_FLASH=y\r\n+CONFIG_DM=y\r\n+CONFIG_FSL_CAAM=y\r\n+CONFIG_FSL_ESDHC=y\r\n+CONFIG_SPI_FLASH=y\r\n+# CONFIG_SPI_FLASH_BAR is not set\r\n+CONFIG_SPI_FLASH_STMICRO=y\r\n+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set\r\n+CONFIG_PHYLIB=y\r\n+CONFIG_PHY_GIGE=y\r\n+CONFIG_PHY_VITESSE=y\r\n+CONFIG_E1000=y\r\n+CONFIG_PCI=y\r\n+CONFIG_DM_PCI=y\r\n+CONFIG_DM_PCI_COMPAT=y\r\n+CONFIG_PCIE_LAYERSCAPE=y\r\n+CONFIG_SYS_NS16550=y\r\n+CONFIG_SPI=y\r\n+CONFIG_DM_SPI=y\r\n+CONFIG_FSL_QSPI=y\r\n+CONFIG_USB=y\r\n+CONFIG_DM_USB=y\r\n+CONFIG_USB_XHCI_HCD=y\r\n+CONFIG_USB_XHCI_DWC3=y\r\n+CONFIG_USB_STORAGE=y\r\n+CONFIG_DM_MMC=y\r\n+CONFIG_DM_SCSI=y\r\n+CONFIG_SATA_CEVA=y\r\n+CONFIG_SCSI_AHCI=y\r\n+CONFIG_SCSI=y\r\n+CONFIG_AHCI=y\r\ndiff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h\r\nindex 34b4756..59c43f1 100644\r\n--- a/include/configs/ls1046a_common.h\r\n+++ b/include/configs/ls1046a_common.h\r\n@@ -1,6 +1,7 @@\r\n /* SPDX-License-Identifier: GPL-2.0+ */\r\n /*\r\n * Copyright 2016 Freescale Semiconductor\r\n+ * Copyright 2019 NXP\r\n */\r\n \r\n #ifndef __LS1046A_COMMON_H\r\n@@ -202,6 +203,15 @@\r\n #include <config_distro_bootcmd.h>\r\n #endif\r\n \r\n+#if defined(CONFIG_TARGET_LS1046AFRWY)\r\n+#define LS1046A_BOOT_SRC_AND_HDR\\\r\n+\t\"boot_scripts=ls1046afrwy_boot.scr\\0\"\t\\\r\n+\t\"boot_script_hdr=hdr_ls1046afrwy_bs.out\\0\"\r\n+#else\r\n+#define LS1046A_BOOT_SRC_AND_HDR\\\r\n+\t\"boot_scripts=ls1046ardb_boot.scr\\0\"\t\\\r\n+\t\"boot_script_hdr=hdr_ls1046ardb_bs.out\\0\"\r\n+#endif\r\n #ifndef SPL_NO_MISC\r\n /* Initial environment variables */\r\n #define CONFIG_EXTRA_ENV_SETTINGS\t\t\\\r\n@@ -232,8 +242,7 @@\r\n \t\"console=ttyS0,115200\\0\" \\\r\n \t CONFIG_MTDPARTS_DEFAULT \"\\0\"\t\t\\\r\n \tBOOTENV\t\t\t\t\t\\\r\n-\t\"boot_scripts=ls1046ardb_boot.scr\\0\" \\\r\n-\t\"boot_script_hdr=hdr_ls1046ardb_bs.out\\0\"\t\\\r\n+\tLS1046A_BOOT_SRC_AND_HDR\t\t\\\r\n \t\"scan_dev_for_boot_part=\" \\\r\n \t\t\"part list ${devtype} ${devnum} devplist; \" \\\r\n \t\t\"env exists devplist || setenv devplist 1; \" \\\r\ndiff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h\r\nnew file mode 100644\r\nindex 0000000..791bb8d\r\n--- /dev/null\r\n+++ b/include/configs/ls1046afrwy.h\r\n@@ -0,0 +1,136 @@\r\n+/* SPDX-License-Identifier: GPL-2.0+ */\r\n+/*\r\n+ * Copyright 2019 NXP\r\n+ */\r\n+\r\n+#ifndef __LS1046AFRWY_H__\r\n+#define __LS1046AFRWY_H__\r\n+\r\n+#include \"ls1046a_common.h\"\r\n+\r\n+#define CONFIG_SYS_CLK_FREQ\t\t100000000\r\n+#define CONFIG_DDR_CLK_FREQ\t\t100000000\r\n+\r\n+#define CONFIG_LAYERSCAPE_NS_ACCESS\r\n+\r\n+#define CONFIG_DIMM_SLOTS_PER_CTLR 1\r\n+#define CONFIG_CHIP_SELECTS_PER_CTRL 4\r\n+\r\n+#define CONFIG_SYS_UBOOT_BASE\t\t0x40100000\r\n+\r\n+/* IFC */\r\n+#define CONFIG_FSL_IFC\r\n+/*\r\n+ * NAND Flash Definitions\r\n+ */\r\n+#define CONFIG_NAND_FSL_IFC\r\n+\r\n+#define CONFIG_SYS_NAND_BASE\t\t0x7e800000\r\n+#define CONFIG_SYS_NAND_BASE_PHYS\tCONFIG_SYS_NAND_BASE\r\n+\r\n+#define CONFIG_SYS_NAND_CSPR_EXT\t(0x0)\r\n+#define CONFIG_SYS_NAND_CSPR\t(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \\\r\n+\t\t\t\t| CSPR_PORT_SIZE_8\t\\\r\n+\t\t\t\t| CSPR_MSEL_NAND\t\\\r\n+\t\t\t\t| CSPR_V)\r\n+#define CONFIG_SYS_NAND_AMASK\tIFC_AMASK(64 * 1024)\r\n+#define CONFIG_SYS_NAND_CSOR\t(CSOR_NAND_ECC_ENC_EN\t/* ECC on encode */ \\\r\n+\t\t\t\t| CSOR_NAND_ECC_DEC_EN\t/* ECC on decode */ \\\r\n+\t\t\t\t| CSOR_NAND_ECC_MODE_4\t/* 4-bit ECC */ \\\r\n+\t\t\t\t| CSOR_NAND_RAL_3\t/* RAL = 3 Bytes */ \\\r\n+\t\t\t\t| CSOR_NAND_PGS_2K\t/* Page Size = 2K */ \\\r\n+\t\t\t\t| CSOR_NAND_SPRZ_128\t/* Spare size = 128 */ \\\r\n+\t\t\t\t| CSOR_NAND_PB(64))\t/* 64 Pages Per Block */\r\n+\r\n+#define CONFIG_SYS_NAND_ONFI_DETECTION\r\n+\r\n+#define CONFIG_SYS_NAND_FTIM0\t\t(FTIM0_NAND_TCCST(0x7) | \\\r\n+\t\t\t\t\tFTIM0_NAND_TWP(0x18) | \\\r\n+\t\t\t\t\tFTIM0_NAND_TWCHT(0x7) | \\\r\n+\t\t\t\t\tFTIM0_NAND_TWH(0xa))\r\n+#define CONFIG_SYS_NAND_FTIM1\t\t(FTIM1_NAND_TADLE(0x32) | \\\r\n+\t\t\t\t\tFTIM1_NAND_TWBE(0x39) | \\\r\n+\t\t\t\t\tFTIM1_NAND_TRR(0xe) | \\\r\n+\t\t\t\t\tFTIM1_NAND_TRP(0x18))\r\n+#define CONFIG_SYS_NAND_FTIM2\t\t(FTIM2_NAND_TRAD(0xf) | \\\r\n+\t\t\t\t\tFTIM2_NAND_TREH(0xa) | \\\r\n+\t\t\t\t\tFTIM2_NAND_TWHRE(0x1e))\r\n+#define CONFIG_SYS_NAND_FTIM3\t\t0x0\r\n+\r\n+#define CONFIG_SYS_NAND_BASE_LIST\t{ CONFIG_SYS_NAND_BASE }\r\n+#define CONFIG_SYS_MAX_NAND_DEVICE\t1\r\n+#define CONFIG_MTD_NAND_VERIFY_WRITE\r\n+\r\n+#define CONFIG_SYS_NAND_BLOCK_SIZE\t(128 * 1024)\r\n+\r\n+/* IFC Timing Params */\r\n+#define CONFIG_SYS_CSPR0_EXT\t\tCONFIG_SYS_NAND_CSPR_EXT\r\n+#define CONFIG_SYS_CSPR0\t\tCONFIG_SYS_NAND_CSPR\r\n+#define CONFIG_SYS_AMASK0\t\tCONFIG_SYS_NAND_AMASK\r\n+#define CONFIG_SYS_CSOR0\t\tCONFIG_SYS_NAND_CSOR\r\n+#define CONFIG_SYS_CS0_FTIM0\t\tCONFIG_SYS_NAND_FTIM0\r\n+#define CONFIG_SYS_CS0_FTIM1\t\tCONFIG_SYS_NAND_FTIM1\r\n+#define CONFIG_SYS_CS0_FTIM2\t\tCONFIG_SYS_NAND_FTIM2\r\n+#define CONFIG_SYS_CS0_FTIM3\t\tCONFIG_SYS_NAND_FTIM3\r\n+\r\n+/* EEPROM */\r\n+#define CONFIG_ID_EEPROM\r\n+#define CONFIG_SYS_I2C_EEPROM_NXID\r\n+#define CONFIG_SYS_EEPROM_BUS_NUM\t\t0\r\n+#define CONFIG_SYS_I2C_EEPROM_ADDR\t\t0x52\r\n+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN\t\t1\r\n+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS\t3\r\n+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS\t5\r\n+#define I2C_RETIMER_ADDR\t\t\t0x18\r\n+\r\n+/* I2C bus multiplexer */\r\n+#define I2C_MUX_PCA_ADDR_PRI\t\t\t0x77 /* Primary Mux*/\r\n+#define I2C_MUX_CH_DEFAULT\t\t\t0x1 /* Channel 0*/\r\n+#define I2C_MUX_CH_RTC\t\t\t\t0x1 /* Channel 0*/\r\n+\r\n+/* RTC */\r\n+#define RTC\r\n+#define CONFIG_SYS_I2C_RTC_ADDR\t\t0x51 /* Channel 0 I2C bus 0*/\r\n+#define CONFIG_SYS_RTC_BUS_NUM\t\t\t0\r\n+\r\n+/*\r\n+ * Environment\r\n+ */\r\n+#define CONFIG_ENV_OVERWRITE\r\n+\r\n+#define CONFIG_SYS_MMC_ENV_DEV\t\t0\r\n+\r\n+#define CONFIG_ENV_SIZE\t\t\t0x2000\t\t/* 8KB */\r\n+#define CONFIG_ENV_OFFSET\t\t0x500000\t/* 5MB */\r\n+#define CONFIG_ENV_SECT_SIZE\t\t0x40000\t\t/* 256KB */\r\n+\r\n+/* FMan */\r\n+#ifdef CONFIG_SYS_DPAA_FMAN\r\n+#define CONFIG_FMAN_ENET\r\n+\r\n+#define QSGMII_PORT1_PHY_ADDR\t\t0x1c\r\n+#define QSGMII_PORT2_PHY_ADDR\t\t0x1d\r\n+#define QSGMII_PORT3_PHY_ADDR\t\t0x1e\r\n+#define QSGMII_PORT4_PHY_ADDR\t\t0x1f\r\n+\r\n+#define FDT_SEQ_MACADDR_FROM_ENV\r\n+\r\n+#define CONFIG_ETHPRIME\t\t\t\"FM1@DTSEC3\"\r\n+\r\n+#endif\r\n+\r\n+/* QSPI device */\r\n+#ifdef CONFIG_FSL_QSPI\r\n+#define FSL_QSPI_FLASH_SIZE\t\tSZ_64M\r\n+#define FSL_QSPI_FLASH_NUM\t\t1\r\n+#endif\r\n+\r\n+#undef CONFIG_BOOTCOMMAND\r\n+#define QSPI_NOR_BOOTCOMMAND \"run distro_bootcmd; run qspi_bootcmd; \"\t\\\r\n+\t\t\t \"env exists secureboot && esbc_halt;;\"\r\n+#define SD_BOOTCOMMAND \"run distro_bootcmd;run sd_bootcmd; \"\t\\\r\n+\t\t\t \"env exists secureboot && esbc_halt;\"\r\n+\r\n+#include <asm/fsl_secure_boot.h>\r\n+\r\n+#endif /* __LS1046AFRWY_H__ */\r\ndiff --git a/include/fm_eth.h b/include/fm_eth.h\r\nindex 2e2ba75..729ad63 100644\r\n--- a/include/fm_eth.h\r\n+++ b/include/fm_eth.h\r\n@@ -1,6 +1,7 @@\r\n /* SPDX-License-Identifier: GPL-2.0+ */\r\n /*\r\n * Copyright 2009-2012 Freescale Semiconductor, Inc.\r\n+ * Copyright 2019 NXP\r\n */\r\n \r\n #ifndef __FM_ETH_H__\r\n@@ -41,8 +42,19 @@ enum fm_eth_type {\r\n \tFM_ETH_10G_E,\r\n };\r\n \r\n+/* Historically, on FMan v3 platforms, the first MDIO bus has been used for\r\n+ * Clause 22 PHYs and the second MDIO bus for 10G Clause 45 PHYs (thus the\r\n+ * TGEC name).\r\n+ *\r\n+ * On LS1046A-FRWY, the QSGMII PHY is connected to the second MDIO bus,\r\n+ * and no TGEC ports are present on-board.\r\n+ */\r\n #ifdef CONFIG_SYS_FMAN_V3\r\n+#ifdef CONFIG_TARGET_LS1046AFRWY\r\n+#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR\t(CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)\r\n+#else\r\n #define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR\t(CONFIG_SYS_FSL_FM1_ADDR + 0xfc000)\r\n+#endif\r\n #define CONFIG_SYS_FM1_TGEC_MDIO_ADDR\t(CONFIG_SYS_FSL_FM1_ADDR + 0xfd000)\r\n #if (CONFIG_SYS_NUM_FMAN == 2)\r\n #define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR\t(CONFIG_SYS_FSL_FM2_ADDR + 0xfc000)\r\n", "prefixes": [ "U-Boot", "v2" ] }