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GET /api/patches/110575/?format=api
{ "id": 110575, "url": "http://patchwork.ozlabs.org/api/patches/110575/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1313743504-20908-1-git-send-email-aneesh@ti.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1313743504-20908-1-git-send-email-aneesh@ti.com>", "list_archive_url": null, "date": "2011-08-19T08:45:04", "name": "[U-Boot] omap4: fix pad configuration settings for SDP and Panda", "commit_ref": "43de24fdc7f5715423441e6538a16afe2d4ad168", "pull_url": null, "state": "accepted", "archived": false, "hash": "782978adfecd1e3f5e3f0bf91fcfc6ef32377539", "submitter": { "id": 6298, "url": "http://patchwork.ozlabs.org/api/people/6298/?format=api", "name": "Aneesh V", "email": "aneesh@ti.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1313743504-20908-1-git-send-email-aneesh@ti.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/110575/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/110575/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Received": [ "from theia.denx.de (theia.denx.de [85.214.87.163])\n\tby ozlabs.org (Postfix) with ESMTP id 7F08CB6F6F\n\tfor <incoming@patchwork.ozlabs.org>;\n\tFri, 19 Aug 2011 18:50:38 +1000 (EST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 6330F28098;\n\tFri, 19 Aug 2011 10:50:36 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id Y7WiEagg0hxi; Fri, 19 Aug 2011 10:50:36 +0200 (CEST)", "from theia.denx.de (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id 529C72809C;\n\tFri, 19 Aug 2011 10:50:33 +0200 (CEST)", "from localhost (localhost [127.0.0.1])\n\tby theia.denx.de (Postfix) with ESMTP id D4AAE28098\n\tfor <u-boot@lists.denx.de>; Fri, 19 Aug 2011 10:50:30 +0200 (CEST)", "from theia.denx.de ([127.0.0.1])\n\tby localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024)\n\twith ESMTP id New+a3n98ski for <u-boot@lists.denx.de>;\n\tFri, 19 Aug 2011 10:50:29 +0200 (CEST)", "from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153])\n\tby theia.denx.de (Postfix) with ESMTPS id 905B72809A\n\tfor <u-boot@lists.denx.de>; Fri, 19 Aug 2011 10:50:26 +0200 (CEST)", "from dbdp20.itg.ti.com ([172.24.170.38])\n\tby devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id p7J8oLnV006662\n\t(version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO)\n\tfor <u-boot@lists.denx.de>; Fri, 19 Aug 2011 03:50:23 -0500", "from dbde71.ent.ti.com (localhost [127.0.0.1])\n\tby dbdp20.itg.ti.com (8.13.8/8.13.8) with ESMTP id p7J8oJFK025106\n\tfor <u-boot@lists.denx.de>; Fri, 19 Aug 2011 14:20:20 +0530 (IST)", "from dbdp31.itg.ti.com (172.24.170.98) by DBDE71.ent.ti.com\n\t(172.24.170.149) with Microsoft SMTP Server id 8.3.106.1;\n\tFri, 19 Aug 2011 14:20:20 +0530", "from localhost (a0393566pc.apr.dhcp.ti.com [172.24.137.55])\tby\n\tdbdp31.itg.ti.com (8.13.8/8.13.8) with ESMTP id p7J8oHsR007309;\n\tFri, 19 Aug 2011 14:20:19 +0530 (IST)" ], "X-Virus-Scanned": [ "Debian amavisd-new at theia.denx.de", "Debian amavisd-new at theia.denx.de" ], "X-policyd-weight": "NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5\n\tNOT_IN_BL_NJABL=-1.5 (only DNSBL check requested)", "From": "Aneesh V <aneesh@ti.com>", "To": "<u-boot@lists.denx.de>", "Date": "Fri, 19 Aug 2011 14:15:04 +0530", "Message-ID": "<1313743504-20908-1-git-send-email-aneesh@ti.com>", "X-Mailer": "git-send-email 1.7.0.4", "MIME-Version": "1.0", "Cc": "David Anders <x0132446@ti.com>, santosh.shilimkar@ti.com,\n\tSebastien Jan <s-jan@ti.com>", "Subject": "[U-Boot] [PATCH] omap4: fix pad configuration settings for SDP and\n\tPanda", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.9", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<http://lists.denx.de/mailman/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "u-boot-bounces@lists.denx.de", "Errors-To": "u-boot-bounces@lists.denx.de" }, "content": "Signed-off-by: Aneesh V <aneesh@ti.com>\nSigned-off-by: Sebastien Jan <s-jan@ti.com>\nSigned-off-by: David Anders <x0132446@ti.com>\n---\n board/ti/panda/panda_mux_data.h | 41 ++++++++++++++++------------------\n board/ti/sdp4430/sdp4430_mux_data.h | 9 ++-----\n 2 files changed, 22 insertions(+), 28 deletions(-)", "diff": "diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h\nindex 16cc0ad..63448b6 100644\n--- a/board/ti/panda/panda_mux_data.h\n+++ b/board/ti/panda/panda_mux_data.h\n@@ -23,8 +23,8 @@\n * Foundation, Inc., 59 Temple Place, Suite 330, Boston,\n * MA 02111-1307 USA\n */\n-#ifndef _SDP4430_MUX_DATA_H\n-#define _SDP4430_MUX_DATA_H\n+#ifndef _PANDA_MUX_DATA_H_\n+#define _PANDA_MUX_DATA_H_\n \n #include <asm/arch/mux_omap4.h>\n \n@@ -43,7 +43,7 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {\n \t{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},\t/* kpd_row7 */\n \t{GPMC_A20, (IEN | M3)},\t\t\t\t\t\t/* gpio_44 */\n \t{GPMC_A21, (M3)},\t\t\t\t\t\t/* gpio_45 */\n-\t{GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)},\t\t\t/* kpd_col6 */\n+\t{GPMC_A22, (M3)},\t\t\t\t\t\t/* gpio_46 */\n \t{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)},\t\t\t/* kpd_col7 */\n \t{GPMC_A24, (PTD | M3)},\t\t\t\t\t\t/* gpio_48 */\n \t{GPMC_A25, (PTD | M3)},\t\t\t\t\t\t/* gpio_49 */\n@@ -57,9 +57,9 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {\n \t{GPMC_NBE0_CLE, (M3)},\t\t\t\t\t\t/* gpio_59 */\n \t{GPMC_NBE1, (PTD | M3)},\t\t\t\t\t/* gpio_60 */\n \t{GPMC_WAIT0, (PTU | IEN | M3)},\t\t\t\t\t/* gpio_61 */\n-\t{GPMC_WAIT1, (IEN | M3)},\t\t\t\t\t/* gpio_62 */\n+\t{GPMC_WAIT1, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},\t/* gpio_62 */\n \t{C2C_DATA11, (PTD | M3)},\t\t\t\t\t/* gpio_100 */\n-\t{C2C_DATA12, (M1)},\t\t\t\t\t\t/* dsi1_te0 */\n+\t{C2C_DATA12, (PTU | IEN | M3)},\t\t\t\t\t/* gpio_101 */\n \t{C2C_DATA13, (PTD | M3)},\t\t\t\t\t/* gpio_102 */\n \t{C2C_DATA14, (M1)},\t\t\t\t\t\t/* dsi2_te0 */\n \t{C2C_DATA15, (PTD | M3)},\t\t\t\t\t/* gpio_104 */\n@@ -104,8 +104,8 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {\n \t{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},\t\t/* abe_mcbsp2_dr */\n \t{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},\t\t\t/* abe_mcbsp2_dx */\n \t{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},\t/* abe_mcbsp2_fsx */\n-\t{ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},\t/* abe_mcbsp1_clkx */\n-\t{ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},\t\t/* abe_mcbsp1_dr */\n+\t{ABE_MCBSP1_CLKX, (IEN | M0)},\t\t\t\t\t/* abe_mcbsp1_clkx */\n+\t{ABE_MCBSP1_DR, (IEN | M0)},\t\t\t\t\t/* abe_mcbsp1_dr */\n \t{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},\t\t\t/* abe_mcbsp1_dx */\n \t{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},\t/* abe_mcbsp1_fsx */\n \t{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},\t/* abe_pdm_ul_data */\n@@ -115,7 +115,7 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {\n \t{ABE_CLKS, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},\t/* abe_clks */\n \t{ABE_DMIC_CLK1, (M0)},\t\t\t\t\t\t/* abe_dmic_clk1 */\n \t{ABE_DMIC_DIN1, (IEN | M0)},\t\t\t\t\t/* abe_dmic_din1 */\n-\t{ABE_DMIC_DIN2, (IEN | M0)},\t\t\t\t\t/* abe_dmic_din2 */\n+\t{ABE_DMIC_DIN2, (PTU | IEN | M3)},\t\t\t\t/* gpio_121 */\n \t{ABE_DMIC_DIN3, (IEN | M0)},\t\t\t\t\t/* abe_dmic_din3 */\n \t{UART2_CTS, (PTU | IEN | M0)},\t\t\t\t\t/* uart2_cts */\n \t{UART2_RTS, (M0)},\t\t\t\t\t\t/* uart2_rts */\n@@ -141,7 +141,7 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {\n \t{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},\t/* mcspi4_cs0 */\n \t{UART4_RX, (IEN | M0)},\t\t\t\t\t\t/* uart4_rx */\n \t{UART4_TX, (M0)},\t\t\t\t\t\t/* uart4_tx */\n-\t{USBB2_ULPITLL_CLK, (PTD | IEN | M3)},\t\t\t\t/* gpio_157 */\n+\t{USBB2_ULPITLL_CLK, (IEN | M3)},\t\t\t\t/* gpio_157 */\n \t{USBB2_ULPITLL_STP, (IEN | M5)},\t\t\t\t/* dispc2_data23 */\n \t{USBB2_ULPITLL_DIR, (IEN | M5)},\t\t\t\t/* dispc2_data22 */\n \t{USBB2_ULPITLL_NXT, (IEN | M5)},\t\t\t\t/* dispc2_data21 */\n@@ -155,12 +155,12 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {\n \t{USBB2_ULPITLL_DAT7, (IEN | M5)},\t\t\t\t/* dispc2_data11 */\n \t{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)},\t\t/* gpio_169 */\n \t{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)},\t\t/* gpio_170 */\n-\t{UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)},\t\t\t/* kpd_col0 */\n+\t{UNIPRO_TX0, (PTD | IEN | M3)},\t\t\t\t\t/* gpio_171 */\n \t{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)},\t\t\t/* kpd_col1 */\n \t{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},\t\t\t/* kpd_col2 */\n \t{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},\t\t\t/* kpd_col3 */\n-\t{UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)},\t\t\t/* kpd_col4 */\n-\t{UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)},\t\t\t/* kpd_col5 */\n+\t{UNIPRO_TX2, (PTU | IEN | M3)},\t\t\t\t\t/* gpio_0 */\n+\t{UNIPRO_TY2, (PTU | IEN | M3)},\t\t\t\t\t/* gpio_1 */\n \t{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},\t/* kpd_row0 */\n \t{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},\t/* kpd_row1 */\n \t{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},\t/* kpd_row2 */\n@@ -171,13 +171,13 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {\n \t{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},\t\t/* usba0_otg_dp */\n \t{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},\t\t/* usba0_otg_dm */\n \t{FREF_CLK1_OUT, (M0)},\t\t\t\t\t\t/* fref_clk1_out */\n-\t{FREF_CLK2_OUT, (M0)},\t\t\t\t\t\t/* fref_clk2_out */\n+\t{FREF_CLK2_OUT, (PTU | IEN | M3)},\t\t\t\t/* gpio_182 */\n \t{SYS_NIRQ1, (PTU | IEN | M0)},\t\t\t\t\t/* sys_nirq1 */\n-\t{SYS_NIRQ2, (M7)},\t\t\t\t\t\t/* sys_nirq2 */\n+\t{SYS_NIRQ2, (PTU | IEN | M0)},\t\t\t\t\t/* sys_nirq2 */\n \t{SYS_BOOT0, (PTU | IEN | M3)},\t\t\t\t\t/* gpio_184 */\n \t{SYS_BOOT1, (M3)},\t\t\t\t\t\t/* gpio_185 */\n \t{SYS_BOOT2, (PTD | IEN | M3)},\t\t\t\t\t/* gpio_186 */\n-\t{SYS_BOOT3, (PTD | IEN | M3)},\t\t\t\t\t/* gpio_187 */\n+\t{SYS_BOOT3, (M3)},\t\t\t\t\t\t/* gpio_187 */\n \t{SYS_BOOT4, (M3)},\t\t\t\t\t\t/* gpio_188 */\n \t{SYS_BOOT5, (PTD | IEN | M3)},\t\t\t\t\t/* gpio_189 */\n \t{DPM_EMU0, (IEN | M0)},\t\t\t\t\t\t/* dpm_emu0 */\n@@ -212,19 +212,16 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = {\n \t{PAD0_FREF_SLICER_IN, (M0)},\t\t/* fref_slicer_in */\n \t{PAD1_FREF_CLK_IOREQ, (M0)},\t\t/* fref_clk_ioreq */\n \t{PAD0_FREF_CLK0_OUT, (M2)},\t\t/* sys_drm_msecure */\n-\t{PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)},\t/* # */\n+\t{PAD1_FREF_CLK3_REQ, M7},\t\t\t\t\t/* safe mode */\n \t{PAD0_FREF_CLK3_OUT, (M0)},\t\t/* fref_clk3_out */\n-\t{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)},\t/* # */\n-\t{PAD0_FREF_CLK4_OUT, (M0)},\t\t/* # */\n+\t{PAD1_FREF_CLK4_REQ, (PTU | M3)},\t/* led status_1 */\n+\t{PAD0_FREF_CLK4_OUT, (PTU | M3)},\t/* led status_2 */\n \t{PAD0_SYS_NRESPWRON, (M0)},\t\t/* sys_nrespwron */\n \t{PAD1_SYS_NRESWARM, (M0)},\t\t/* sys_nreswarm */\n \t{PAD0_SYS_PWR_REQ, (PTU | M0)},\t\t/* sys_pwr_req */\n \t{PAD1_SYS_PWRON_RESET, (M3)},\t\t/* gpio_wk29 */\n \t{PAD0_SYS_BOOT6, (IEN | M3)},\t\t/* gpio_wk9 */\n \t{PAD1_SYS_BOOT7, (IEN | M3)},\t\t/* gpio_wk10 */\n-\t{PAD1_FREF_CLK3_REQ, (M3)},\t\t/* gpio_wk30 */\n-\t{PAD1_FREF_CLK4_REQ, (M3)},\t\t/* gpio_wk7 */\n-\t{PAD0_FREF_CLK4_OUT, (M3)},\t\t/* gpio_wk8 */\n };\n \n-#endif /* _SDP4430_MUX_DATA_H */\n+#endif /* _PANDA_MUX_DATA_H_ */\ndiff --git a/board/ti/sdp4430/sdp4430_mux_data.h b/board/ti/sdp4430/sdp4430_mux_data.h\nindex 16cc0ad..06efaea 100644\n--- a/board/ti/sdp4430/sdp4430_mux_data.h\n+++ b/board/ti/sdp4430/sdp4430_mux_data.h\n@@ -212,19 +212,16 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = {\n \t{PAD0_FREF_SLICER_IN, (M0)},\t\t/* fref_slicer_in */\n \t{PAD1_FREF_CLK_IOREQ, (M0)},\t\t/* fref_clk_ioreq */\n \t{PAD0_FREF_CLK0_OUT, (M2)},\t\t/* sys_drm_msecure */\n-\t{PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)},\t/* # */\n+\t{PAD1_FREF_CLK3_REQ, (M3)},\t\t/* gpio_wk30 - Debug led-1 */\n \t{PAD0_FREF_CLK3_OUT, (M0)},\t\t/* fref_clk3_out */\n-\t{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)},\t/* # */\n-\t{PAD0_FREF_CLK4_OUT, (M0)},\t\t/* # */\n+\t{PAD1_FREF_CLK4_REQ, (M3)},\t\t/* gpio_wk7 - Debug led-2 */\n+\t{PAD0_FREF_CLK4_OUT, (M3)},\t\t/* gpio_wk8 - Debug led-3 */\n \t{PAD0_SYS_NRESPWRON, (M0)},\t\t/* sys_nrespwron */\n \t{PAD1_SYS_NRESWARM, (M0)},\t\t/* sys_nreswarm */\n \t{PAD0_SYS_PWR_REQ, (PTU | M0)},\t\t/* sys_pwr_req */\n \t{PAD1_SYS_PWRON_RESET, (M3)},\t\t/* gpio_wk29 */\n \t{PAD0_SYS_BOOT6, (IEN | M3)},\t\t/* gpio_wk9 */\n \t{PAD1_SYS_BOOT7, (IEN | M3)},\t\t/* gpio_wk10 */\n-\t{PAD1_FREF_CLK3_REQ, (M3)},\t\t/* gpio_wk30 */\n-\t{PAD1_FREF_CLK4_REQ, (M3)},\t\t/* gpio_wk7 */\n-\t{PAD0_FREF_CLK4_OUT, (M3)},\t\t/* gpio_wk8 */\n };\n \n #endif /* _SDP4430_MUX_DATA_H */\n", "prefixes": [ "U-Boot" ] }